1 /* $NetBSD: etsecreg.h,v 1.12 2024/11/05 22:00:30 andvar Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _POWERPC_BOOKE_ETSEC_REG_H_ 38 #define _POWERPC_BOOKE_ETSEC_REG_H_ 39 40 #define TXBD_R 0x8000 /* Ready (HW Owned) */ 41 #define TXBD_PADCRC 0x4000 /* B: Pad+CRC */ 42 #define TXBD_W 0x2000 /* B: Wrap (End of Ring) */ 43 #define TXBD_I 0x1000 /* B: Interrupt (IEVENT[TXB|TXF]) */ 44 #define TXBD_L 0x0800 /* B: Last */ 45 #define TXBD_TC 0x0400 /* B: Tx CRC. (Add CRC) */ 46 #define TXBD_PRE 0x0200 /* B: custom preamble */ 47 #define TXBD_DEF TXBD_PRE /* A: transmit deferred */ 48 #define TXBD_HFE 0x0080 /* B: Huge Frame Enable */ 49 #define TXBD_LC TXBD_HFE /* A: Late Coll */ 50 #define TXBD_CF 0x0040 /* B: Control Frame */ 51 #define TXBD_RL TXBD_CF /* A: Tx Limit */ 52 #define TXBD_RC 0x003c /* A: Retry Count */ 53 #define TXBD_TOE 0x0002 /* B: TOE frame */ 54 #define TXBD_UN TXBD_TOE /* A: Underrun */ 55 #define TXBD_TR 0x0001 /* A: Truncation */ 56 #define TXBD_ERRORS (TXBD_LC|TXBD_RL|TXBD_UN|TXBD_TR) 57 58 struct txbd { 59 uint16_t txbd_flags; 60 uint16_t txbd_len; 61 uint32_t txbd_bufptr; 62 }; 63 64 #define TXFCB_VLN 0x8000 /* VLaN control word valid */ 65 #define TXFCB_IP 0x4000 /* Layer 3 header is an IP header */ 66 #define TXFCB_IP6 0x2000 /* IP Header is IPv6 */ 67 #define TXFCB_TUP 0x1000 /* Layer 4 is TCP or UDP */ 68 #define TXFCB_UDP 0x0800 /* UDP at layer 4 */ 69 #define TXFCB_CIP 0x0400 /* Checksum IP header enable */ 70 #define TXFCB_CTU 0x0200 /* Checksum TCP or UDP header enable */ 71 #define TXFCB_NPH 0x0100 /* No std Pseudo-Header checksum, use phcs */ 72 73 struct txfcb { 74 uint16_t txfcb_flags; 75 uint8_t txfcb_l4os; /* layer 4 hdr from start of layer 3 header */ 76 uint8_t txfcb_l3os; /* layer 3 hdr from start of layer 2 header */ 77 uint16_t txfcb_phcs; /* pseudo-header checksum for NPH */ 78 uint16_t txfcb_vlctl; /* vlan control word for insertion for VLN */ 79 }; 80 81 #define RXBD_E 0x8000 /* Empty (1 = Owned by ETSEC) */ 82 #define RXBD_RO1 0x4000 /* S/W Ownership */ 83 #define RXBD_W 0x2000 /* Wrap ring. */ 84 #define RXBD_I 0x1000 /* Interrupt IEVENT[RXB|RXF] */ 85 #define RXBD_L 0x0800 /* Last in frame */ 86 #define RXBD_F 0x0400 /* First in frame */ 87 #define RXBD_M 0x0100 /* Miss (promiscuous match) */ 88 #define RXBD_BC 0x0080 /* BroadCast match */ 89 #define RXBD_MC 0x0040 /* MultiCast match */ 90 #define RXBD_LG 0x0020 /* rx LarGe frame error */ 91 #define RXBD_NO 0x0010 /* Non-octet aligned frame error */ 92 #define RXBD_SH 0x0008 /* SHort frame */ 93 #define RXBD_CR 0x0004 /* rx CRc error */ 94 #define RXBD_OV 0x0002 /* OVerrun error */ 95 #define RXBD_TR 0x0001 /* TRuncation error */ 96 #define RXBD_ERRORS 0x003f 97 98 struct rxbd { 99 uint16_t rxbd_flags; 100 uint16_t rxbd_len; 101 uint32_t rxbd_bufptr; 102 }; 103 104 #define RXFCB_VLN 0x8000 /* VLaN tag recognized */ 105 #define RXFCB_IP 0x4000 /* IP header found at layer 3 */ 106 #define RXFCB_IP6 0x2000 /* IPv6 header found */ 107 #define RXFCB_TUP 0x1000 /* TCP or UDP header found */ 108 #define RXFCB_CIP 0x0800 /* IPv4 checksum performed */ 109 #define RXFCB_CTU 0x0400 /* TCP or UDP checksum checked */ 110 #define RXFCB_EIP 0x0200 /* IPv4 header checksum error */ 111 #define RXFCB_ETU 0x0100 /* TCP or UDP header checksum error */ 112 #define RXFCB_HASH_VAL 0x0010 /* FLR_HASH value is valid */ 113 #define RXFCB_PERR 0x000c /* Parse Error */ 114 #define RXFCB_PERR_L3 0x0008 /* L3 Parse Error */ 115 116 struct rxfcb { 117 uint16_t rxfcb_flags; 118 uint8_t rxfcb_rq; /* receive queue index */ 119 uint8_t rxfcb_pro; /* IP Protocol received */ 120 uint16_t rxfcb_flr_hash; /* filer hash value */ 121 uint16_t rxfcb_vlctl; /* VLAN control field */ 122 }; 123 124 /* 0x000-0x0ff eTSEC general control/status registers */ 125 #define TSEC_ID 0x000 /* Controller ID register */ 126 #define TSEC_ID2 0x004 /* Controller ID register */ 127 #define IEVENT 0x010 /* Interrupt event register */ 128 #define IEVENT_BABR __PPCBIT(0) /* babbling receive error */ 129 #define IEVENT_RXC __PPCBIT(1) /* receive control interrupt */ 130 #define IEVENT_BSY __PPCBIT(2) /* busy condition interrupt */ 131 #define IEVENT_EBERR __PPCBIT(3) /* internal bus error */ 132 #define IEVENT_MSR0 __PPCBIT(5) /* MIB counter overflow */ 133 #define IEVENT_GTSC __PPCBIT(6) /* graceful transmit stop complete */ 134 #define IEVENT_BABT __PPCBIT(7) /* babbing transmit error */ 135 #define IEVENT_TXC __PPCBIT(8) /* transmit control interrupt */ 136 #define IEVENT_TXE __PPCBIT(9) /* transmit error */ 137 #define IEVENT_TXB __PPCBIT(10) /* transmit buffer */ 138 #define IEVENT_TXF __PPCBIT(11) /* transmit frame interrupt */ 139 #define IEVENT_LC __PPCBIT(13) /* late collision */ 140 #define IEVENT_CRL __PPCBIT(14) /* collision retry limit */ 141 #define IEVENT_XFUN __PPCBIT(15) /* transmit fifo underrun */ 142 #define IEVENT_RXB __PPCBIT(16) /* receive buffer */ 143 #define IEVENT_TWK __PPCBIT(19) /* timer wakeup */ 144 #define IEVENT_MAG __PPCBIT(20) /* magic packet detected */ 145 #define IEVENT_MMRD __PPCBIT(21) /* MMI management read complete */ 146 #define IEVENT_MMWR __PPCBIT(22) /* MMI management write complete */ 147 #define IEVENT_GRSC __PPCBIT(23) /* graceful receive stop complete */ 148 #define IEVENT_RXF __PPCBIT(24) /* receive frame interrupt */ 149 #define IEVENT_FGPI __PPCBIT(27) /* filer generated general purpose interrupt */ 150 #define IEVENT_FIR __PPCBIT(28) /* receive queue filer is invalid */ 151 #define IEVENT_FIQ __PPCBIT(29) /* filed frame to invalid receive queue */ 152 #define IEVENT_DPE __PPCBIT(30) /* internal data parity error */ 153 #define IEVENT_PERR __PPCBIT(31) /* Receive parse error for TOE */ 154 #define IMASK 0x014 /* Interrupt mask register */ 155 #define EDIS 0x018 /* error disabled register */ 156 #define EMAPG 0x01c /* group error mapping register */ 157 #define ECNTRL 0x020 /* ethernet control register */ 158 #define ECNTRL_FIFM __PPCBIT(16) /* FIFO mode enable */ 159 #define ECNTRL_CLRCNT __PPCBIT(17) /* Clear all MIB counters */ 160 #define ECNTRL_AUTOZ __PPCBIT(18) /* Auto zero MIB counter on read */ 161 #define ECNTRL_STEN __PPCBIT(19) /* MIB Statistics Enabled */ 162 #define ECNTRL_GMIIM __PPCBIT(25) /* GMII Interface Mode */ 163 #define ECNTRL_TBIM __PPCBIT(26) /* Ten-Bit Interface Mode */ 164 #define ECNTRL_RPM __PPCBIT(27) /* Reduced Pin Mode */ 165 #define ECNTRL_R100M __PPCBIT(28) /* RGMII/RMII 100 Mode */ 166 #define ECNTRL_RMM __PPCBIT(29) /* Reduced Pin Mode for 10/100 */ 167 #define ECNTRL_SGMIIM __PPCBIT(30) /* SGMII Interface Mode */ 168 #define ECNTRL_DEFAULT ECNTRL_STEN 169 170 #define PTV 0x028 /* Pause time value register */ 171 #define DMACTRL 0x02c /* DMA control register */ 172 #define DMACTRL_LE __PPCBIT(16) /* Little Endian Descriptor Mode */ 173 #define DMACTRL_TDSEN __PPCBIT(24) /* TX Data Snoop enable */ 174 #define DMACTRL_TBDSEN __PPCBIT(25) /* TxBD Data Snoop enable */ 175 #define DMACTRL_GRS __PPCBIT(27) /* graceful receive stop */ 176 #define DMACTRL_GTS __PPCBIT(28) /* graceful transmit stop */ 177 #define DMACTRL_TOD __PPCBIT(29) /* Transmit On Demand for TxBD ring 0 */ 178 #define DMACTRL_WWR __PPCBIT(30) /* Write With Response */ 179 #define DMACTRL_WOP __PPCBIT(31) /* Wait or pool for TxBD ring 0 */ 180 #define DMACTRL_DEFAULT (DMACTRL_WOP|DMACTRL_WWR|DMACTRL_TDSEN|DMACTRL_TBDSEN) 181 182 #define TBIPA 0x030 /* TBI phy address register */ 183 184 /* 0x100-0x2ff eTSEC transmit control/status registers */ 185 186 #define TCTRL 0x100 /* Transmit control register */ 187 #define TCTRL_IPCSEN __PPCBIT(17) /* IP header checksum generation enable */ 188 #define TCTRL_TUCSEN __PPCBIT(18) /* TCP/UDP header checksum generation enable */ 189 #define TCTRL_VLINS __PPCBIT(19) /* VLAN tag insertion */ 190 #define TCTRL_THDF __PPCBIT(29) /* Transmit half duplex */ 191 #define TCTRL_RFC_PAUSE __PPCBIT(27) /* receive flow control pause frame */ 192 #define TCTRL_TFC_PAUSE __PPCBIT(28) /* transmit flow control pause frame */ 193 #define TCTRL_TXSCHED __PPCBITS(29,30) /* transmit ring scheduling algorithm */ 194 #define TCTRL_TXSCHED_SINGLE __SHIFTIN(0,TCTRL_TXSCHED) 195 #define TCTRL_TXSCHED_PRIO __SHIFTIN(1,TCTRL_TXSCHED) 196 #define TCTRL_TXSCHED_MWRR __SHIFTIN(2,TCTRL_TXSCHED) 197 198 #define TSTAT 0x104 /* Transmit status register */ 199 #define TSTAT_THLT0 __PPCBIT(0) /* transmit halt of ring 0 */ 200 #define TSTAT_THLT1 __PPCBIT(1) 201 #define TSTAT_THLT2 __PPCBIT(2) 202 #define TSTAT_THLT3 __PPCBIT(3) 203 #define TSTAT_THLT4 __PPCBIT(4) 204 #define TSTAT_THLT5 __PPCBIT(5) 205 #define TSTAT_THLT6 __PPCBIT(6) 206 #define TSTAT_THLT7 __PPCBIT(7) 207 #define TSTAT_THLTn(n) (TSTAT_THLT0 >> (n)) 208 #define TSTAT_THLT __PPCBITS(0,7) 209 #define TSTAT_TXF0 __PPCBIT(16) /* transmit frame event occurred on ring 0 */ 210 #define TSTAT_TXF1 __PPCBIT(17) 211 #define TSTAT_TXF2 __PPCBIT(18) 212 #define TSTAT_TXF3 __PPCBIT(19) 213 #define TSTAT_TXF4 __PPCBIT(20) 214 #define TSTAT_TXF5 __PPCBIT(21) 215 #define TSTAT_TXF6 __PPCBIT(22) 216 #define TSTAT_TXF7 __PPCBIT(23) 217 #define TSTAT_TXF __PPCBITS(16,23) 218 #define TSTAT_TXFn(n) (TSTAT_TXF0 >> (n)) 219 #define DFVLAN 0x108 /* Default VLAN control word [TSEC3] */ 220 #define TXIC 0x110 /* Transmit interrupt coalescing register */ 221 #define TXIC_ICEN __PPCBIT(0) /* Interrupt coalescing enable */ 222 #define TXIC_ICCS __PPCBIT(1) /* Interrupt coalescing timer clock source */ 223 #define TXIC_ICCS_ETSEC 0 /* eTSEC Tx interface clocks */ 224 #define TXIC_ICCS_SYSTEM TXIC_ICCS /* system clocks */ 225 #define TXIC_ICFT __PPCBITS(3,10) 226 #define TXIC_ICFT_SET(n) __SHIFTIN((n),TXIC_ICFT) 227 #define TXIC_ICTT __PPCBITS(16,31) 228 #define TXIC_ICTT_SET(n) __SHIFTIN((n),TXIC_ICTT) 229 #define TQUEUE 0x114 /* Transmit queue control register [TSEC3] */ 230 #define TQUEUE_EN0 __PPCBIT(16) /* transmit ring enabled */ 231 #define TQUEUE_EN1 __PPCBIT(17) 232 #define TQUEUE_EN2 __PPCBIT(18) 233 #define TQUEUE_EN3 __PPCBIT(19) 234 #define TQUEUE_EN4 __PPCBIT(20) 235 #define TQUEUE_EN5 __PPCBIT(21) 236 #define TQUEUE_EN6 __PPCBIT(22) 237 #define TQUEUE_EN7 __PPCBIT(23) 238 #define TQUEUE_EN __PPCBITS(16,23) 239 #define TQUEUE_ENn(n) (TQUEUE_EN0 >> (n)) 240 #define TR03WT 0x140 /* TxBD Rings 0-3 round-robin weightings [TSEC3] */ 241 #define TR47WT 0x144 /* TxBD Rings 4-7 round-robin weightings [TSEC3] */ 242 #define TBDBPH 0x180 /* Tx data buffer pointer high bits [TSEC3] */ 243 #define TBPTR0 0x184 /* TxBD pointer for ring 0 */ 244 #define TBPTR1 0x18C /* TxBD pointer for ring 1 [TSEC3] */ 245 #define TBPTR2 0x194 /* TxBD pointer for ring 2 [TSEC3] */ 246 #define TBPTR3 0x19C /* TxBD pointer for ring 3 [TSEC3] */ 247 #define TBPTR4 0x1A4 /* TxBD pointer for ring 4 [TSEC3] */ 248 #define TBPTR5 0x1AC /* TxBD pointer for ring 5 [TSEC3] */ 249 #define TBPTR6 0x1B4 /* TxBD pointer for ring 6 [TSEC3] */ 250 #define TBPTR7 0x1BC /* TxBD pointer for ring 7 [TSEC3] */ 251 #define TBPTRn(n) (TBPTR0 + 8*(n)) 252 #define TBASEH 0x200 /* TxBD base address high bits [TSEC3] */ 253 #define TBASE0 0x204 /* TxBD base address of ring 0 */ 254 #define TBASE1 0x20C /* TxBD base address of ring 1 [TSEC3] */ 255 #define TBASE2 0x214 /* TxBD base address of ring 2 [TSEC3] */ 256 #define TBASE3 0x21C /* TxBD base address of ring 3 [TSEC3] */ 257 #define TBASE4 0x224 /* TxBD base address of ring 4 [TSEC3] */ 258 #define TBASE5 0x22C /* TxBD base address of ring 5 [TSEC3] */ 259 #define TBASE6 0x234 /* TxBD base address of ring 6 [TSEC3] */ 260 #define TBASE7 0x23C /* TxBD base address of ring 7 [TSEC3] */ 261 #define TBASEn(n) (TBASE0 + 8*(n)) 262 #define TMR_TXTS1_ID 0x280 /* Tx time stamp identification tag (set 1) [TSEC3] */ 263 #define TMR_TXTS2_ID 0x284 /* Tx time stamp identification tag (set 2) [TSEC3] */ 264 #define TMR_TXTS1_H 0x2C0 /* Tx time stamp high (set 1) [TSEC3] */ 265 #define TMR_TXTS1_L 0x2C4 /* Tx time stamp high (set 1) [TSEC3] */ 266 #define TMR_TXTS2_H 0x2C8 /* Tx time stamp high (set 2) [TSEC3] */ 267 #define TMR_TXTS2_L 0x2CC /* Tx time stamp high (set 2) [TSEC3] */ 268 269 /* 0x300-0x4ff eTSEC receive control/status registers */ 270 271 #define RCTRL 0x300 /* Receive control register */ 272 #define RCTRL_L2OFF __PPCBITS(0,6) 273 #define RCTRL_L2OFF_SET(n) __SHIFTIN((n),RCTRL_L2OFF) 274 #define RCTRL_TS __PPCBIT(7) 275 #define RCTRL_RR __PPCBIT(10) 276 #define RCTRL_PAL __PPCBITS(11,15) 277 #define RCTRL_VLEX __PPCBIT(18) 278 #define RCTRL_FILREN __PPCBIT(19) 279 #define RCTRL_FSQEN __PPCBIT(20) 280 #define RCTRL_GHTX __PPCBIT(21) 281 #define RCTRL_IPCSEN __PPCBIT(22) 282 #define RCTRL_TUCSEN __PPCBIT(23) 283 #define RCTRL_PRSDEP __PPCBITS(24,25) 284 #define RCTRL_PRSDEP_L4 __SHIFTIN(3,RCTRL_PRSDEP) 285 #define RCTRL_PRSDEP_L3 __SHIFTIN(2,RCTRL_PRSDEP) 286 #define RCTRL_PRSDEP_L2 __SHIFTIN(1,RCTRL_PRSDEP) 287 #define RCTRL_PRSDEP_OFF __SHIFTIN(0,RCTRL_PRSDEP) 288 #define RCTRL_BC_REJ __PPCBIT(27) 289 #define RCTRL_PROM __PPCBIT(28) 290 #define RCTRL_RSF __PPCBIT(29) 291 #define RCTRL_EMEN __PPCBIT(30) 292 #define RCTRL_DEFAULT (__SHIFTIN(2, RCTRL_PAL)|RCTRL_EMEN) 293 #define RSTAT 0x304 /* Receive status register */ 294 #define RSTAT_QHLT0 __PPCBIT(8) /* receive halt of ring 0 */ 295 #define RSTAT_QHLT1 __PPCBIT(9) 296 #define RSTAT_QHLT2 __PPCBIT(10) 297 #define RSTAT_QHLT3 __PPCBIT(11) 298 #define RSTAT_QHLT4 __PPCBIT(12) 299 #define RSTAT_QHLT5 __PPCBIT(13) 300 #define RSTAT_QHLT6 __PPCBIT(14) 301 #define RSTAT_QHLT7 __PPCBIT(15) 302 #define RSTAT_QHLTn(n) (RSTAT_QHLT0 >> (n)) 303 #define RSTAT_QHLT __PPCBITS(8,15) 304 #define RSTAT_RXF0 __PPCBIT(24) /* receive frame event occurred on ring 0 */ 305 #define RSTAT_RXF1 __PPCBIT(25) 306 #define RSTAT_RXF2 __PPCBIT(26) 307 #define RSTAT_RXF3 __PPCBIT(27) 308 #define RSTAT_RXF4 __PPCBIT(28) 309 #define RSTAT_RXF5 __PPCBIT(29) 310 #define RSTAT_RXF6 __PPCBIT(30) 311 #define RSTAT_RXF7 __PPCBIT(31) 312 #define RSTAT_RXF __PPCBITS(24,31) 313 #define RSTAT_RXFn(n) (RSTAT_RXF0 >> (n)) 314 #define RXIC 0x310 /* Receive interrupt coalescing register */ 315 #define RXIC_ICEN __PPCBIT(0) /* Interrupt coalescing enable */ 316 #define RXIC_ICCS __PPCBIT(1) /* Interrupt coalescing timer clock source */ 317 #define RXIC_ICCS_ETSEC 0 /* eTSEC Rx interface clocks */ 318 #define RXIC_ICCS_SYSTEM TXIC_ICCS /* system clocks */ 319 #define RXIC_ICFT __PPCBITS(3,10) 320 #define RXIC_ICFT_SET(n) __SHIFTIN((n),TXIC_ICFT) 321 #define RXIC_ICTT __PPCBITS(16,31) 322 #define RXIC_ICTT_SET(n) __SHIFTIN((n),TXIC_ICTT) 323 #define RQUEUE 0x314 /* Receive queue control register. [TSEC3] */ 324 #define RQUEUE_EX0 __PPCBIT(8) /* data transferred by DMA to ring extracted according to ATTR register */ 325 #define RQUEUE_EX1 __PPCBIT(9) 326 #define RQUEUE_EX2 __PPCBIT(10) 327 #define RQUEUE_EX3 __PPCBIT(11) 328 #define RQUEUE_EX4 __PPCBIT(12) 329 #define RQUEUE_EX5 __PPCBIT(13) 330 #define RQUEUE_EX6 __PPCBIT(14) 331 #define RQUEUE_EX7 __PPCBIT(15) 332 #define RQUEUE_EXn(n) (RQUEUE_EX0 >> (n)) 333 #define RQUEUE_EX __PPCBITS(8,15) 334 #define RQUEUE_EN0 __PPCBIT(24) /* ring is queried for reception */ 335 #define RQUEUE_EN1 __PPCBIT(25) 336 #define RQUEUE_EN2 __PPCBIT(26) 337 #define RQUEUE_EN3 __PPCBIT(27) 338 #define RQUEUE_EN4 __PPCBIT(28) 339 #define RQUEUE_EN5 __PPCBIT(29) 340 #define RQUEUE_EN6 __PPCBIT(30) 341 #define RQUEUE_EN7 __PPCBIT(31) 342 #define RQUEUE_EN __PPCBITS(24,31) 343 #define RQUEUE_ENn(n) (RQUEUE_EN0 >> (n)) 344 #define RIR0 0x318 /* Ring mapping register 0 */ 345 #define RIR1 0x31c /* Ring mapping register 1 */ 346 #define RIR2 0x320 /* Ring mapping register 2 */ 347 #define RIR3 0x324 /* Ring mapping register 3 */ 348 #define RIRn(n) (RIR0 + 4*(n)) 349 #define RBIFX 0x330 /* Receive bit field extract control register [TSEC3] */ 350 #define RQFAR 0x334 /* Receive queue filing table address register [TSEC3] */ 351 #define RQFCR 0x338 /* Receive queue filing table control register [TSEC3] */ 352 #define RQFCR_GPI __PPCBIT(0) /* General purpose interrupt */ 353 #define RQFCR_HASHTBL __PPCBITS(12,14) /* Select between filer Q value and RIR fileds. */ 354 #define RQFCR_HASHTBL_Q __SHIFTIN(0,RQFCR_HASHTBL) 355 #define RQFCR_HASHTBL_0 __SHIFTIN(1,RQFCR_HASHTBL) 356 #define RQFCR_HASHTBL_1 __SHIFTIN(2,RQFCR_HASHTBL) 357 #define RQFCR_HASHTBL_2 __SHIFTIN(3,RQFCR_HASHTBL) 358 #define RQFCR_HASHTBL_3 __SHIFTIN(4,RQFCR_HASHTBL) 359 #define RQFCR_HASH __PPCBIT(15) /* Include parser results in hash */ 360 #define RQFCR_QUEUE __PPCBITS(16,21) /* Receive queue index */ 361 #define RQFCR_QUEUE_SET(n) __SHIFTIN((n),RQFCR_QUEUE) 362 #define RQFCR_CLE __PPCBIT(22) /* Cluster entry/exit */ 363 #define RQFCR_REJ __PPCBIT(23) /* Reject frame */ 364 #define RQFCR_AND __PPCBIT(24) /* AND, in combination with CLE, REJ, and PID match */ 365 #define RQFCR_CMP __PPCBITS(25,26) /* Comparison operation to perform on the RQPROP entry at this index when PID > 0 */ 366 #define RQFCR_CMP_EXACT __SHIFTIN(0,RQFCR_CMP) 367 #define RQFCR_CMP_MATCH __SHIFTIN(1,RQFCR_CMP) 368 #define RQFCR_CMP_NOEXACT __SHIFTIN(2,RQFCR_CMP) 369 #define RQFCR_CMP_NOMATCH __SHIFTIN(3,RQFCR_CMP) 370 #define RQFCR_PID __PPCBITS(28,31) 371 #define RQFCR_PID_MASK 0 372 #define RQFCR_PID_PARSE 1 373 #define RQFCR_PID_ARB 2 374 #define RQFCR_PID_DAH 3 375 #define RQFCR_PID_DAL 4 376 #define RQFCR_PID_SAH 5 377 #define RQFCR_PID_SAL 6 378 #define RQFCR_PID_ETY 7 379 #define RQFCR_PID_VID 8 380 #define RQFCR_PID_PRI 9 381 #define RQFCR_PID_TOS 10 382 #define RQFCR_PID_L4P 11 383 #define RQFCR_PID_DIA 12 384 #define RQFCR_PID_SIA 13 385 #define RQFCR_PID_DPT 14 386 #define RQFCR_PID_SPT 15 387 #define RQFPR 0x33C /* Receive queue filing table property register [TSEC3] */ 388 #define RQFPR_PID1_AR __PPCBIT(14) /* ARP response */ 389 #define RQFPR_PID1_ARQ __PPCBIT(15) /* ARP request */ 390 #define RQFPR_PID1_EBC __PPCBIT(16) /* destination Ethernet address is to the broadcast address */ 391 #define RQFPR_PID1_VLN __PPCBIT(17) /* VLAN tag */ 392 #define RQFPR_PID1_CFI __PPCBIT(18) /* Canonical Format Indicator */ 393 #define RQFPR_PID1_JUM __PPCBIT(19) /* Jumbo Ethernet frame */ 394 #define RQFPR_PID1_IPF __PPCBIT(20) /* fragmented IPv4 or IPv6 header */ 395 #define RQFPR_PID1_IP4 __PPCBIT(22) /* IPv4 header */ 396 #define RQFPR_PID1_IP6 __PPCBIT(23) /* IPv6 header */ 397 #define RQFPR_PID1_ICC __PPCBIT(24) /* IPv4 header checksum */ 398 #define RQFPR_PID1_ICV __PPCBIT(25) /* IPv4 header checksum was verified correct */ 399 #define RQFPR_PID1_TCP __PPCBIT(26) /* TCP header */ 400 #define RQFPR_PID1_UDP __PPCBIT(27) /* UDP header */ 401 #define RQFPR_PID1_PER __PPCBIT(30) /* parse error */ 402 #define RQFPR_PID1_EER __PPCBIT(31) /* Ethernet framing error */ 403 #define MRBLR 0x340 /* Maximum receive buffer length register */ 404 #define RBDBPH 0x380 /* Rx data buffer pointer high bits [TSEC3] */ 405 #define RBPTR0 0x384 /* RxBD pointer for ring 0 */ 406 #define RBPTR1 0x38C /* RxBD pointer for ring 1 [TSEC3] */ 407 #define RBPTR2 0x394 /* RxBD pointer for ring 2 [TSEC3] */ 408 #define RBPTR3 0x39C /* RxBD pointer for ring 3 [TSEC3] */ 409 #define RBPTR4 0x3A4 /* RxBD pointer for ring 4 [TSEC3] */ 410 #define RBPTR5 0x3AC /* RxBD pointer for ring 5 [TSEC3] */ 411 #define RBPTR6 0x3B4 /* RxBD pointer for ring 6 [TSEC3] */ 412 #define RBPTR7 0x3BC /* RxBD pointer for ring 7 [TSEC3] */ 413 #define RBPTRn(n) (RBPTR0 + 8*(n)) 414 #define RBASEH 0x400 /* RxBD base address high bits [TSEC3] */ 415 #define RBASE0 0x404 /* RxBD base address of ring 0 */ 416 #define RBASE1 0x40C /* RxBD base address of ring 1 [TSEC3] */ 417 #define RBASE2 0x414 /* RxBD base address of ring 2 [TSEC3] */ 418 #define RBASE3 0x41C /* RxBD base address of ring 3 [TSEC3] */ 419 #define RBASE4 0x424 /* RxBD base address of ring 4 [TSEC3] */ 420 #define RBASE5 0x42C /* RxBD base address of ring 5 [TSEC3] */ 421 #define RBASE6 0x434 /* RxBD base address of ring 6 [TSEC3] */ 422 #define RBASE7 0x43C /* RxBD base address of ring 7 [TSEC3] */ 423 #define RBASEn(n) (RBASE0 + 8*(n)) 424 #define TMR_RXTS_H 0x4C0 /* Rx timer time stamp register high [TSEC3] */ 425 #define TMR_RXTS_L 0x4C4 /* Rx timer time stamp register low [TSEC3] */ 426 427 /* 0x500-0x5ff MAC registers */ 428 429 #define MACCFG1 0x500 /* MAC configuration register 1 */ 430 #define MACCFG1_SOFT_RESET __PPCBIT(0) 431 #define MACCFG1_RESET_RX_MAC __PPCBIT(12) 432 #define MACCFG1_RESET_TX_MAC __PPCBIT(13) 433 #define MACCFG1_RESET_RX_FUNC __PPCBIT(14) 434 #define MACCFG1_RESET_TX_FUNC __PPCBIT(15) 435 #define MACCFG1_LOOPBACK __PPCBIT(23) 436 #define MACCFG1_RX_FLOW __PPCBIT(26) 437 #define MACCFG1_TX_FLOW __PPCBIT(27) 438 #define MACCFG1_SYNC_RX_EN __PPCBIT(28) 439 #define MACCFG1_RX_EN __PPCBIT(29) 440 #define MACCFG1_SYNC_TX_EN __PPCBIT(30) 441 #define MACCFG1_TX_EN __PPCBIT(31) 442 #define MACCFG2 0x504 /* MAC configuration register 2 */ 443 #define MACCFG2_PRELEN __PPCBITS(16,19) 444 #define MACCFG2_PRELEN_DEFAULT __SHIFTIN(7,MACCFG2_PRELEN) 445 #define MACCFG2_IFMODE __PPCBITS(22,23) 446 #define MACCFG2_IFMODE_MII __SHIFTIN(1,MACCFG2_IFMODE) 447 #define MACCFG2_IFMODE_GMII __SHIFTIN(2,MACCFG2_IFMODE) 448 #define MACCFG2_PRERXEN __PPCBIT(24) 449 #define MACCFG2_PRETXEN __PPCBIT(25) 450 #define MACCFG2_HG __PPCBIT(26) 451 #define MACCFG2_LENCHK __PPCBIT(27) 452 #define MACCFG2_MPEN __PPCBIT(28) 453 #define MACCFG2_PADCRC __PPCBIT(29) 454 #define MACCFG2_CRCEN __PPCBIT(30) 455 #define MACCFG2_FD __PPCBIT(31) 456 #define MACCFG2_DEFAULT (MACCFG2_FD|MACCFG2_PADCRC|MACCFG2_PRELEN_DEFAULT) 457 #define IPGIFG 0x508 /* Inter-packet/inter-frame gap register */ 458 #define HAFDUP 0x50C /* Half-duplex control */ 459 #define MAXFRM 0x510 /* Maximum frame length */ 460 #define MIIMCFG 0x520 /* MII management configuration */ 461 #define MIIMCFG_RESET __PPCBIT(0) /* Reset management */ 462 #define MIIMCFG_NOPRE __PPCBIT(27) /* Preamble suppress */ 463 #define MIIMCOM 0x524 /* MII management command */ 464 #define MIIMCOM_SCAN __PPCBIT(30) 465 #define MIIMCOM_READ __PPCBIT(31) 466 #define MIIMADD 0x528 /* MII management address */ 467 #define MIIMADD_PHY __PPCBITS(19,23) 468 #define MIIMADD_REG __PPCBITS(27,31) 469 #define MIIMCON 0x52C /* MII management control */ 470 #define MIIMSTAT 0x530 /* MII management status */ 471 #define MIIMIND 0x534 /* MII management indicator */ 472 #define MIIMIND_NOTVALID __PPCBIT(29) 473 #define MIIMIND_SCAN __PPCBIT(30) 474 #define MIIMIND_BUSY __PPCBIT(31) 475 #define IFSTAT 0x53C /* Interface status */ 476 #define MACSTNADDR1 0x540 /* MAC station address register 1 */ 477 #define MACSTNADDR2 0x544 /* MAC station address register 2 */ 478 #define MAC01ADDR1 0x548 /* MAC exact match address 1, part 1 [TSEC3] */ 479 #define MAC01ADDR2 0x54C /* MAC exact match address 1, part 2 [TSEC3] */ 480 #define MAC02ADDR1 0x550 /* MAC exact match address 2, part 1 [TSEC3] */ 481 #define MAC02ADDR2 0x554 /* MAC exact match address 2, part 2 [TSEC3] */ 482 #define MAC03ADDR1 0x558 /* MAC exact match address 3, part 1 [TSEC3] */ 483 #define MAC03ADDR2 0x55C /* MAC exact match address 3, part 2 [TSEC3] */ 484 #define MAC04ADDR1 0x560 /* MAC exact match address 4, part 1 [TSEC3] */ 485 #define MAC04ADDR2 0x564 /* MAC exact match address 4, part 2 [TSEC3] */ 486 #define MAC05ADDR1 0x568 /* MAC exact match address 5, part 1 [TSEC3] */ 487 #define MAC05ADDR2 0x56C /* MAC exact match address 5, part 2 [TSEC3] */ 488 #define MAC06ADDR1 0x570 /* MAC exact match address 6, part 1 [TSEC3] */ 489 #define MAC06ADDR2 0x574 /* MAC exact match address 6, part 2 [TSEC3] */ 490 #define MAC07ADDR1 0x578 /* MAC exact match address 7, part 1 [TSEC3] */ 491 #define MAC07ADDR2 0x57C /* MAC exact match address 7, part 2 [TSEC3] */ 492 #define MAC08ADDR1 0x580 /* MAC exact match address 8, part 1 [TSEC3] */ 493 #define MAC08ADDR2 0x584 /* MAC exact match address 8, part 2 [TSEC3] */ 494 #define MAC09ADDR1 0x588 /* MAC exact match address 9, part 1 [TSEC3] */ 495 #define MAC09ADDR2 0x58C /* MAC exact match address 9, part 2 [TSEC3] */ 496 #define MAC10ADDR1 0x590 /* MAC exact match address 10, part 1 [TSEC3] */ 497 #define MAC10ADDR2 0x594 /* MAC exact match address 10, part 2 [TSEC3] */ 498 #define MAC11ADDR1 0x598 /* MAC exact match address 11, part 1 [TSEC3] */ 499 #define MAC11ADDR2 0x59C /* MAC exact match address 11, part 2 [TSEC3] */ 500 #define MAC12ADDR1 0x5A0 /* MAC exact match address 12, part 1 [TSEC3] */ 501 #define MAC12ADDR2 0x5A4 /* MAC exact match address 12, part 2 [TSEC3] */ 502 #define MAC13ADDR1 0x5A8 /* MAC exact match address 13, part 1 [TSEC3] */ 503 #define MAC13ADDR2 0x5AC /* MAC exact match address 13, part 2 [TSEC3] */ 504 #define MAC14ADDR1 0x5B0 /* MAC exact match address 14, part 1 [TSEC3] */ 505 #define MAC14ADDR2 0x5B4 /* MAC exact match address 14, part 2 [TSEC3] */ 506 #define MAC15ADDR1 0x5B8 /* MAC exact match address 15, part 1 [TSEC3] */ 507 #define MAC15ADDR2 0x5BC /* MAC exact match address 15, part 2 [TSEC3] */ 508 #define MACnADDR1(n) (MAC01ADDR1 + 8*(n)) 509 #define MACnADDR2(n) (MAC01ADDR2 + 8*(n)) 510 511 /* 0x600-0x7ff RMON MIB registers */ 512 513 /* eTSEC Transmit and Receive Counters */ 514 #define TR64 0x680 /* Transmit and receive 64 byte frame counter */ 515 #define TR127 0x684 /* Transmit and receive 65 to 127-byte frame counter */ 516 #define TR255 0x688 /* Transmit and receive 128 to 255-byte frame counter */ 517 #define TR511 0x68C /* Transmit and receive 256 to 511-byte frame counter */ 518 #define TR1K 0x690 /* Transmit and receive 512 to 1023-byte frame counter */ 519 #define TRMAX 0x694 /* Transmit and receive 1024 to 1518-byte frame counter */ 520 #define TRMGV 0x698 /* Transmit and receive 1519 to 1522-byte good VLAN frame count */ 521 522 /* eTSEC Receive Counters Registers */ 523 #define RBYT 0x69C /* Receive byte counter */ 524 #define RPKT 0x6A0 /* Receive packet counter */ 525 #define RFCS 0x6A4 /* Receive FCS error counter */ 526 #define RMCA 0x6A8 /* Receive multicast packet counter */ 527 #define RBCA 0x6AC /* Receive broadcast packet counter */ 528 #define RXCF 0x6B0 /* Receive control frame packet counter */ 529 #define RXPF 0x6B4 /* Receive PAUSE frame packet counter */ 530 #define RXUO 0x6B8 /* Receive unknown OP code counter */ 531 #define RALN 0x6BC /* Receive alignment error counter */ 532 #define RFLR 0x6C0 /* Receive frame length error counter */ 533 #define RCDE 0x6C4 /* Receive code error counter */ 534 #define RCSE 0x6C8 /* Receive carrier sense error counter */ 535 #define RUND 0x6CC /* Receive undersize packet counter */ 536 #define ROVR 0x6D0 /* Receive oversize packet counter */ 537 #define RFRG 0x6D4 /* Receive fragments counter */ 538 #define RJBR 0x6D8 /* Receive jabber counter */ 539 #define RDRP 0x6DC /* Receive drop counter */ 540 541 /* eTSEC Transmit Counters Registers */ 542 #define TBYT 0x6E0 /* Transmit byte counter */ 543 #define TPKT 0x6E4 /* Transmit packet counter */ 544 #define TMCA 0x6E8 /* Transmit multicast packet counter */ 545 #define TBCA 0x6EC /* Transmit broadcast packet counter */ 546 #define TXPF 0x6F0 /* Transmit PAUSE control frame counter */ 547 #define TDFR 0x6F4 /* Transmit deferral packet counter */ 548 #define TEDF 0x6F8 /* Transmit excessive deferral packet counter */ 549 #define TSCL 0x6FC /* Transmit single collision packet counter */ 550 #define TMCL 0x700 /* Transmit multiple collision packet counter */ 551 #define TLCL 0x704 /* Transmit late collision packet counter */ 552 553 #define TXCL 0x708 /* Transmit excessive collision packet counter */ 554 #define TNCL 0x70C /* Transmit total collision counter */ 555 #define TDRP 0x714 /* Transmit drop frame counter */ 556 #define TJBR 0x718 /* Transmit jabber frame counter */ 557 #define TFCS 0x71C /* Transmit FCS error counter */ 558 #define TXCF 0x720 /* Transmit control frame counter */ 559 #define TOVR 0x724 /* Transmit oversize frame counter */ 560 #define TUND 0x728 /* Transmit undersize frame counter */ 561 #define TFRG 0x72C /* Transmit fragments frame counter */ 562 563 /* eTSEC Counter Control and TOE Statistics Registers */ 564 #define CAR1 0x730 /* Carry register one register 3 */ 565 #define CAR2 0x734 /* Carry register two register 3 */ 566 #define CAM1 0x738 /* Carry register one mask register */ 567 #define CAM2 0x73C /* Carry register two mask register */ 568 #define RREJ 0x740 /* Receive filter rejected packet counter [TSEC3] */ 569 570 /* 0x800-0x8ff Hash table registers */ 571 572 #define IGADDR0 0x800 /* Individual/group address register 0 */ 573 #define IGADDR1 0x804 /* Individual/group address register 1 */ 574 #define IGADDR2 0x808 /* Individual/group address register 2 */ 575 #define IGADDR3 0x80C /* Individual/group address register 3 */ 576 #define IGADDR4 0x810 /* Individual/group address register 4 */ 577 #define IGADDR5 0x814 /* Individual/group address register 5 */ 578 #define IGADDR6 0x818 /* Individual/group address register 6 */ 579 #define IGADDR7 0x81C /* Individual/group address register 7 */ 580 #define IGADDR(n) (IGADDR0 + 4*(n)) 581 582 #define GADDR0 0x880 /* Group address register 0 */ 583 #define GADDR1 0x884 /* Group address register 1 */ 584 #define GADDR2 0x888 /* Group address register 2 */ 585 #define GADDR3 0x88C /* Group address register 3 */ 586 #define GADDR4 0x890 /* Group address register 4 */ 587 #define GADDR5 0x894 /* Group address register 5 */ 588 #define GADDR6 0x898 /* Group address register 6 */ 589 #define GADDR7 0x89C /* Group address register 7 */ 590 #define GADDR(n) (GADDR0 + 4*(n)) 591 592 /* 0x900-0x9ff unused */ 593 /* 0xa00-0xaff FIFO control/status registers */ 594 595 #define FIFOCFG 0xA00 /* FIFO interface configuration register */ 596 597 /* 0xb00-0xbff DMA system registers */ 598 599 #define ATTR 0xBF8 /* Attribute register */ 600 #define ATTR_ELCWT __PPCBITS(17,18) 601 #define ATTR_ELCWT_L2 __SHIFTIN(2, ATTR_ELCWT) 602 #define ATTR_BDLWT __PPCBITS(20,21) 603 #define ATTR_BDLWT_L2 __SHIFTIN(2, ATTR_BDLWT) 604 #define ATTR_RDSEN __PPCBIT(24) 605 #define ATTR_RBDSEN __PPCBIT(25) 606 #define ATTR_DEFAULT (ATTR_ELCWT_L2|ATTR_BDLWT_L2|ATTR_RDSEN|ATTR_RBDSEN) 607 608 #define ATTRELI 0xBFC /* Attribute extract length and extract index register [TSEC3] */ 609 #define ATTRELI_EL __PPCBITS(2,12) /* extracted length */ 610 #define ATTRELI_EI __PPCBITS(18,28) /* extracted index */ 611 #define ATTRELI_DEFAULT (__SHIFTIN(72, ATTRELI_EL)) 612 613 /* 0xc00-0xc3f Lossless Flow Control registers */ 614 615 #define RQPRM0 0xC00 /* Receive Queue Parameters register 0 [TSEC3] */ 616 #define RQPRM1 0xC04 /* Receive Queue Parameters register 1 [TSEC3] */ 617 #define RQPRM2 0xC08 /* Receive Queue Parameters register 2 [TSEC3] */ 618 #define RQPRM3 0xC0C /* Receive Queue Parameters register 3 [TSEC3] */ 619 #define RQPRM4 0xC10 /* Receive Queue Parameters register 4 [TSEC3] */ 620 #define RQPRM5 0xC14 /* Receive Queue Parameters register 5 [TSEC3] */ 621 #define RQPRM6 0xC18 /* Receive Queue Parameters register 6 [TSEC3] */ 622 #define RQPRM7 0xC1C /* Receive Queue Parameters register 7 [TSEC3] */ 623 #define RQPRMn(n) (RQPRM0 + 4*(n)) 624 #define RQPRM_FBTHR __PPCBITS(0,7) 625 #define RQPRM_FBTHR_SET(n) __SHIFTIN((n),RQPRM_FBTHR) 626 #define RQPRM_LEN __PPCBITS(8,31) 627 #define RQPRM_LEN_SET(n) __SHIFTIN((n),RQPRM_LEN) 628 629 #define RFBPTR0 0xC44 /* Last Free RxBD pointer for ring 0 [TSEC3] */ 630 #define RFBPTR1 0xC4C /* Last Free RxBD pointer for ring 1 [TSEC3] */ 631 #define RFBPTR2 0xC54 /* Last Free RxBD pointer for ring 2 [TSEC3] */ 632 #define RFBPTR3 0xC58 /* Last Free RxBD pointer for ring 3 [TSEC3] */ 633 #define RFBPTR4 0xC64 /* Last Free RxBD pointer for ring 4 [TSEC3] */ 634 #define RFBPTR5 0xC6C /* Last Free RxBD pointer for ring 5 [TSEC3] */ 635 #define RFBPTR6 0xC74 /* Last Free RxBD pointer for ring 6 [TSEC3] */ 636 #define RFBPTR7 0xC7C /* Last Free RxBD pointer for ring 7 [TSEC3] */ 637 #define RFBPTRn(n) (RFBPTR0 + 4*(n)) 638 639 /* 0xc40-0xdff unused */ 640 /* 0xe00-0xeaf 1588 Hardware Assist */ 641 642 #define TMR_CTRL 0xE00 /* Timer control register [TSEC3] */ 643 #define TMR_TEVENT 0xE04 /* time stamp event register [TSEC3] */ 644 #define TMR_TEMASK 0xE08 /* Timer event mask register [TSEC3] */ 645 #define TMR_PEVENT 0xE0C /* time stamp event register [TSEC3] */ 646 #define TMR_PEMASK 0xE10 /* Timer event mask register [TSEC3] */ 647 #define TMR_STAT 0xE14 /* time stamp status register [TSEC3] */ 648 #define TMR_CNT_H 0xE18 /* timer counter high register [TSEC3] */ 649 #define TMR_CNT_L 0xE1C /* timer counter low register [TSEC3] */ 650 #define TMR_ADD 0xE20 /* Timer drift compensation addend register [TSEC3] */ 651 #define TMR_ACC 0xE24 /* Timer accumulator register [TSEC3] */ 652 #define TMR_PRSC 0xE28 /* timer prescale [TSEC3] */ 653 #define TMROFF_H 0xE30 /* Timer offset high [TSEC3] */ 654 #define TMROFF_L 0xE34 /* Timer offset low [TSEC3] */ 655 #define TMR_ALARM1_H 0xE40 /* Timer alarm 1 high register [TSEC3] */ 656 #define TMR_ALARM1_L 0xE44 /* Timer alarm 1 high register [TSEC3] */ 657 #define TMR_ALARM2_H 0xE48 /* Timer alarm 2 high register [TSEC3] */ 658 #define TMR_ALARM2_L 0xE4C /* Timer alarm 2 high register [TSEC3] */ 659 #define TMR_FIPER1 0xE80 /* Timer fixed period interval [TSEC3] */ 660 #define TMR_FIPER2 0xE84 /* Timer fixed period interval [TSEC3] */ 661 #define TMR_FIPER 0xE88 /* Timer fixed period interval [TSEC3] */ 662 #define TMR_ETTS1_H 0xEA0 /* Time stamp of general purpose external trigger [TSEC3] */ 663 #define TMR_ETTS1_L 0xEA4 /* Time stamp of general purpose external trigger [TSEC3] */ 664 #define TMR_ETTS2_H 0xEA8 /* Time stamp of general purpose external trigger [TSEC3] */ 665 #define TMR_ETTS2_L 0xEAC /* Time stamp of general purpose external trigger [TSEC3] */ 666 667 /* 0xeb0-0xeff Interrupt steering and coalescing */ 668 669 #define ISRG0 0xeb0 /* Interrupt steering register group 0 */ 670 #define ISRG1 0xeb4 /* Interrupt steering register group 1 */ 671 #define ISRGn(n) (ISRG0+4*(n)) 672 #define ISRG_RRn(n) __PPCBIT(n) 673 #define ISRG_TRn(n) __PPCBIT(8+(n)) 674 675 #define RXIC0 0xed0 /* Ring 0 Rx interrupt coalescing register */ 676 #define RXIC1 0xed4 /* Ring 1 Rx interrupt coalescing register */ 677 #define RXIC2 0xed8 /* Ring 2 Rx interrupt coalescing register */ 678 #define RXIC3 0xedc /* Ring 3 Rx interrupt coalescing register */ 679 #define RXIC4 0xee0 /* Ring 4 Rx interrupt coalescing register */ 680 #define RXIC5 0xee4 /* Ring 5 Rx interrupt coalescing register */ 681 #define RXIC6 0xee8 /* Ring 6 Rx interrupt coalescing register */ 682 #define RXIC7 0xeec /* Ring 7 Rx interrupt coalescing register */ 683 #define RXICn(n) (RXIC0+4*(n)) 684 685 #define TXIC0 0xf10 /* Ring 0 Tx interrupt coalescing register */ 686 #define TXIC1 0xf14 /* Ring 1 Tx interrupt coalescing register */ 687 #define TXIC2 0xf18 /* Ring 2 Tx interrupt coalescing register */ 688 #define TXIC3 0xf1c /* Ring 3 Tx interrupt coalescing register */ 689 #define TXIC4 0xf20 /* Ring 4 Tx interrupt coalescing register */ 690 #define TXIC5 0xf24 /* Ring 5 Tx interrupt coalescing register */ 691 #define TXIC6 0xf28 /* Ring 6 Tx interrupt coalescing register */ 692 #define TXIC7 0xf2c /* Ring 7 Tx interrupt coalescing register */ 693 #define TXICn(n) (TXIC0+4*(n)) 694 695 #endif /* _POWERPC_BOOKE_ETSECREG_H_ */ 696
Indexes created Sat Sep 20 22:09:52 GMT 2025