1 /* $NetBSD: if_axereg.h,v 1.21 2019/07/14 21:37:09 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000-2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/usb/if_axereg.h,v 1.2 2003/06/15 21:45:43 wpaul Exp $ 35 */ 36 37 /* 38 * Definitions for the ASIX Electronics AX88172 to ethernet controller. 39 */ 40 41 #include <sys/rndsource.h> 42 43 /* 44 * Vendor specific commands 45 * ASIX conveniently doesn't document the 'set NODEID' command in their 46 * datasheet (thanks a lot guys). 47 * To make handling these commands easier, I added some extra data 48 * which is decided by the axe_cmd() routine. Commands are encoded 49 * in 16 bites, with the format: LDCC. L and D are both nibbles in 50 * the high byte. L represents the data length (0 to 15) and D 51 * represents the direction (0 for vendor read, 1 for vendor write). 52 * CC is the command byte, as specified in the manual. 53 */ 54 55 #define AXE_CMD_DIR(x) (((x) & 0x0F00) >> 8) 56 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12) 57 #define AXE_CMD_CMD(x) ((x) & 0x00FF) 58 59 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002 60 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002 61 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103 62 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103 63 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104 64 65 #define AXE_CMD_MII_OPMODE_SW 0x0106 66 #define AXE_CMD_MII_READ_REG 0x2007 67 #define AXE_CMD_MII_WRITE_REG 0x2108 68 #define AXE_CMD_MII_READ_OPMODE 0x1009 69 #define AXE_CMD_MII_OPMODE_HW 0x010A 70 #define AXE_CMD_SROM_READ 0x200B 71 #define AXE_CMD_SROM_WRITE 0x010C 72 #define AXE_CMD_SROM_WR_ENABLE 0x010D 73 #define AXE_CMD_SROM_WR_DISABLE 0x010E 74 #define AXE_CMD_RXCTL_READ 0x200F 75 #define AXE_CMD_RXCTL_WRITE 0x0110 76 #define AXE_CMD_READ_IPG012 0x3011 77 #define AXE_172_CMD_WRITE_IPG0 0x0112 78 #define AXE_172_CMD_WRITE_IPG1 0x0113 79 #define AXE_172_CMD_WRITE_IPG2 0x0114 80 #define AXE_178_CMD_WRITE_IPG012 0x0112 81 #define AXE_CMD_READ_MCAST 0x8015 82 #define AXE_CMD_WRITE_MCAST 0x8116 83 #define AXE_172_CMD_READ_NODEID 0x6017 84 #define AXE_172_CMD_WRITE_NODEID 0x6118 85 #define AXE_178_CMD_READ_NODEID 0x6013 86 #define AXE_178_CMD_WRITE_NODEID 0x6114 87 #define AXE_CMD_READ_PHYID 0x2019 88 #define AXE_172_CMD_READ_MEDIA 0x101A 89 #define AXE_178_CMD_READ_MEDIA 0x201A 90 #define AXE_CMD_WRITE_MEDIA 0x011B 91 #define AXE_CMD_READ_MONITOR_MODE 0x101C 92 #define AXE_CMD_WRITE_MONITOR_MODE 0x011D 93 #define AXE_CMD_READ_GPIO 0x101E 94 #define AXE_CMD_WRITE_GPIO 0x011F 95 #define AXE_CMD_SW_RESET_REG 0x0120 96 #define AXE_CMD_SW_PHY_STATUS 0x0021 97 #define AXE_CMD_SW_PHY_SELECT 0x0122 98 99 /* AX88772A and AX88772B only. */ 100 #define AXE_CMD_READ_VLAN_CTRL 0x4027 101 #define AXE_CMD_WRITE_VLAN_CTRL 0x4028 102 103 #define AXE_772B_CMD_RXCTL_WRITE_CFG 0x012A 104 #define AXE_772B_CMD_READ_RXCSUM 0x002B 105 #define AXE_772B_CMD_WRITE_RXCSUM 0x012C 106 #define AXE_772B_CMD_READ_TXCSUM 0x002D 107 #define AXE_772B_CMD_WRITE_TXCSUM 0x012E 108 109 #define AXE_SW_RESET_CLEAR 0x00 110 #define AXE_SW_RESET_RR 0x01 111 #define AXE_SW_RESET_RT 0x02 112 #define AXE_SW_RESET_PRTE 0x04 113 #define AXE_SW_RESET_PRL 0x08 114 #define AXE_SW_RESET_BZ 0x10 115 #define AXE_SW_RESET_IPRL 0x20 116 #define AXE_SW_RESET_IPPD 0x40 117 118 /* AX88178 documentation says to always write this bit... */ 119 #define AXE_178_RESET_MAGIC 0x40 120 121 #define AXE_178_MEDIA_GMII 0x0001 122 #define AXE_MEDIA_FULL_DUPLEX 0x0002 123 #define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004 124 125 /* AX88178/88772 documentation says to always write 1 to bit 2 */ 126 #define AXE_178_MEDIA_MAGIC 0x0004 127 /* AX88772 documentation says to always write 0 to bit 3 */ 128 #define AXE_178_MEDIA_ENCK 0x0008 129 #define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010 130 #define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010 131 #define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020 132 #define AXE_178_MEDIA_JUMBO_EN 0x0040 133 #define AXE_178_MEDIA_LTPF_ONLY 0x0080 134 #define AXE_178_MEDIA_RX_EN 0x0100 135 #define AXE_178_MEDIA_100TX 0x0200 136 #define AXE_178_MEDIA_SBP 0x0800 137 #define AXE_178_MEDIA_SUPERMAC 0x1000 138 139 #define AXE_RXCMD_PROMISC 0x0001 140 #define AXE_RXCMD_ALLMULTI 0x0002 141 #define AXE_172_RXCMD_UNICAST 0x0004 142 #define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004 143 #define AXE_RXCMD_BROADCAST 0x0008 144 #define AXE_RXCMD_MULTICAST 0x0010 145 #define AXE_RXCMD_ACCEPT_RUNT 0x0040 /* AX88772B */ 146 #define AXE_RXCMD_ENABLE 0x0080 147 #define AXE_178_RXCMD_MFB_MASK 0x0300 148 #define AXE_178_RXCMD_MFB_2048 0x0000 149 #define AXE_178_RXCMD_MFB_4096 0x0100 150 #define AXE_178_RXCMD_MFB_8192 0x0200 151 #define AXE_178_RXCMD_MFB_16384 0x0300 152 #define AXE_772B_RXCMD_HDR_TYPE_0 0x0000 153 #define AXE_772B_RXCMD_HDR_TYPE_1 0x0100 154 #define AXE_772B_RXCMD_IPHDR_ALIGN 0x0200 155 #define AXE_772B_RXCMD_ADD_CHKSUM 0x0400 156 #define AXE_RXCMD_LOOPBACK 0x1000 /* AX88772A/AX88772B */ 157 158 #define AXE_PHY_SEL_PRI 1 159 #define AXE_PHY_SEL_SEC 0 160 #define AXE_PHY_TYPE_MASK 0xE0 161 #define AXE_PHY_TYPE_SHIFT 5 162 #define AXE_PHY_TYPE(x) \ 163 (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT) 164 165 #define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */ 166 #define PHY_TYPE_GIG 1 /* Gigabit PHY */ 167 #define PHY_TYPE_SPECIAL 4 /* Special case */ 168 #define PHY_TYPE_RSVD 5 /* Reserved */ 169 #define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */ 170 171 #define AXE_PHY_NO_MASK 0x1F 172 #define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK) 173 174 #define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */ 175 176 177 /* 178, 772, 772A, 172A, 772B */ 178 #define AXE_IPG0_DEFAULT 0x15 179 #define AXE_IPG1_DEFAULT 0x0c 180 #define AXE_IPG2_DEFAULT 0x12 181 182 #define AXE_GPIO0_EN 0x01 183 #define AXE_GPIO0 0x02 184 #define AXE_GPIO1_EN 0x04 185 #define AXE_GPIO1 0x08 186 #define AXE_GPIO2_EN 0x10 187 #define AXE_GPIO2 0x20 188 #define AXE_GPIO_RELOAD_EEPROM 0x80 189 190 #define AXE_PHY_MODE_MARVELL 0x00 191 #define AXE_PHY_MODE_CICADA 0x01 192 #define AXE_PHY_MODE_AGERE 0x02 193 #define AXE_PHY_MODE_CICADA_V2 0x05 194 #define AXE_PHY_MODE_AGERE_GMII 0x06 195 #define AXE_PHY_MODE_CICADA_V2_ASIX 0x09 196 #define AXE_PHY_MODE_REALTEK_8211CL 0x0C 197 #define AXE_PHY_MODE_REALTEK_8211BN 0x0D 198 #define AXE_PHY_MODE_REALTEK_8251CL 0x0E 199 #define AXE_PHY_MODE_ATTANSIC 0x40 200 201 /* AX88772A/AX88772B only. */ 202 #define AXE_SW_PHY_SELECT_EXT 0x0000 203 #define AXE_SW_PHY_SELECT_EMBEDDED 0x0001 204 #define AXE_SW_PHY_SELECT_AUTO 0x0002 205 #define AXE_SW_PHY_SELECT_SS_MII 0x0004 206 #define AXE_SW_PHY_SELECT_SS_RVRS_MII 0x0008 207 #define AXE_SW_PHY_SELECT_SS_RVRS_RMII 0x000C 208 #define AXE_SW_PHY_SELECT_SS_ENB 0x0010 209 210 #define AXE_SW_RESET_CLEAR 0x00 211 #define AXE_SW_RESET_RR 0x01 212 #define AXE_SW_RESET_RT 0x02 213 #define AXE_SW_RESET_PRTE 0x04 /* not 772b */ 214 #define AXE_SW_RESET_PRL 0x08 /* not 772b */ 215 #define AXE_SW_RESET_BZ 0x10 216 #define AXE_SW_RESET_IPRL 0x20 217 #define AXE_SW_RESET_IPPD 0x40 218 #define AXE_SW_RESET_IPOSC __BIT(7) 219 /* 772B only */ 220 #define AXE_SW_RESET_IPPSL_MASK __BITS(9,8) 221 #define AXE_SW_RESET_IPPSL_0 0 222 #define AXE_SW_RESET_IPPSL_1 1 223 #define AXE_SW_RESET_IPCOPS __BIT(10) 224 #define AXE_SW_RESET_IPCOPSC __BIT(11) 225 #define AXE_SW_RESET_AD __BIT(12) 226 #define AXE_SW_RESET_IPFPS __BIT(13) 227 #define AXE_SW_RESET_WOLLP __BIT(14) 228 229 /* AX88772A/AX88772B VLAN control. */ 230 #define AXE_VLAN_CTRL_ENB 0x00001000 231 #define AXE_VLAN_CTRL_STRIP 0x00002000 232 #define AXE_VLAN_CTRL_VID1_MASK 0x00000FFF 233 #define AXE_VLAN_CTRL_VID2_MASK 0x0FFF0000 234 235 #define AXE_RXCSUM_IP 0x0001 236 #define AXE_RXCSUM_IPVE 0x0002 237 #define AXE_RXCSUM_IPV6E 0x0004 238 #define AXE_RXCSUM_TCP 0x0008 239 #define AXE_RXCSUM_UDP 0x0010 240 #define AXE_RXCSUM_ICMP 0x0020 241 #define AXE_RXCSUM_IGMP 0x0040 242 #define AXE_RXCSUM_ICMP6 0x0080 243 #define AXE_RXCSUM_TCPV6 0x0100 244 #define AXE_RXCSUM_UDPV6 0x0200 245 #define AXE_RXCSUM_ICMPV6 0x0400 246 #define AXE_RXCSUM_IGMPV6 0x0800 247 #define AXE_RXCSUM_ICMP6V6 0x1000 248 #define AXE_RXCSUM_FOPC 0x8000 249 250 #define AXE_RXCSUM_64TE 0x0100 251 #define AXE_RXCSUM_PPPOE 0x0200 252 #define AXE_RXCSUM_RPCE 0x8000 253 254 #define AXE_TXCSUM_IP 0x0001 255 #define AXE_TXCSUM_TCP 0x0002 256 #define AXE_TXCSUM_UDP 0x0004 257 #define AXE_TXCSUM_ICMP 0x0008 258 #define AXE_TXCSUM_IGMP 0x0010 259 #define AXE_TXCSUM_ICMP6 0x0020 260 #define AXE_TXCSUM_TCPV6 0x0100 261 #define AXE_TXCSUM_UDPV6 0x0200 262 #define AXE_TXCSUM_ICMPV6 0x0400 263 #define AXE_TXCSUM_IGMPV6 0x0800 264 #define AXE_TXCSUM_ICMP6V6 0x1000 265 266 #define AXE_TXCSUM_64TE 0x0001 267 #define AXE_TXCSUM_PPPOE 0x0002 268 269 #define AXE_NOPHY 0xE0 270 #define AXE_INTPHY 0x10 271 272 #define AXE_RH1M_RXLEN_MASK 0x07ff 273 274 #define AXE_TIMEOUT 1000 275 276 #define AXE_172_BUFSZ 1536 277 #define AXE_178_MIN_BUFSZ 2048 278 #define AXE_178_MAX_BUFSZ 16384 279 280 #define AXE_MIN_FRAMELEN 60 281 #define AXE_RX_FRAMES 1 282 #define AXE_TX_FRAMES 1 283 284 #define AXE_RX_LIST_CNT 1 285 #define AXE_TX_LIST_CNT 1 286 287 #define AXE_CTL_READ 0x01 288 #define AXE_CTL_WRITE 0x02 289 290 #define AXE_CONFIG_NO 1 291 #define AXE_IFACE_IDX 0 292 293 /* EEPROM Map. */ 294 #define AXE_EEPROM_772B_NODE_ID 0x04 295 #define AXE_EEPROM_772B_PHY_PWRCFG 0x18 296 297 struct ax88772b_mfb { 298 int byte_cnt; 299 int threshold; 300 int size; 301 }; 302 #define AX88772B_MFB_2K 0 303 #define AX88772B_MFB_4K 1 304 #define AX88772B_MFB_6K 2 305 #define AX88772B_MFB_8K 3 306 #define AX88772B_MFB_16K 4 307 #define AX88772B_MFB_20K 5 308 #define AX88772B_MFB_24K 6 309 #define AX88772B_MFB_32K 7 310 311 struct axe_sframe_hdr { 312 uint16_t len; 313 #define AXE_HDR_LEN_MASK 0xFFFF 314 uint16_t ilen; 315 } __packed; 316 317 #define AXE_TX_CSUM_PSEUDO_HDR 0x4000 318 #define AXE_TX_CSUM_DIS 0x8000 319 320 /* 321 * When RX checksum offloading is enabled, AX88772B uses new RX header 322 * format and it's not compatible with previous RX header format. In 323 * addition, IP header align option should be enabled to get correct 324 * frame size including RX header. Total transferred size including 325 * the RX header is multiple of 4 and controller will pad necessary 326 * bytes if the length is not multiple of 4. 327 * This driver does not enable partial checksum feature which will 328 * compute 16bit checksum from 14th byte to the end of the frame. If 329 * this feature is enabled, computed checksum value is embedded into 330 * RX header which in turn means it uses different RX header format. 331 */ 332 struct axe_csum_hdr { 333 uint16_t len; 334 #define AXE_CSUM_HDR_LEN_MASK 0x07FF 335 #define AXE_CSUM_HDR_CRC_ERR 0x1000 336 #define AXE_CSUM_HDR_MII_ERR 0x2000 337 #define AXE_CSUM_HDR_RUNT 0x4000 338 #define AXE_CSUM_HDR_BMCAST 0x8000 339 uint16_t ilen; 340 uint16_t cstatus; 341 #define AXE_CSUM_HDR_VLAN_MASK 0x0007 342 #define AXE_CSUM_HDR_VLAN_STRIP 0x0008 343 #define AXE_CSUM_HDR_VLAN_PRI_MASK 0x0070 344 #define AXE_CSUM_HDR_L4_CSUM_ERR 0x0100 345 #define AXE_CSUM_HDR_L3_CSUM_ERR 0x0200 346 #define AXE_CSUM_HDR_L4_TYPE_UDP 0x0400 347 #define AXE_CSUM_HDR_L4_TYPE_ICMP 0x0800 348 #define AXE_CSUM_HDR_L4_TYPE_IGMP 0x0C00 349 #define AXE_CSUM_HDR_L4_TYPE_TCP 0x1000 350 #define AXE_CSUM_HDR_L4_TYPE_TCPV6 0x1400 351 #define AXE_CSUM_HDR_L4_TYPE_MASK 0x1C00 352 #define AXE_CSUM_HDR_L3_TYPE_IPV4 0x2000 353 #define AXE_CSUM_HDR_L3_TYPE_IPV6 0x4000 354 355 #ifdef AXE_APPEND_PARTIAL_CSUM 356 /* 357 * These members present only when partial checksum 358 * offloading is enabled. The checksum value is simple 359 * 16bit sum of received frame starting at offset 14 of 360 * the frame to the end of the frame excluding FCS bytes. 361 */ 362 uint16_t csum_value; 363 uint16_t dummy; 364 #endif 365 } __packed; 366 367 #define AXE_CSUM_RXBYTES(x) ((x) & AXE_CSUM_HDR_LEN_MASK) 368 369 /* 370 * The interrupt and CBW endpoints are currently unused by tthe driver. 371 */ 372 #define AXE_ENDPT_CTRL 0x0 373 #define AXE_ENDPT_INTR 0x1 374 #define AXE_ENDPT_RX 0x2 375 #define AXE_ENDPT_TX 0x3 376 #define AXx72A_ENDPT_RXCBW 0x4 /* AX88172A, and AX88772A */ 377 #define AXx72A_ENDPT_TXCBW 0x5 /* AX88172A, and AX88772A */ 378 #define AX772B_ENDPT_BOTM 0x5 /* AX88772B */ 379 #define AXE_ENDPT_MAX 0x6 380
Indexes created Mon Sep 22 21:09:42 GMT 2025