1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo1 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /* 8 * Copyright (C) 2000 - 2025, Intel Corp. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 */ 43 44 #include "acpi.h" 45 #include "accommon.h" 46 #include "acdisasm.h" 47 #include "actbinfo.h" 48 49 /* This module used for application-level code only */ 50 51 #define _COMPONENT ACPI_CA_DISASSEMBLER 52 ACPI_MODULE_NAME ("dmtbinfo1") 53 54 /* 55 * How to add a new table: 56 * 57 * - Add the C table definition to the actbl1.h or actbl2.h header. 58 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 59 * - Define the table in this file (for the disassembler). If any 60 * new data types are required (ACPI_DMT_*), see below. 61 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 62 * in acdisam.h 63 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 64 * If a simple table (with no subtables), no disassembly code is needed. 65 * Otherwise, create the AcpiDmDump* function for to disassemble the table 66 * and add it to the dmtbdump.c file. 67 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 68 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 69 * - Create a template for the new table 70 * - Add data table compiler support 71 * 72 * How to add a new data type (ACPI_DMT_*): 73 * 74 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 75 * - Add length and implementation cases in dmtable.c (disassembler) 76 * - Add type and length cases in dtutils.c (DT compiler) 77 */ 78 79 /* 80 * ACPI Table Information, used to dump formatted ACPI tables 81 * 82 * Each entry is of the form: <Field Type, Field Offset, Field Name> 83 */ 84 85 86 /******************************************************************************* 87 * 88 * AEST - ARM Error Source table. Conforms to: 89 * ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document Sep 2020 90 * 91 ******************************************************************************/ 92 93 /* Common Subtable header (one per Subtable) */ 94 95 ACPI_DMTABLE_INFO AcpiDmTableInfoAestHdr[] = 96 { 97 {ACPI_DMT_AEST, ACPI_AESTH_OFFSET (Type), "Subtable Type", 0}, 98 {ACPI_DMT_UINT16, ACPI_AESTH_OFFSET (Length), "Length", DT_LENGTH}, 99 {ACPI_DMT_UINT8, ACPI_AESTH_OFFSET (Reserved), "Reserved", 0}, 100 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeSpecificOffset), "Node Specific Offset", 0}, 101 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterfaceOffset), "Node Interface Offset", 0}, 102 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterruptOffset), "Node Interrupt Array Offset", 0}, 103 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterruptCount), "Node Interrupt Array Count", 0}, 104 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (TimestampRate), "Timestamp Rate", 0}, 105 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (Reserved1), "Reserved", 0}, 106 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (ErrorInjectionRate), "Error Injection Rate", 0}, 107 ACPI_DMT_TERMINATOR 108 }; 109 110 /* 111 * AEST subtables (nodes) 112 */ 113 114 /* 0: Processor Error */ 115 116 ACPI_DMTABLE_INFO AcpiDmTableInfoAestProcError[] = 117 { 118 {ACPI_DMT_UINT32, ACPI_AEST0_OFFSET (ProcessorId), "Processor ID", 0}, 119 {ACPI_DMT_AEST_RES, ACPI_AEST0_OFFSET (ResourceType), "Resource Type", 0}, 120 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Reserved), "Reserved", 0}, 121 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Flags), "Flags (decoded Below)", 0}, 122 {ACPI_DMT_FLAG0, ACPI_AEST0_FLAG_OFFSET (Flags, 0), "Global", 0}, 123 {ACPI_DMT_FLAG1, ACPI_AEST0_FLAG_OFFSET (Flags, 0), "Shared", 0}, 124 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Revision), "Revision", 0}, 125 {ACPI_DMT_UINT64, ACPI_AEST0_OFFSET (ProcessorAffinity), "Processor Affinity Structure", 0}, 126 ACPI_DMT_TERMINATOR 127 }; 128 129 /* 0RT: Processor Cache Resource */ 130 131 ACPI_DMTABLE_INFO AcpiDmTableInfoAestCacheRsrc[] = 132 { 133 {ACPI_DMT_UINT32, ACPI_AEST0A_OFFSET (CacheReference), "Cache Reference", 0}, 134 {ACPI_DMT_UINT32, ACPI_AEST0A_OFFSET (Reserved), "Reserved", 0}, 135 ACPI_DMT_TERMINATOR 136 }; 137 138 /* 1RT: ProcessorTLB Resource */ 139 140 ACPI_DMTABLE_INFO AcpiDmTableInfoAestTlbRsrc[] = 141 { 142 {ACPI_DMT_UINT32, ACPI_AEST0B_OFFSET (TlbLevel), "TLB Level", 0}, 143 {ACPI_DMT_UINT32, ACPI_AEST0B_OFFSET (Reserved), "Reserved", 0}, 144 ACPI_DMT_TERMINATOR 145 }; 146 147 /* 2RT: Processor Generic Resource */ 148 149 ACPI_DMTABLE_INFO AcpiDmTableInfoAestGenRsrc[] = 150 { 151 {ACPI_DMT_RAW_BUFFER, 0, "Resource", 0}, 152 ACPI_DMT_TERMINATOR 153 }; 154 155 /* 1: Memory Error */ 156 157 ACPI_DMTABLE_INFO AcpiDmTableInfoAestMemError[] = 158 { 159 {ACPI_DMT_UINT32, ACPI_AEST1_OFFSET (SratProximityDomain), "Srat Proximity Domain", 0}, 160 ACPI_DMT_TERMINATOR 161 }; 162 163 /* 2: Smmu Error */ 164 165 ACPI_DMTABLE_INFO AcpiDmTableInfoAestSmmuError[] = 166 { 167 {ACPI_DMT_UINT32, ACPI_AEST2_OFFSET (IortNodeReference), "Iort Node Reference", 0}, 168 {ACPI_DMT_UINT32, ACPI_AEST2_OFFSET (SubcomponentReference), "Subcomponent Reference", 0}, 169 ACPI_DMT_TERMINATOR 170 }; 171 172 /* 3: Vendor Defined */ 173 174 ACPI_DMTABLE_INFO AcpiDmTableInfoAestVendorError[] = 175 { 176 {ACPI_DMT_UINT32, ACPI_AEST3_OFFSET (AcpiHid), "ACPI HID", 0}, 177 {ACPI_DMT_UINT32, ACPI_AEST3_OFFSET (AcpiUid), "ACPI UID", 0}, 178 {ACPI_DMT_BUF16, ACPI_AEST3_OFFSET (VendorSpecificData), "Vendor Specific Data", 0}, 179 ACPI_DMT_TERMINATOR 180 }; 181 182 /* 3: Vendor Defined V2 */ 183 184 ACPI_DMTABLE_INFO AcpiDmTableInfoAestVendorV2Error[] = 185 { 186 {ACPI_DMT_UINT64, ACPI_AEST3A_OFFSET (AcpiHid), "ACPI HID", 0}, 187 {ACPI_DMT_UINT32, ACPI_AEST3A_OFFSET (AcpiUid), "ACPI UID", 0}, 188 {ACPI_DMT_BUF16, ACPI_AEST3A_OFFSET (VendorSpecificData), "Vendor Specific Data", 0}, 189 ACPI_DMT_TERMINATOR 190 }; 191 192 /* 4: Gic Error */ 193 194 ACPI_DMTABLE_INFO AcpiDmTableInfoAestGicError[] = 195 { 196 {ACPI_DMT_AEST_GIC, ACPI_AEST4_OFFSET (InterfaceType), "GIC Interface Type", 0}, 197 {ACPI_DMT_UINT32, ACPI_AEST4_OFFSET (InstanceId), "Instance ID", 0}, 198 ACPI_DMT_TERMINATOR 199 }; 200 201 /* 5: PCIe Error */ 202 203 ACPI_DMTABLE_INFO AcpiDmTableInfoAestPCIeError[] = 204 { 205 {ACPI_DMT_UINT32, ACPI_AEST5_OFFSET (IortNodeReference), "Iort Node Reference", 0}, 206 ACPI_DMT_TERMINATOR 207 }; 208 209 /* 6: Proxy Error */ 210 211 ACPI_DMTABLE_INFO AcpiDmTableInfoAestProxyError[] = 212 { 213 {ACPI_DMT_UINT64, ACPI_AEST6_OFFSET (NodeAddress), "Proxy Node Address", 0}, 214 ACPI_DMT_TERMINATOR 215 }; 216 217 /* Common AEST structures for subtables */ 218 219 #define ACPI_DM_AEST_INTERFACE_COMMON(a) \ 220 {ACPI_DMT_UINT32, ACPI_AEST0D##a##_OFFSET (Common.ErrorNodeDevice), "Arm Error Node Device", 0},\ 221 {ACPI_DMT_UINT32, ACPI_AEST0D##a##_OFFSET (Common.ProcessorAffinity), "Processor Affinity", 0}, \ 222 {ACPI_DMT_UINT64, ACPI_AEST0D##a##_OFFSET (Common.ErrorGroupRegisterBase), "Err-Group Register Addr", 0}, \ 223 {ACPI_DMT_UINT64, ACPI_AEST0D##a##_OFFSET (Common.FaultInjectRegisterBase), "Err-Inject Register Addr", 0}, \ 224 {ACPI_DMT_UINT64, ACPI_AEST0D##a##_OFFSET (Common.InterruptConfigRegisterBase), "IRQ-Config Register Addr", 0}, 225 226 /* AestXface: Node Interface Structure */ 227 228 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface[] = 229 { 230 {ACPI_DMT_AEST_XFACE, ACPI_AEST0D_OFFSET (Type), "Interface Type", 0}, 231 {ACPI_DMT_UINT24, ACPI_AEST0D_OFFSET (Reserved[0]), "Reserved", 0}, 232 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (Flags), "Flags (decoded below)", 0}, 233 {ACPI_DMT_FLAG0, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Shared Interface", 0}, 234 {ACPI_DMT_FLAG1, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Clear MISCx Registers", 0}, 235 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (Address), "Address", 0}, 236 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (ErrorRecordIndex), "Error Record Index", 0}, 237 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (ErrorRecordCount), "Error Record Count", 0}, 238 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (ErrorRecordImplemented),"Error Record Implemented", 0}, 239 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (ErrorStatusReporting), "Error Status Reporting", 0}, 240 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (AddressingMode), "Addressing Mode", 0}, 241 ACPI_DMT_TERMINATOR 242 }; 243 244 /* AestXface: Node Interface Structure V2 Header */ 245 246 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXfaceHeader[] = 247 { 248 {ACPI_DMT_AEST_XFACE, ACPI_AEST0DH_OFFSET (Type), "Interface Type", 0}, 249 {ACPI_DMT_UINT8, ACPI_AEST0DH_OFFSET (GroupFormat), "Group Format", 0}, 250 {ACPI_DMT_UINT16, ACPI_AEST0DH_OFFSET (Reserved[0]), "Reserved", 0}, 251 {ACPI_DMT_UINT32, ACPI_AEST0DH_OFFSET (Flags), "Flags (decoded below)", 0}, 252 {ACPI_DMT_FLAG0, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Shared Interface", 0}, 253 {ACPI_DMT_FLAG1, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Clear MISCx Registers", 0}, 254 {ACPI_DMT_FLAG2, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Error Node Device Valid", 0}, 255 {ACPI_DMT_FLAG3, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Affinity Type", 0}, 256 {ACPI_DMT_FLAG4, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Error group Address Valid", 0}, 257 {ACPI_DMT_FLAG5, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Fault Injection Address Valid", 0}, 258 {ACPI_DMT_FLAG7, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Interrupt Config Address valid", 0}, 259 {ACPI_DMT_UINT64, ACPI_AEST0DH_OFFSET (Address), "Address", 0}, 260 {ACPI_DMT_UINT32, ACPI_AEST0DH_OFFSET (ErrorRecordIndex), "Error Record Index", 0}, 261 {ACPI_DMT_UINT32, ACPI_AEST0DH_OFFSET (ErrorRecordCount), "Error Record Count", 0}, 262 ACPI_DMT_TERMINATOR 263 }; 264 265 /* AestXface: Node Interface Structure V2 4K Group Format */ 266 267 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface4k[] = 268 { 269 {ACPI_DMT_UINT64, ACPI_AEST0D4_OFFSET (ErrorRecordImplemented),"Error Record Implemented", 0}, 270 {ACPI_DMT_UINT64, ACPI_AEST0D4_OFFSET (ErrorStatusReporting), "Error Status Reporting", 0}, 271 {ACPI_DMT_UINT64, ACPI_AEST0D4_OFFSET (AddressingMode), "Addressing Mode", 0}, 272 ACPI_DM_AEST_INTERFACE_COMMON(4) 273 ACPI_DMT_TERMINATOR 274 }; 275 276 /* AestXface: Node Interface Structure V2 16K Group Format */ 277 278 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface16k[] = 279 { 280 {ACPI_DMT_BUF32, ACPI_AEST0D16_OFFSET (ErrorRecordImplemented[0]),"Error Record Implemented", 0}, 281 {ACPI_DMT_BUF32, ACPI_AEST0D16_OFFSET (ErrorStatusReporting[0]), "Error Status Reporting", 0}, 282 {ACPI_DMT_BUF32, ACPI_AEST0D16_OFFSET (AddressingMode[0]), "Addressing Mode", 0}, 283 ACPI_DM_AEST_INTERFACE_COMMON(16) 284 ACPI_DMT_TERMINATOR 285 }; 286 287 /* AestXface: Node Interface Structure V2 64K Group Format */ 288 289 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface64k[] = 290 { 291 {ACPI_DMT_BUF112, ACPI_AEST0D64_OFFSET (ErrorRecordImplemented[0]),"Error Record Implemented", 0}, 292 {ACPI_DMT_BUF112, ACPI_AEST0D64_OFFSET (ErrorStatusReporting[0]), "Error Status Reporting", 0}, 293 {ACPI_DMT_BUF112, ACPI_AEST0D64_OFFSET (AddressingMode[0]), "Addressing Mode", 0}, 294 ACPI_DM_AEST_INTERFACE_COMMON(64) 295 ACPI_DMT_TERMINATOR 296 }; 297 298 /* AestXrupt: Node Interrupt Structure */ 299 300 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXrupt[] = 301 { 302 {ACPI_DMT_AEST_XRUPT, ACPI_AEST0E_OFFSET (Type), "Interrupt Type", 0}, 303 {ACPI_DMT_UINT16, ACPI_AEST0E_OFFSET (Reserved), "Reserved", 0}, 304 {ACPI_DMT_UINT8, ACPI_AEST0E_OFFSET (Flags), "Flags (decoded below)", 0}, 305 {ACPI_DMT_FLAG0, ACPI_AEST0E_FLAG_OFFSET (Flags, 0), "Level Triggered", 0}, 306 {ACPI_DMT_UINT32, ACPI_AEST0E_OFFSET (Gsiv), "Gsiv", 0}, 307 {ACPI_DMT_UINT8, ACPI_AEST0E_OFFSET (IortId), "IortId", 0}, 308 {ACPI_DMT_UINT24, ACPI_AEST0E_OFFSET (Reserved1[0]), "Reserved", 0}, 309 ACPI_DMT_TERMINATOR 310 }; 311 312 313 /* AestXrupt: Node Interrupt Structure V2 */ 314 315 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXruptV2[] = 316 { 317 {ACPI_DMT_AEST_XRUPT, ACPI_AEST0EA_OFFSET (Type), "Interrupt Type", 0}, 318 {ACPI_DMT_UINT16, ACPI_AEST0EA_OFFSET (Reserved), "Reserved", 0}, 319 {ACPI_DMT_UINT8, ACPI_AEST0EA_OFFSET (Flags), "Flags (decoded below)", 0}, 320 {ACPI_DMT_FLAG0, ACPI_AEST0EA_FLAG_OFFSET (Flags, 0), "Level Triggered", 0}, 321 {ACPI_DMT_UINT32, ACPI_AEST0EA_OFFSET (Gsiv), "Gsiv", 0}, 322 {ACPI_DMT_UINT32, ACPI_AEST0EA_OFFSET (Reserved1[0]), "Reserved", 0}, 323 ACPI_DMT_TERMINATOR 324 }; 325 326 327 /******************************************************************************* 328 * 329 * ASF - Alert Standard Format table (Signature "ASF!") 330 * 331 ******************************************************************************/ 332 333 /* Common Subtable header (one per Subtable) */ 334 335 ACPI_DMTABLE_INFO AcpiDmTableInfoAsfHdr[] = 336 { 337 {ACPI_DMT_ASF, ACPI_ASF0_OFFSET (Header.Type), "Subtable Type", 0}, 338 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Header.Reserved), "Reserved", 0}, 339 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (Header.Length), "Length", DT_LENGTH}, 340 ACPI_DMT_TERMINATOR 341 }; 342 343 /* 0: ASF Information */ 344 345 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf0[] = 346 { 347 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinResetValue), "Minimum Reset Value", 0}, 348 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinPollInterval), "Minimum Polling Interval", 0}, 349 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (SystemId), "System ID", 0}, 350 {ACPI_DMT_UINT32, ACPI_ASF0_OFFSET (MfgId), "Manufacturer ID", 0}, 351 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Flags), "Flags", 0}, 352 {ACPI_DMT_UINT24, ACPI_ASF0_OFFSET (Reserved2[0]), "Reserved", 0}, 353 ACPI_DMT_TERMINATOR 354 }; 355 356 /* 1: ASF Alerts */ 357 358 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1[] = 359 { 360 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (AssertMask), "AssertMask", 0}, 361 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DeassertMask), "DeassertMask", 0}, 362 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (Alerts), "Alert Count", 0}, 363 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DataLength), "Alert Data Length", 0}, 364 ACPI_DMT_TERMINATOR 365 }; 366 367 /* 1a: ASF Alert data */ 368 369 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1a[] = 370 { 371 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Address), "Address", 0}, 372 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Command), "Command", 0}, 373 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Mask), "Mask", 0}, 374 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Value), "Value", 0}, 375 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorType), "SensorType", 0}, 376 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Type), "Type", 0}, 377 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Offset), "Offset", 0}, 378 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SourceType), "SourceType", 0}, 379 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Severity), "Severity", 0}, 380 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorNumber), "SensorNumber", 0}, 381 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Entity), "Entity", 0}, 382 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Instance), "Instance", 0}, 383 ACPI_DMT_TERMINATOR 384 }; 385 386 /* 2: ASF Remote Control */ 387 388 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2[] = 389 { 390 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (Controls), "Control Count", 0}, 391 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (DataLength), "Control Data Length", 0}, 392 {ACPI_DMT_UINT16, ACPI_ASF2_OFFSET (Reserved2), "Reserved", 0}, 393 ACPI_DMT_TERMINATOR 394 }; 395 396 /* 2a: ASF Control data */ 397 398 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2a[] = 399 { 400 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Function), "Function", 0}, 401 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Address), "Address", 0}, 402 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Command), "Command", 0}, 403 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Value), "Value", 0}, 404 ACPI_DMT_TERMINATOR 405 }; 406 407 /* 3: ASF RMCP Boot Options */ 408 409 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf3[] = 410 { 411 {ACPI_DMT_BUF7, ACPI_ASF3_OFFSET (Capabilities[0]), "Capabilities", 0}, 412 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (CompletionCode), "Completion Code", 0}, 413 {ACPI_DMT_UINT32, ACPI_ASF3_OFFSET (EnterpriseId), "Enterprise ID", 0}, 414 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (Command), "Command", 0}, 415 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (Parameter), "Parameter", 0}, 416 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (BootOptions), "Boot Options", 0}, 417 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (OemParameters), "Oem Parameters", 0}, 418 ACPI_DMT_TERMINATOR 419 }; 420 421 /* 4: ASF Address */ 422 423 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf4[] = 424 { 425 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (EpromAddress), "Eprom Address", 0}, 426 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (Devices), "Device Count", DT_COUNT}, 427 ACPI_DMT_TERMINATOR 428 }; 429 430 431 /******************************************************************************* 432 * 433 * ASPT - AMD Secure Processor table (Signature "ASPT") 434 * 435 ******************************************************************************/ 436 437 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt[] = 438 { 439 {ACPI_DMT_UINT32, ACPI_ASPT_OFFSET(NumEntries), "Number of Subtables", 0}, 440 ACPI_DMT_TERMINATOR 441 }; 442 443 /* Common Subtable header (one per Subtable) */ 444 ACPI_DMTABLE_INFO AcpiDmTableInfoAsptHdr[] = 445 { 446 {ACPI_DMT_ASPT, ACPI_ASPTH_OFFSET(Type), "Type", 0}, 447 {ACPI_DMT_UINT16, ACPI_ASPTH_OFFSET(Length), "Length", 0}, 448 ACPI_DMT_TERMINATOR 449 }; 450 451 /* 0: ASPT Global Registers */ 452 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt0[] = 453 { 454 {ACPI_DMT_UINT32, ACPI_ASPT0_OFFSET(Reserved), "Reserved", 0}, 455 {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(FeatureRegAddr), "Feature Register Address", 0}, 456 {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(IrqEnRegAddr), "Interrupt Enable Register Address", 0}, 457 {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(IrqStRegAddr), "Interrupt Status Register Address", 0}, 458 ACPI_DMT_TERMINATOR 459 }; 460 461 /* 1: ASPT SEV Mailbox Registers */ 462 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt1[] = 463 { 464 {ACPI_DMT_UINT8, ACPI_ASPT1_OFFSET(MboxIrqId), "Mailbox Interrupt ID", 0}, 465 {ACPI_DMT_UINT24, ACPI_ASPT1_OFFSET(Reserved[0]), "Reserved", 0}, 466 {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdRespRegAddr), "CmdResp Register Address", 0}, 467 {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdBufLoRegAddr), "CmdBufAddr_Lo Register Address", 0}, 468 {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdBufHiRegAddr), "CmdBufAddr_Hi Register Address", 0}, 469 ACPI_DMT_TERMINATOR 470 }; 471 472 /* 2: ASPT ACPI Maiblox Registers */ 473 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt2[] = 474 { 475 {ACPI_DMT_UINT32, ACPI_ASPT2_OFFSET(Reserved1), "Reserved", 0}, 476 {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(CmdRespRegAddr), "CmdResp Register Address", 0}, 477 {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(Reserved2[0]), "Reserved", 0}, 478 {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(Reserved2[1]), "Reserved", 0}, 479 ACPI_DMT_TERMINATOR 480 }; 481 482 /******************************************************************************* 483 * 484 * BDAT - BIOS Data ACPI Table 485 * 486 ******************************************************************************/ 487 488 ACPI_DMTABLE_INFO AcpiDmTableInfoBdat[] = 489 { 490 {ACPI_DMT_GAS, ACPI_BDAT_OFFSET (Gas), "BDAT Generic Address", 0}, 491 ACPI_DMT_TERMINATOR 492 }; 493 494 495 /******************************************************************************* 496 * 497 * BERT - Boot Error Record table 498 * 499 ******************************************************************************/ 500 501 ACPI_DMTABLE_INFO AcpiDmTableInfoBert[] = 502 { 503 {ACPI_DMT_UINT32, ACPI_BERT_OFFSET (RegionLength), "Boot Error Region Length", 0}, 504 {ACPI_DMT_UINT64, ACPI_BERT_OFFSET (Address), "Boot Error Region Address", 0}, 505 ACPI_DMT_TERMINATOR 506 }; 507 508 509 /******************************************************************************* 510 * 511 * BGRT - Boot Graphics Resource Table (ACPI 5.0) 512 * 513 ******************************************************************************/ 514 515 ACPI_DMTABLE_INFO AcpiDmTableInfoBgrt[] = 516 { 517 {ACPI_DMT_UINT16, ACPI_BGRT_OFFSET (Version), "Version", 0}, 518 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (Status), "Status (decoded below)", DT_FLAG}, 519 {ACPI_DMT_FLAG0, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Displayed", 0}, 520 {ACPI_DMT_FLAGS1, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Orientation Offset", 0}, 521 522 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (ImageType), "Image Type", 0}, 523 {ACPI_DMT_UINT64, ACPI_BGRT_OFFSET (ImageAddress), "Image Address", 0}, 524 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetX), "Image OffsetX", 0}, 525 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetY), "Image OffsetY", 0}, 526 ACPI_DMT_TERMINATOR 527 }; 528 529 530 /******************************************************************************* 531 * 532 * BOOT - Simple Boot Flag Table 533 * 534 ******************************************************************************/ 535 536 ACPI_DMTABLE_INFO AcpiDmTableInfoBoot[] = 537 { 538 {ACPI_DMT_UINT8, ACPI_BOOT_OFFSET (CmosIndex), "Boot Register Index", 0}, 539 {ACPI_DMT_UINT24, ACPI_BOOT_OFFSET (Reserved[0]), "Reserved", 0}, 540 ACPI_DMT_TERMINATOR 541 }; 542 543 /******************************************************************************* 544 * 545 * CDAT - Coherent Device Attribute Table 546 * 547 ******************************************************************************/ 548 549 /* Table header (not ACPI-compliant) */ 550 551 ACPI_DMTABLE_INFO AcpiDmTableInfoCdatTableHdr[] = 552 { 553 {ACPI_DMT_UINT32, ACPI_CDAT_OFFSET (Length), "CDAT Table Length", DT_LENGTH}, 554 {ACPI_DMT_UINT8, ACPI_CDAT_OFFSET (Revision), "Revision", 0}, 555 {ACPI_DMT_UINT8, ACPI_CDAT_OFFSET (Checksum), "Checksum", 0}, 556 {ACPI_DMT_UINT48, ACPI_CDAT_OFFSET (Reserved), "Reserved", 0}, 557 {ACPI_DMT_UINT32, ACPI_CDAT_OFFSET (Sequence), "Sequence", 0}, 558 ACPI_DMT_TERMINATOR 559 }; 560 561 /* Common subtable header */ 562 563 ACPI_DMTABLE_INFO AcpiDmTableInfoCdatHeader[] = 564 { 565 {ACPI_DMT_CDAT, ACPI_CDATH_OFFSET (Type), "Subtable Type", 0}, 566 {ACPI_DMT_UINT8, ACPI_CDATH_OFFSET (Reserved), "Reserved", 0}, 567 {ACPI_DMT_UINT16, ACPI_CDATH_OFFSET (Length), "Length", DT_LENGTH}, 568 ACPI_DMT_TERMINATOR 569 }; 570 571 /* Subtable 0: Device Scoped Memory Affinity Structure (DSMAS) */ 572 573 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat0[] = 574 { 575 {ACPI_DMT_UINT8, ACPI_CDAT0_OFFSET (DsmadHandle), "DSMAD Handle", 0}, 576 {ACPI_DMT_UINT8, ACPI_CDAT0_OFFSET (Flags), "Flags", 0}, 577 {ACPI_DMT_UINT16, ACPI_CDAT0_OFFSET (Reserved), "Reserved", 0}, 578 {ACPI_DMT_UINT64, ACPI_CDAT0_OFFSET (DpaBaseAddress), "DPA Base Address", 0}, 579 {ACPI_DMT_UINT64, ACPI_CDAT0_OFFSET (DpaLength), "DPA Length", 0}, 580 ACPI_DMT_TERMINATOR 581 }; 582 583 /* Subtable 1: Device scoped Latency and Bandwidth Information Structure (DSLBIS) */ 584 585 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat1[] = 586 { 587 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Handle), "Handle", 0}, 588 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Flags), "Flags", 0}, 589 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (DataType), "Data Type", 0}, 590 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Reserved), "Reserved", 0}, 591 {ACPI_DMT_UINT64, ACPI_CDAT1_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 592 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[0]), "Entry0", 0}, 593 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[1]), "Entry1", 0}, 594 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[2]), "Entry2", 0}, 595 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Reserved2), "Reserved", 0}, 596 ACPI_DMT_TERMINATOR 597 }; 598 599 /* Subtable 2: Device Scoped Memory Side Cache Information Structure (DSMSCIS) */ 600 601 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat2[] = 602 { 603 {ACPI_DMT_UINT8, ACPI_CDAT2_OFFSET (DsmasHandle), "DSMAS Handle", 0}, 604 {ACPI_DMT_UINT24, ACPI_CDAT2_OFFSET (Reserved[3]), "Reserved", 0}, 605 {ACPI_DMT_UINT64, ACPI_CDAT2_OFFSET (SideCacheSize), "Side Cache Size", 0}, 606 {ACPI_DMT_UINT32, ACPI_CDAT2_OFFSET (CacheAttributes), "Cache Attributes", 0}, 607 ACPI_DMT_TERMINATOR 608 }; 609 610 /* Subtable 3: Device Scoped Initiator Structure (DSIS) */ 611 612 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat3[] = 613 { 614 {ACPI_DMT_UINT8, ACPI_CDAT3_OFFSET (Flags), "Flags", 0}, 615 {ACPI_DMT_UINT8, ACPI_CDAT3_OFFSET (Handle), "Handle", 0}, 616 {ACPI_DMT_UINT16, ACPI_CDAT3_OFFSET (Reserved), "Reserved", 0}, 617 ACPI_DMT_TERMINATOR 618 }; 619 620 /* Subtable 4: Device Scoped EFI Memory Type Structure (DSEMTS) */ 621 622 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat4[] = 623 { 624 {ACPI_DMT_UINT8, ACPI_CDAT4_OFFSET (DsmasHandle), "DSMAS Handle", 0}, 625 {ACPI_DMT_UINT8, ACPI_CDAT4_OFFSET (MemoryType), "Memory Type", 0}, 626 {ACPI_DMT_UINT16, ACPI_CDAT4_OFFSET (Reserved), "Reserved", 0}, 627 {ACPI_DMT_UINT64, ACPI_CDAT4_OFFSET (DpaOffset), "DPA Offset", 0}, 628 {ACPI_DMT_UINT64, ACPI_CDAT4_OFFSET (RangeLength), "DPA Range Length", 0}, 629 ACPI_DMT_TERMINATOR 630 }; 631 632 /* Subtable 5: Switch Scoped Latency and Bandwidth Information Structure (SSLBIS) */ 633 634 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat5[] = 635 { 636 {ACPI_DMT_UINT8, ACPI_CDAT5_OFFSET (DataType), "Data Type", 0}, 637 {ACPI_DMT_UINT24, ACPI_CDAT5_OFFSET (Reserved), "Reserved", 0}, 638 {ACPI_DMT_UINT64, ACPI_CDAT5_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 639 ACPI_DMT_TERMINATOR 640 }; 641 642 /* Switch Scoped Latency and Bandwidth Entry (SSLBE) (For subtable 5 above) */ 643 644 ACPI_DMTABLE_INFO AcpiDmTableInfoCdatEntries[] = 645 { 646 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (PortxId), "Port X Id", 0}, 647 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (PortyId), "Port Y Id", 0}, 648 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (LatencyOrBandwidth), "Latency or Bandwidth", 0}, 649 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (Reserved), "Reserved", 0}, 650 ACPI_DMT_TERMINATOR 651 }; 652 653 654 /******************************************************************************* 655 * 656 * CEDT - CXL Early Discovery Table 657 * 658 ******************************************************************************/ 659 660 ACPI_DMTABLE_INFO AcpiDmTableInfoCedtHdr[] = 661 { 662 {ACPI_DMT_CEDT, ACPI_CEDT_OFFSET (Type), "Subtable Type", 0}, 663 {ACPI_DMT_UINT8, ACPI_CEDT_OFFSET (Reserved), "Reserved", 0}, 664 {ACPI_DMT_UINT16, ACPI_CEDT_OFFSET (Length), "Length", DT_LENGTH}, 665 ACPI_DMT_TERMINATOR 666 }; 667 668 /* 0: CXL Host Bridge Structure */ 669 670 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt0[] = 671 { 672 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Uid), "Associated host bridge", 0}, 673 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (CxlVersion), "Specification version", 0}, 674 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Reserved), "Reserved", 0}, 675 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Base), "Register base", 0}, 676 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Length), "Register length", 0}, 677 ACPI_DMT_TERMINATOR 678 }; 679 680 /* 1: CXL Fixed Memory Window Structure */ 681 682 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt1[] = 683 { 684 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (Reserved1), "Reserved", 0}, 685 {ACPI_DMT_UINT64, ACPI_CEDT1_OFFSET (BaseHpa), "Window base address", 0}, 686 {ACPI_DMT_UINT64, ACPI_CEDT1_OFFSET (WindowSize), "Window size", 0}, 687 {ACPI_DMT_UINT8, ACPI_CEDT1_OFFSET (InterleaveWays), "Interleave Members", 0}, 688 {ACPI_DMT_UINT8, ACPI_CEDT1_OFFSET (InterleaveArithmetic), "Interleave Arithmetic", 0}, 689 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (Reserved2), "Reserved", 0}, 690 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (Granularity), "Granularity", 0}, 691 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (Restrictions), "Restrictions", 0}, 692 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (QtgId), "QtgId", 0}, 693 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (InterleaveTargets), "First Target", 0}, 694 ACPI_DMT_TERMINATOR 695 }; 696 697 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt1_te[] = 698 { 699 {ACPI_DMT_UINT32, ACPI_CEDT1_TE_OFFSET (InterleaveTarget), "Next Target", 0}, 700 ACPI_DMT_TERMINATOR 701 }; 702 703 /* 2: CXL XOR Interleave Math Structure */ 704 705 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt2[] = 706 { 707 {ACPI_DMT_UINT16, ACPI_CEDT2_OFFSET (Reserved1), "Reserved", 0}, 708 {ACPI_DMT_UINT8, ACPI_CEDT2_OFFSET (Hbig), "Interleave Granularity", 0}, 709 {ACPI_DMT_UINT8, ACPI_CEDT2_OFFSET (NrXormaps), "Xormap List Count", 0}, 710 {ACPI_DMT_UINT64, ACPI_CEDT2_OFFSET (XormapList), "First Xormap", 0}, 711 ACPI_DMT_TERMINATOR 712 }; 713 714 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt2_te[] = 715 { 716 {ACPI_DMT_UINT64, ACPI_CEDT2_TE_OFFSET (Xormap), "Next Xormap", 0}, 717 ACPI_DMT_TERMINATOR 718 }; 719 720 /******************************************************************************* 721 * 722 * CPEP - Corrected Platform Error Polling table 723 * 724 ******************************************************************************/ 725 726 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep[] = 727 { 728 {ACPI_DMT_UINT64, ACPI_CPEP_OFFSET (Reserved), "Reserved", 0}, 729 ACPI_DMT_TERMINATOR 730 }; 731 732 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep0[] = 733 { 734 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Type), "Subtable Type", 0}, 735 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Length), "Length", DT_LENGTH}, 736 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Id), "Processor ID", 0}, 737 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Eid), "Processor EID", 0}, 738 {ACPI_DMT_UINT32, ACPI_CPEP0_OFFSET (Interval), "Polling Interval", 0}, 739 ACPI_DMT_TERMINATOR 740 }; 741 742 743 /******************************************************************************* 744 * 745 * CSRT - Core System Resource Table 746 * 747 ******************************************************************************/ 748 749 /* Main table consists only of the standard ACPI table header */ 750 751 /* Resource Group subtable */ 752 753 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt0[] = 754 { 755 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (Length), "Length", DT_LENGTH}, 756 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (VendorId), "Vendor ID", 0}, 757 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SubvendorId), "Subvendor ID", 0}, 758 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (DeviceId), "Device ID", 0}, 759 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (SubdeviceId), "Subdevice ID", 0}, 760 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Revision), "Revision", 0}, 761 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Reserved), "Reserved", 0}, 762 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SharedInfoLength), "Shared Info Length", 0}, 763 ACPI_DMT_TERMINATOR 764 }; 765 766 /* Shared Info subtable */ 767 768 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt1[] = 769 { 770 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MajorVersion), "Major Version", 0}, 771 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MinorVersion), "Minor Version", 0}, 772 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseLow), "MMIO Base Address Low", 0}, 773 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseHigh), "MMIO Base Address High", 0}, 774 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (GsiInterrupt), "GSI Interrupt", 0}, 775 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptPolarity), "Interrupt Polarity", 0}, 776 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptMode), "Interrupt Mode", 0}, 777 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (NumChannels), "Num Channels", 0}, 778 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (DmaAddressWidth), "DMA Address Width", 0}, 779 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (BaseRequestLine), "Base Request Line", 0}, 780 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (NumHandshakeSignals), "Num Handshake Signals", 0}, 781 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MaxBlockSize), "Max Block Size", 0}, 782 ACPI_DMT_TERMINATOR 783 }; 784 785 /* Resource Descriptor subtable */ 786 787 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2[] = 788 { 789 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Length), "Length", DT_LENGTH}, 790 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Type), "Type", 0}, 791 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Subtype), "Subtype", 0}, 792 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Uid), "UID", 0}, 793 ACPI_DMT_TERMINATOR 794 }; 795 796 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2a[] = 797 { 798 {ACPI_DMT_RAW_BUFFER, 0, "ResourceInfo", DT_OPTIONAL}, 799 ACPI_DMT_TERMINATOR 800 }; 801 802 803 /******************************************************************************* 804 * 805 * DBG2 - Debug Port Table 2 806 * 807 ******************************************************************************/ 808 809 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2[] = 810 { 811 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoOffset), "Info Offset", 0}, 812 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoCount), "Info Count", 0}, 813 ACPI_DMT_TERMINATOR 814 }; 815 816 /* Debug Device Information Subtable */ 817 818 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Device[] = 819 { 820 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (Revision), "Revision", 0}, 821 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Length), "Length", DT_LENGTH}, 822 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (RegisterCount), "Register Count", 0}, 823 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathLength), "Namepath Length", 0}, 824 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathOffset), "Namepath Offset", 0}, 825 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataLength), "OEM Data Length", DT_DESCRIBES_OPTIONAL}, 826 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataOffset), "OEM Data Offset", DT_DESCRIBES_OPTIONAL}, 827 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortType), "Port Type", 0}, 828 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortSubtype), "Port Subtype", 0}, 829 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Reserved), "Reserved", 0}, 830 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (BaseAddressOffset), "Base Address Offset", 0}, 831 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (AddressSizeOffset), "Address Size Offset", 0}, 832 ACPI_DMT_TERMINATOR 833 }; 834 835 /* Variable-length data for the subtable */ 836 837 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Addr[] = 838 { 839 {ACPI_DMT_GAS, 0, "Base Address Register", 0}, 840 ACPI_DMT_TERMINATOR 841 }; 842 843 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Size[] = 844 { 845 {ACPI_DMT_UINT32, 0, "Address Size", 0}, 846 ACPI_DMT_TERMINATOR 847 }; 848 849 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Name[] = 850 { 851 {ACPI_DMT_STRING, 0, "Namepath", 0}, 852 ACPI_DMT_TERMINATOR 853 }; 854 855 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2OemData[] = 856 { 857 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", DT_OPTIONAL}, 858 ACPI_DMT_TERMINATOR 859 }; 860 861 862 /******************************************************************************* 863 * 864 * DBGP - Debug Port 865 * 866 ******************************************************************************/ 867 868 ACPI_DMTABLE_INFO AcpiDmTableInfoDbgp[] = 869 { 870 {ACPI_DMT_UINT8, ACPI_DBGP_OFFSET (Type), "Interface Type", 0}, 871 {ACPI_DMT_UINT24, ACPI_DBGP_OFFSET (Reserved[0]), "Reserved", 0}, 872 {ACPI_DMT_GAS, ACPI_DBGP_OFFSET (DebugPort), "Debug Port Register", 0}, 873 ACPI_DMT_TERMINATOR 874 }; 875 876 877 /******************************************************************************* 878 * 879 * DMAR - DMA Remapping table 880 * 881 ******************************************************************************/ 882 883 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar[] = 884 { 885 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Width), "Host Address Width", 0}, 886 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Flags), "Flags", 0}, 887 {ACPI_DMT_BUF10, ACPI_DMAR_OFFSET (Reserved[0]), "Reserved", 0}, 888 ACPI_DMT_TERMINATOR 889 }; 890 891 /* Common Subtable header (one per Subtable) */ 892 893 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarHdr[] = 894 { 895 {ACPI_DMT_DMAR, ACPI_DMAR0_OFFSET (Header.Type), "Subtable Type", 0}, 896 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Header.Length), "Length", DT_LENGTH}, 897 ACPI_DMT_TERMINATOR 898 }; 899 900 /* Common device scope entry */ 901 902 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarScope[] = 903 { 904 {ACPI_DMT_DMAR_SCOPE, ACPI_DMARS_OFFSET (EntryType), "Device Scope Type", 0}, 905 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Length), "Entry Length", DT_LENGTH}, 906 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Flags), "Flags", 0}, 907 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Reserved), "Reserved", 0}, 908 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (EnumerationId), "Enumeration ID", 0}, 909 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Bus), "PCI Bus Number", 0}, 910 ACPI_DMT_TERMINATOR 911 }; 912 913 /* DMAR Subtables */ 914 915 /* 0: Hardware Unit Definition */ 916 917 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar0[] = 918 { 919 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Flags), "Flags", 0}, 920 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Size), "Size (decoded below)", 0}, 921 {ACPI_DMT_FLAGS4_0, ACPI_DMAR0_FLAG_OFFSET (Size,0), "Size (pages, log2)", 0}, 922 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Segment), "PCI Segment Number", 0}, 923 {ACPI_DMT_UINT64, ACPI_DMAR0_OFFSET (Address), "Register Base Address", 0}, 924 ACPI_DMT_TERMINATOR 925 }; 926 927 /* 1: Reserved Memory Definition */ 928 929 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar1[] = 930 { 931 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Reserved), "Reserved", 0}, 932 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Segment), "PCI Segment Number", 0}, 933 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (BaseAddress), "Base Address", 0}, 934 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (EndAddress), "End Address (limit)", 0}, 935 ACPI_DMT_TERMINATOR 936 }; 937 938 /* 2: Root Port ATS Capability Definition */ 939 940 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar2[] = 941 { 942 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Flags), "Flags", 0}, 943 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Reserved), "Reserved", 0}, 944 {ACPI_DMT_UINT16, ACPI_DMAR2_OFFSET (Segment), "PCI Segment Number", 0}, 945 ACPI_DMT_TERMINATOR 946 }; 947 948 /* 3: Remapping Hardware Static Affinity Structure */ 949 950 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar3[] = 951 { 952 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (Reserved), "Reserved", 0}, 953 {ACPI_DMT_UINT64, ACPI_DMAR3_OFFSET (BaseAddress), "Base Address", 0}, 954 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (ProximityDomain), "Proximity Domain", 0}, 955 ACPI_DMT_TERMINATOR 956 }; 957 958 /* 4: ACPI Namespace Device Declaration Structure */ 959 960 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar4[] = 961 { 962 {ACPI_DMT_UINT24, ACPI_DMAR4_OFFSET (Reserved[0]), "Reserved", 0}, 963 {ACPI_DMT_UINT8, ACPI_DMAR4_OFFSET (DeviceNumber), "Device Number", 0}, 964 {ACPI_DMT_STRING, ACPI_DMAR4_OFFSET (DeviceName[0]), "Device Name", 0}, 965 ACPI_DMT_TERMINATOR 966 }; 967 968 /* 5: SoC Integrated Address Translation Cache */ 969 970 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar5[] = 971 { 972 {ACPI_DMT_UINT8, ACPI_DMAR5_OFFSET (Flags), "Flags", 0}, 973 {ACPI_DMT_UINT8, ACPI_DMAR5_OFFSET (Reserved), "Reserved", 0}, 974 {ACPI_DMT_UINT16, ACPI_DMAR5_OFFSET (Segment), "PCI Segment Number", 0}, 975 ACPI_DMT_TERMINATOR 976 }; 977 978 /* 6: SoC Integrated Device Property */ 979 980 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar6[] = 981 { 982 {ACPI_DMT_UINT16, ACPI_DMAR6_OFFSET (Reserved), "Reserved", 0}, 983 {ACPI_DMT_UINT16, ACPI_DMAR6_OFFSET (Segment), "PCI Segment Number", 0}, 984 ACPI_DMT_TERMINATOR 985 }; 986 987 988 /******************************************************************************* 989 * 990 * DRTM - Dynamic Root of Trust for Measurement table 991 * 992 ******************************************************************************/ 993 994 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm[] = 995 { 996 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryBaseAddress), "Entry Base Address", 0}, 997 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryLength), "Entry Length", 0}, 998 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (EntryAddress32), "Entry 32", 0}, 999 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryAddress64), "Entry 64", 0}, 1000 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ExitAddress), "Exit Address", 0}, 1001 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (LogAreaAddress), "Log Area Start", 0}, 1002 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (LogAreaLength), "Log Area Length", 0}, 1003 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ArchDependentAddress), "Arch Dependent Address", 0}, 1004 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (Flags), "Flags (decoded below)", 0}, 1005 {ACPI_DMT_FLAG0, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Namespace in TCB", 0}, 1006 {ACPI_DMT_FLAG1, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on S3 Resume", 0}, 1007 {ACPI_DMT_FLAG2, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on DLME_Exit", 0}, 1008 {ACPI_DMT_FLAG3, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "PCR_Authorities Changed", 0}, 1009 ACPI_DMT_TERMINATOR 1010 }; 1011 1012 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0[] = 1013 { 1014 {ACPI_DMT_UINT32, ACPI_DRTM0_OFFSET (ValidatedTableCount), "Validated Table Count", DT_COUNT}, 1015 ACPI_DMT_TERMINATOR 1016 }; 1017 1018 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0a[] = 1019 { 1020 {ACPI_DMT_UINT64, 0, "Table Address", DT_OPTIONAL}, 1021 ACPI_DMT_TERMINATOR 1022 }; 1023 1024 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1[] = 1025 { 1026 {ACPI_DMT_UINT32, ACPI_DRTM1_OFFSET (ResourceCount), "Resource Count", DT_COUNT}, 1027 ACPI_DMT_TERMINATOR 1028 }; 1029 1030 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1a[] = 1031 { 1032 {ACPI_DMT_UINT56, ACPI_DRTM1a_OFFSET (Size[0]), "Size", DT_OPTIONAL}, 1033 {ACPI_DMT_UINT8, ACPI_DRTM1a_OFFSET (Type), "Type", 0}, 1034 {ACPI_DMT_FLAG0, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Resource Type", 0}, 1035 {ACPI_DMT_FLAG7, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Protections", 0}, 1036 {ACPI_DMT_UINT64, ACPI_DRTM1a_OFFSET (Address), "Address", 0}, 1037 ACPI_DMT_TERMINATOR 1038 }; 1039 1040 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm2[] = 1041 { 1042 {ACPI_DMT_UINT32, ACPI_DRTM2_OFFSET (DpsIdLength), "DLME Platform Id Length", DT_COUNT}, 1043 {ACPI_DMT_BUF16, ACPI_DRTM2_OFFSET (DpsId), "DLME Platform Id", DT_COUNT}, 1044 ACPI_DMT_TERMINATOR 1045 }; 1046 1047 1048 /******************************************************************************* 1049 * 1050 * ECDT - Embedded Controller Boot Resources Table 1051 * 1052 ******************************************************************************/ 1053 1054 ACPI_DMTABLE_INFO AcpiDmTableInfoEcdt[] = 1055 { 1056 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Control), "Command/Status Register", 0}, 1057 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Data), "Data Register", 0}, 1058 {ACPI_DMT_UINT32, ACPI_ECDT_OFFSET (Uid), "UID", 0}, 1059 {ACPI_DMT_UINT8, ACPI_ECDT_OFFSET (Gpe), "GPE Number", 0}, 1060 {ACPI_DMT_STRING, ACPI_ECDT_OFFSET (Id[0]), "Namepath", 0}, 1061 ACPI_DMT_TERMINATOR 1062 }; 1063 1064 1065 /******************************************************************************* 1066 * 1067 * EINJ - Error Injection table 1068 * 1069 ******************************************************************************/ 1070 1071 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj[] = 1072 { 1073 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (HeaderLength), "Injection Header Length", 0}, 1074 {ACPI_DMT_UINT8, ACPI_EINJ_OFFSET (Flags), "Flags", 0}, 1075 {ACPI_DMT_UINT24, ACPI_EINJ_OFFSET (Reserved[0]), "Reserved", 0}, 1076 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (Entries), "Injection Entry Count", 0}, 1077 ACPI_DMT_TERMINATOR 1078 }; 1079 1080 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj0[] = 1081 { 1082 {ACPI_DMT_EINJACT, ACPI_EINJ0_OFFSET (Action), "Action", 0}, 1083 {ACPI_DMT_EINJINST, ACPI_EINJ0_OFFSET (Instruction), "Instruction", 0}, 1084 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1085 {ACPI_DMT_FLAG0, ACPI_EINJ0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 1086 1087 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Reserved), "Reserved", 0}, 1088 {ACPI_DMT_GAS, ACPI_EINJ0_OFFSET (RegisterRegion), "Register Region", 0}, 1089 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Value), "Value", 0}, 1090 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Mask), "Mask", 0}, 1091 ACPI_DMT_TERMINATOR 1092 }; 1093 1094 1095 /******************************************************************************* 1096 * 1097 * ERDT - Enhanced Resource Director Technology table 1098 * 1099 ******************************************************************************/ 1100 1101 ACPI_DMTABLE_INFO AcpiDmTableInfoErdt[] = 1102 { 1103 {ACPI_DMT_UINT32, ACPI_ERDT_OFFSET (MaxClos), "Maximum supported CLOSID", 0}, 1104 {ACPI_DMT_BUF24, ACPI_ERDT_OFFSET (Reserved), "Reserved", 0}, 1105 ACPI_DMT_TERMINATOR 1106 }; 1107 1108 1109 /******************************************************************************* 1110 * 1111 * ERDT - Common Subtable Header 1112 * 1113 ******************************************************************************/ 1114 1115 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtHdr[] = 1116 { 1117 {ACPI_DMT_ERDT, ACPI_ERDT_HDR_OFFSET (Type), "Type", 0}, 1118 {ACPI_DMT_UINT16, ACPI_ERDT_HDR_OFFSET (Length), "Length", DT_LENGTH}, 1119 ACPI_DMT_TERMINATOR 1120 }; 1121 1122 1123 /******************************************************************************* 1124 * 1125 * RMDD - ERDT Resource Management Domain Description subtable 1126 * 1127 ******************************************************************************/ 1128 1129 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtRmdd[] = 1130 { 1131 {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1132 {ACPI_DMT_FLAG0, ACPI_ERDT_RMDD_FLAG_OFFSET (Flags,0), "L3 Domain", 0}, 1133 {ACPI_DMT_FLAG1, ACPI_ERDT_RMDD_FLAG_OFFSET (Flags,0), "I/O L3 Domain", 0}, 1134 {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (IO_l3_Slices), "I/O L3 Slices", 0}, 1135 {ACPI_DMT_UINT8, ACPI_ERDT_RMDD_OFFSET (IO_l3_Sets), "I/O L3 Sets", 0}, 1136 {ACPI_DMT_UINT8, ACPI_ERDT_RMDD_OFFSET (IO_l3_Ways), "I/O L3 Ways", 0}, 1137 {ACPI_DMT_UINT64, ACPI_ERDT_RMDD_OFFSET (Reserved), "Reserved", 0}, 1138 {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (DomainId), "Domain ID", 0}, 1139 {ACPI_DMT_UINT32, ACPI_ERDT_RMDD_OFFSET (MaxRmid), "Maximum supported RMID", 0}, 1140 {ACPI_DMT_UINT64, ACPI_ERDT_RMDD_OFFSET (CregBase), "Control Register Base Address", 0}, 1141 {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (CregSize), "Control Register Base Size", 0}, 1142 ACPI_DMT_TERMINATOR 1143 }; 1144 1145 1146 /******************************************************************************* 1147 * 1148 * RMDD - CACD CPU Agent Collection Description subtable 1149 * 1150 ******************************************************************************/ 1151 1152 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCacd[] = 1153 { 1154 {ACPI_DMT_UINT16, ACPI_ERDT_CACD_OFFSET (Reserved), "Reserved", 0}, 1155 {ACPI_DMT_UINT16, ACPI_ERDT_CACD_OFFSET (DomainId), "Domain ID", 0}, 1156 ACPI_DMT_TERMINATOR 1157 }; 1158 1159 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCacdX2apic[] = 1160 { 1161 {ACPI_DMT_UINT32, 0, "X2ApicID", DT_OPTIONAL}, 1162 ACPI_DMT_TERMINATOR 1163 }; 1164 1165 1166 /******************************************************************************* 1167 * 1168 * RMDD - DACD Device Agent Collection Description subtable 1169 * 1170 ******************************************************************************/ 1171 1172 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtDacd[] = 1173 { 1174 {ACPI_DMT_UINT16, ACPI_ERDT_DACD_OFFSET (Reserved), "Reserved", 0}, 1175 {ACPI_DMT_UINT16, ACPI_ERDT_DACD_OFFSET (DomainId), "Domain ID", 0}, 1176 ACPI_DMT_TERMINATOR 1177 }; 1178 1179 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtDacdScope[] = 1180 { 1181 {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (Header.Type), "PCIType", DT_OPTIONAL}, 1182 {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (Header.Length), "Length", DT_OPTIONAL}, 1183 {ACPI_DMT_UINT16, ACPI_ERDT_DACD_PATH_OFFSET (Segment), "Segment", DT_OPTIONAL}, 1184 {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (Reserved), "Reserved", DT_OPTIONAL}, 1185 {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (StartBus), "StartBus", DT_OPTIONAL}, 1186 ACPI_DMT_TERMINATOR 1187 }; 1188 1189 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtDacdPath[] = 1190 { 1191 {ACPI_DMT_UINT8, 0, "Path", DT_OPTIONAL}, 1192 ACPI_DMT_TERMINATOR 1193 }; 1194 1195 1196 /******************************************************************************* 1197 * 1198 * RMDD - Cache Monitoring Registers for CPU Agents subtable 1199 * 1200 ******************************************************************************/ 1201 1202 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCmrc[] = 1203 { 1204 {ACPI_DMT_UINT32, ACPI_ERDT_CMRC_OFFSET (Reserved1), "Reserved", 0}, 1205 {ACPI_DMT_UINT32, ACPI_ERDT_CMRC_OFFSET (Flags), "Flags", 0}, 1206 {ACPI_DMT_UINT8, ACPI_ERDT_CMRC_OFFSET (IndexFn), "Register Index Function", 0}, 1207 {ACPI_DMT_BUF11, ACPI_ERDT_CMRC_OFFSET (Reserved2), "Reserved", 0}, 1208 {ACPI_DMT_UINT64, ACPI_ERDT_CMRC_OFFSET (CmtRegBase), "CMT Register Base Address", 0}, 1209 {ACPI_DMT_UINT32, ACPI_ERDT_CMRC_OFFSET (CmtRegSize), "CMT Register Size", 0}, 1210 {ACPI_DMT_UINT16, ACPI_ERDT_CMRC_OFFSET (ClumpSize), "Clump Size", 0}, 1211 {ACPI_DMT_UINT16, ACPI_ERDT_CMRC_OFFSET (ClumpStride), "Clump Stride", 0}, 1212 {ACPI_DMT_UINT64, ACPI_ERDT_CMRC_OFFSET (UpScale), "Upscale factor", 0}, 1213 ACPI_DMT_TERMINATOR 1214 }; 1215 1216 1217 /******************************************************************************* 1218 * 1219 * RMDD - Memory-bandwidth Monitoring Registers for CPU agents subtable 1220 * 1221 ******************************************************************************/ 1222 1223 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtMmrc[] = 1224 { 1225 {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (Reserved1), "Reserved", 0}, 1226 {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (Flags), "Flags", 0}, 1227 {ACPI_DMT_UINT8, ACPI_ERDT_MMRC_OFFSET (IndexFn), "Register Index Function", 0}, 1228 {ACPI_DMT_BUF11, ACPI_ERDT_MMRC_OFFSET (Reserved2), "Reserved", 0}, 1229 {ACPI_DMT_UINT64, ACPI_ERDT_MMRC_OFFSET (RegBase), "MBM Register Base Address", 0}, 1230 {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (RegSize), "MBM Register Size", 0}, 1231 {ACPI_DMT_UINT8, ACPI_ERDT_MMRC_OFFSET (CounterWidth), "MBM Counter Width", 0}, 1232 {ACPI_DMT_UINT64, ACPI_ERDT_MMRC_OFFSET (UpScale), "Upscale factor", 0}, 1233 {ACPI_DMT_UINT56, ACPI_ERDT_MMRC_OFFSET (Reserved3), "Reserved", 0}, 1234 {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (CorrFactorListLen), "Corr Factor List Length", 0}, 1235 ACPI_DMT_TERMINATOR 1236 }; 1237 1238 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtMmrcCorrFactor[] = 1239 { 1240 {ACPI_DMT_UINT32, 0, "CorrFactor", DT_OPTIONAL}, 1241 ACPI_DMT_TERMINATOR 1242 }; 1243 1244 1245 /******************************************************************************* 1246 * 1247 * RMDD - Memory-bandwidth Allocation Registers for CPU agents subtable 1248 * 1249 ******************************************************************************/ 1250 1251 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtMarc[] = 1252 { 1253 {ACPI_DMT_UINT16, ACPI_ERDT_MARC_OFFSET (Reserved1), "Reserved", 0}, 1254 {ACPI_DMT_UINT16, ACPI_ERDT_MARC_OFFSET (Flags), "Flags", 0}, 1255 {ACPI_DMT_UINT8, ACPI_ERDT_MARC_OFFSET (IndexFn), "Register Index Function", 0}, 1256 {ACPI_DMT_UINT56, ACPI_ERDT_MARC_OFFSET (Reserved2), "Reserved", 0}, 1257 {ACPI_DMT_UINT64, ACPI_ERDT_MARC_OFFSET (RegBaseOpt), "MBA Register Opt Base Address", 0}, 1258 {ACPI_DMT_UINT64, ACPI_ERDT_MARC_OFFSET (RegBaseMin), "MBA Register Min Base Address", 0}, 1259 {ACPI_DMT_UINT64, ACPI_ERDT_MARC_OFFSET (RegBaseMax), "MBA Register Max Base Address", 0}, 1260 {ACPI_DMT_UINT32, ACPI_ERDT_MARC_OFFSET (MbaRegSize), "MBA Register Size", 0}, 1261 {ACPI_DMT_UINT32, ACPI_ERDT_MARC_OFFSET (MbaCtrlRange), "MBA Control Range", 0}, 1262 ACPI_DMT_TERMINATOR 1263 }; 1264 1265 1266 /******************************************************************************* 1267 * 1268 * RMDD - Cache Allocation Registers for CPU Agents subtable 1269 * 1270 ******************************************************************************/ 1271 1272 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCarc[] = 1273 { 1274 ACPI_DMT_TERMINATOR 1275 }; 1276 1277 1278 /******************************************************************************* 1279 * 1280 * RMDD - Cache Monitoring Registers for Device Agents subtable 1281 * 1282 ******************************************************************************/ 1283 1284 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCmrd[] = 1285 { 1286 {ACPI_DMT_UINT32, ACPI_ERDT_CMRD_OFFSET (Reserved1), "Reserved", 0}, 1287 {ACPI_DMT_UINT32, ACPI_ERDT_CMRD_OFFSET (Flags), "Flags", 0}, 1288 {ACPI_DMT_UINT8, ACPI_ERDT_CMRD_OFFSET (IndexFn), "Register Index Function", 0}, 1289 {ACPI_DMT_BUF11, ACPI_ERDT_CMRD_OFFSET (Reserved2), "Reserved", 0}, 1290 {ACPI_DMT_UINT64, ACPI_ERDT_CMRD_OFFSET (RegBase), "CMRD Register Base Address", 0}, 1291 {ACPI_DMT_UINT32, ACPI_ERDT_CMRD_OFFSET (RegSize), "CMRD Register Size", 0}, 1292 {ACPI_DMT_UINT16, ACPI_ERDT_CMRD_OFFSET (CmtRegOff), "Register Offset", 0}, 1293 {ACPI_DMT_UINT16, ACPI_ERDT_CMRD_OFFSET (CmtClumpSize), "Clump Size", 0}, 1294 {ACPI_DMT_UINT64, ACPI_ERDT_CMRD_OFFSET (UpScale), "Upscale factor", 0}, 1295 ACPI_DMT_TERMINATOR 1296 }; 1297 1298 1299 /******************************************************************************* 1300 * 1301 * RMDD - O Bandwidth Monitoring Registers for Device Agents subtable 1302 * 1303 ******************************************************************************/ 1304 1305 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtIbrd[] = 1306 { 1307 {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (Reserved1), "Reserved", 0}, 1308 {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (Flags), "Flags", 0}, 1309 {ACPI_DMT_UINT8, ACPI_ERDT_IBRD_OFFSET (IndexFn), "Register Index Function", 0}, 1310 {ACPI_DMT_BUF11, ACPI_ERDT_IBRD_OFFSET (Reserved2), "Reserved", 0}, 1311 {ACPI_DMT_UINT64, ACPI_ERDT_IBRD_OFFSET (RegBase), "IBRD Register Base Address", 0}, 1312 {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (RegSize), "IBRD Register Size", 0}, 1313 {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (TotalBwOffset), "TotalBw Offset", 0}, 1314 {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (IOMissBwOffset), "IO Miss Offset", 0}, 1315 {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (TotalBwClump), "TotalBw Clump", 0}, 1316 {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (IOMissBwClump), "IO Miss Clump", 0}, 1317 {ACPI_DMT_UINT56, ACPI_ERDT_IBRD_OFFSET (Reserved3), "Reserved", 0}, 1318 {ACPI_DMT_UINT8, ACPI_ERDT_IBRD_OFFSET (CounterWidth), "Counter Width", 0}, 1319 {ACPI_DMT_UINT64, ACPI_ERDT_IBRD_OFFSET (UpScale), "Upscale factor", 0}, 1320 {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (CorrFactorListLen), "Corr Factor List Length", 0}, 1321 ACPI_DMT_TERMINATOR 1322 }; 1323 1324 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtIbrdCorrFactor[] = 1325 { 1326 {ACPI_DMT_UINT32, 0, "CorrFactor", DT_OPTIONAL}, 1327 ACPI_DMT_TERMINATOR 1328 }; 1329 1330 1331 /******************************************************************************* 1332 * 1333 * RMDD - O bandwidth Allocation Registers for Device Agents subtable 1334 * 1335 ******************************************************************************/ 1336 1337 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtIbad[] = 1338 { 1339 ACPI_DMT_TERMINATOR 1340 }; 1341 1342 1343 /******************************************************************************* 1344 * 1345 * RMDD - Cache Allocation Registers for Device Agents subtable 1346 * 1347 ******************************************************************************/ 1348 1349 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCard[] = 1350 { 1351 {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (Reserved1), "Reserved", 0}, 1352 {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (Flags), "Flags", 0}, 1353 {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (ContentionMask), "ContentionMask", 0}, 1354 {ACPI_DMT_UINT8, ACPI_ERDT_CARD_OFFSET (IndexFn), "Register Index Function", 0}, 1355 {ACPI_DMT_UINT56, ACPI_ERDT_CARD_OFFSET (Reserved2), "Register Index Function", 0}, 1356 {ACPI_DMT_UINT64, ACPI_ERDT_CARD_OFFSET (RegBase), "CARD Register Base Address", 0}, 1357 {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (RegSize), "CARD Register Size", 0}, 1358 {ACPI_DMT_UINT16, ACPI_ERDT_CARD_OFFSET (CatRegOffset), "CARD Register Offset", 0}, 1359 {ACPI_DMT_UINT16, ACPI_ERDT_CARD_OFFSET (CatRegBlockSize), "CARD Register Block Size", 0}, 1360 1361 ACPI_DMT_TERMINATOR 1362 }; 1363 1364 1365 /******************************************************************************* 1366 * 1367 * ERST - Error Record Serialization table 1368 * 1369 ******************************************************************************/ 1370 1371 ACPI_DMTABLE_INFO AcpiDmTableInfoErst[] = 1372 { 1373 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (HeaderLength), "Serialization Header Length", 0}, 1374 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Reserved), "Reserved", 0}, 1375 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Entries), "Instruction Entry Count", 0}, 1376 ACPI_DMT_TERMINATOR 1377 }; 1378 1379 ACPI_DMTABLE_INFO AcpiDmTableInfoErst0[] = 1380 { 1381 {ACPI_DMT_ERSTACT, ACPI_ERST0_OFFSET (Action), "Action", 0}, 1382 {ACPI_DMT_ERSTINST, ACPI_ERST0_OFFSET (Instruction), "Instruction", 0}, 1383 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1384 {ACPI_DMT_FLAG0, ACPI_ERST0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 1385 1386 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Reserved), "Reserved", 0}, 1387 {ACPI_DMT_GAS, ACPI_ERST0_OFFSET (RegisterRegion), "Register Region", 0}, 1388 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Value), "Value", 0}, 1389 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Mask), "Mask", 0}, 1390 ACPI_DMT_TERMINATOR 1391 }; 1392 1393 1394 /******************************************************************************* 1395 * 1396 * FPDT - Firmware Performance Data Table (ACPI 5.0) 1397 * 1398 ******************************************************************************/ 1399 1400 /* Main table consists of only the standard ACPI header - subtables follow */ 1401 1402 /* FPDT subtable header */ 1403 1404 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdtHdr[] = 1405 { 1406 {ACPI_DMT_UINT16, ACPI_FPDTH_OFFSET (Type), "Subtable Type", 0}, 1407 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Length), "Length", DT_LENGTH}, 1408 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Revision), "Revision", 0}, 1409 ACPI_DMT_TERMINATOR 1410 }; 1411 1412 /* 0: Firmware Basic Boot Performance Record */ 1413 1414 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt0[] = 1415 { 1416 {ACPI_DMT_UINT32, ACPI_FPDT0_OFFSET (Reserved), "Reserved", 0}, 1417 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "FPDT Boot Record Address", 0}, 1418 ACPI_DMT_TERMINATOR 1419 }; 1420 1421 /* 1: S3 Performance Table Pointer Record */ 1422 1423 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt1[] = 1424 { 1425 {ACPI_DMT_UINT32, ACPI_FPDT1_OFFSET (Reserved), "Reserved", 0}, 1426 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "S3PT Record Address", 0}, 1427 ACPI_DMT_TERMINATOR 1428 }; 1429 1430 #if 0 1431 /* Boot Performance Record, not supported at this time. */ 1432 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ResetEnd), "Reset End", 0}, 1433 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (LoadStart), "Load Image Start", 0}, 1434 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (StartupStart), "Start Image Start", 0}, 1435 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesEntry), "Exit Services Entry", 0}, 1436 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesExit), "Exit Services Exit", 0}, 1437 #endif 1438 1439 1440 /******************************************************************************* 1441 * 1442 * GTDT - Generic Timer Description Table 1443 * 1444 ******************************************************************************/ 1445 1446 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt[] = 1447 { 1448 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterBlockAddresss), "Counter Block Address", 0}, 1449 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (Reserved), "Reserved", 0}, 1450 ACPI_DMT_NEW_LINE, 1451 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Interrupt), "Secure EL1 Interrupt", 0}, 1452 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Flags), "EL1 Flags (decoded below)", DT_FLAG}, 1453 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Trigger Mode", 0}, 1454 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Polarity", 0}, 1455 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Always On", 0}, 1456 ACPI_DMT_NEW_LINE, 1457 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Interrupt), "Non-Secure EL1 Interrupt", 0}, 1458 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Flags), "NEL1 Flags (decoded below)", DT_FLAG}, 1459 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Trigger Mode", 0}, 1460 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Polarity", 0}, 1461 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Always On", 0}, 1462 ACPI_DMT_NEW_LINE, 1463 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 1464 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerFlags), "VT Flags (decoded below)", DT_FLAG}, 1465 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Trigger Mode", 0}, 1466 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Polarity", 0}, 1467 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Always On", 0}, 1468 ACPI_DMT_NEW_LINE, 1469 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Interrupt), "Non-Secure EL2 Interrupt", 0}, 1470 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Flags), "NEL2 Flags (decoded below)", DT_FLAG}, 1471 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Trigger Mode", 0}, 1472 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Polarity", 0}, 1473 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Always On", 0}, 1474 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterReadBlockAddress), "Counter Read Block Address", 0}, 1475 ACPI_DMT_NEW_LINE, 1476 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerCount), "Platform Timer Count", 0}, 1477 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerOffset), "Platform Timer Offset", 0}, 1478 ACPI_DMT_TERMINATOR 1479 }; 1480 1481 /* GDTD EL2 timer info. This table is appended to AcpiDmTableInfoGtdt for rev 3 and later */ 1482 1483 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtEl2[] = 1484 { 1485 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerGsiv), "Virtual EL2 Timer GSIV", 0}, 1486 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerFlags), "Virtual EL2 Timer Flags", 0}, 1487 ACPI_DMT_TERMINATOR 1488 }; 1489 1490 /* GTDT Subtable header (one per Subtable) */ 1491 1492 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtHdr[] = 1493 { 1494 {ACPI_DMT_GTDT, ACPI_GTDTH_OFFSET (Type), "Subtable Type", 0}, 1495 {ACPI_DMT_UINT16, ACPI_GTDTH_OFFSET (Length), "Length", DT_LENGTH}, 1496 ACPI_DMT_TERMINATOR 1497 }; 1498 1499 /* GTDT Subtables */ 1500 1501 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0[] = 1502 { 1503 {ACPI_DMT_UINT8, ACPI_GTDT0_OFFSET (Reserved), "Reserved", 0}, 1504 {ACPI_DMT_UINT64, ACPI_GTDT0_OFFSET (BlockAddress), "Block Address", 0}, 1505 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerCount), "Timer Count", 0}, 1506 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerOffset), "Timer Offset", 0}, 1507 ACPI_DMT_TERMINATOR 1508 }; 1509 1510 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0a[] = 1511 { 1512 {ACPI_DMT_UINT8 , ACPI_GTDT0a_OFFSET (FrameNumber), "Frame Number", 0}, 1513 {ACPI_DMT_UINT24, ACPI_GTDT0a_OFFSET (Reserved[0]), "Reserved", 0}, 1514 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (BaseAddress), "Base Address", 0}, 1515 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (El0BaseAddress), "EL0 Base Address", 0}, 1516 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1517 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerFlags), "Timer Flags (decoded below)", 0}, 1518 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1519 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1520 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 1521 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerFlags), "Virtual Timer Flags (decoded below)", 0}, 1522 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Trigger Mode", 0}, 1523 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Polarity", 0}, 1524 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (CommonFlags), "Common Flags (decoded below)", 0}, 1525 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Secure", 0}, 1526 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Always On", 0}, 1527 ACPI_DMT_TERMINATOR 1528 }; 1529 1530 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt1[] = 1531 { 1532 {ACPI_DMT_UINT8, ACPI_GTDT1_OFFSET (Reserved), "Reserved", 0}, 1533 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (RefreshFrameAddress), "Refresh Frame Address", 0}, 1534 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (ControlFrameAddress), "Control Frame Address", 0}, 1535 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1536 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerFlags), "Timer Flags (decoded below)", DT_FLAG}, 1537 {ACPI_DMT_FLAG0, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1538 {ACPI_DMT_FLAG1, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1539 {ACPI_DMT_FLAG2, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Security", 0}, 1540 ACPI_DMT_TERMINATOR 1541 }; 1542 1543 1544 /******************************************************************************* 1545 * 1546 * HEST - Hardware Error Source table 1547 * 1548 ******************************************************************************/ 1549 1550 ACPI_DMTABLE_INFO AcpiDmTableInfoHest[] = 1551 { 1552 {ACPI_DMT_UINT32, ACPI_HEST_OFFSET (ErrorSourceCount), "Error Source Count", 0}, 1553 ACPI_DMT_TERMINATOR 1554 }; 1555 1556 /* Common HEST structures for subtables */ 1557 1558 #define ACPI_DM_HEST_HEADER \ 1559 {ACPI_DMT_HEST, ACPI_HEST0_OFFSET (Header.Type), "Subtable Type", 0}, \ 1560 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Header.SourceId), "Source Id", 0} 1561 1562 #define ACPI_DM_HEST_AER \ 1563 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved1), "Reserved", 0}, \ 1564 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Flags), "Flags (decoded below)", DT_FLAG}, \ 1565 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Firmware First", 0}, \ 1566 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Global", 0}, \ 1567 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Enabled), "Enabled", 0}, \ 1568 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.RecordsToPreallocate), "Records To Preallocate", 0}, \ 1569 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.MaxSectionsPerRecord), "Max Sections Per Record", 0}, \ 1570 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.Bus), "Bus", 0}, \ 1571 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Device), "Device", 0}, \ 1572 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Function), "Function", 0}, \ 1573 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.DeviceControl), "DeviceControl", 0}, \ 1574 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved2), "Reserved", 0}, \ 1575 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableMask), "Uncorrectable Mask", 0}, \ 1576 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableSeverity), "Uncorrectable Severity", 0}, \ 1577 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.CorrectableMask), "Correctable Mask", 0}, \ 1578 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.AdvancedCapabilities), "Advanced Capabilities", 0} 1579 1580 1581 /* HEST Subtables */ 1582 1583 /* 0: IA32 Machine Check Exception */ 1584 1585 ACPI_DMTABLE_INFO AcpiDmTableInfoHest0[] = 1586 { 1587 ACPI_DM_HEST_HEADER, 1588 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Reserved1), "Reserved1", 0}, 1589 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1590 {ACPI_DMT_FLAG0, ACPI_HEST0_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1591 {ACPI_DMT_FLAG2, ACPI_HEST0_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1592 1593 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Enabled), "Enabled", 0}, 1594 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1595 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1596 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalCapabilityData), "Global Capability Data", 0}, 1597 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalControlData), "Global Control Data", 0}, 1598 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1599 {ACPI_DMT_UINT56, ACPI_HEST0_OFFSET (Reserved3[0]), "Reserved2", 0}, 1600 ACPI_DMT_TERMINATOR 1601 }; 1602 1603 /* 1: IA32 Corrected Machine Check */ 1604 1605 ACPI_DMTABLE_INFO AcpiDmTableInfoHest1[] = 1606 { 1607 ACPI_DM_HEST_HEADER, 1608 {ACPI_DMT_UINT16, ACPI_HEST1_OFFSET (Reserved1), "Reserved1", 0}, 1609 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1610 {ACPI_DMT_FLAG0, ACPI_HEST1_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1611 {ACPI_DMT_FLAG2, ACPI_HEST1_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1612 1613 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Enabled), "Enabled", 0}, 1614 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1615 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1616 {ACPI_DMT_HESTNTFY, ACPI_HEST1_OFFSET (Notify), "Notify", 0}, 1617 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1618 {ACPI_DMT_UINT24, ACPI_HEST1_OFFSET (Reserved2[0]), "Reserved2", 0}, 1619 ACPI_DMT_TERMINATOR 1620 }; 1621 1622 /* 2: IA32 Non-Maskable Interrupt */ 1623 1624 ACPI_DMTABLE_INFO AcpiDmTableInfoHest2[] = 1625 { 1626 ACPI_DM_HEST_HEADER, 1627 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (Reserved), "Reserved", 0}, 1628 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1629 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1630 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1631 ACPI_DMT_TERMINATOR 1632 }; 1633 1634 /* 6: PCI Express Root Port AER */ 1635 1636 ACPI_DMTABLE_INFO AcpiDmTableInfoHest6[] = 1637 { 1638 ACPI_DM_HEST_HEADER, 1639 ACPI_DM_HEST_AER, 1640 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (RootErrorCommand), "Root Error Command", 0}, 1641 ACPI_DMT_TERMINATOR 1642 }; 1643 1644 /* 7: PCI Express AER (AER Endpoint) */ 1645 1646 ACPI_DMTABLE_INFO AcpiDmTableInfoHest7[] = 1647 { 1648 ACPI_DM_HEST_HEADER, 1649 ACPI_DM_HEST_AER, 1650 ACPI_DMT_TERMINATOR 1651 }; 1652 1653 /* 8: PCI Express/PCI-X Bridge AER */ 1654 1655 ACPI_DMTABLE_INFO AcpiDmTableInfoHest8[] = 1656 { 1657 ACPI_DM_HEST_HEADER, 1658 ACPI_DM_HEST_AER, 1659 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableMask2), "2nd Uncorrectable Mask", 0}, 1660 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableSeverity2), "2nd Uncorrectable Severity", 0}, 1661 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (AdvancedCapabilities2), "2nd Advanced Capabilities", 0}, 1662 ACPI_DMT_TERMINATOR 1663 }; 1664 1665 /* 9: Generic Hardware Error Source */ 1666 1667 ACPI_DMTABLE_INFO AcpiDmTableInfoHest9[] = 1668 { 1669 ACPI_DM_HEST_HEADER, 1670 {ACPI_DMT_UINT16, ACPI_HEST9_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1671 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Reserved), "Reserved", 0}, 1672 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Enabled), "Enabled", 0}, 1673 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1674 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1675 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1676 {ACPI_DMT_GAS, ACPI_HEST9_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1677 {ACPI_DMT_HESTNTFY, ACPI_HEST9_OFFSET (Notify), "Notify", 0}, 1678 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1679 ACPI_DMT_TERMINATOR 1680 }; 1681 1682 /* 10: Generic Hardware Error Source - Version 2 */ 1683 1684 ACPI_DMTABLE_INFO AcpiDmTableInfoHest10[] = 1685 { 1686 ACPI_DM_HEST_HEADER, 1687 {ACPI_DMT_UINT16, ACPI_HEST10_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1688 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Reserved), "Reserved", 0}, 1689 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Enabled), "Enabled", 0}, 1690 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1691 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1692 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1693 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1694 {ACPI_DMT_HESTNTFY, ACPI_HEST10_OFFSET (Notify), "Notify", 0}, 1695 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1696 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ReadAckRegister), "Read Ack Register", 0}, 1697 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckPreserve), "Read Ack Preserve", 0}, 1698 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckWrite), "Read Ack Write", 0}, 1699 ACPI_DMT_TERMINATOR 1700 }; 1701 1702 /* 11: IA32 Deferred Machine Check */ 1703 1704 ACPI_DMTABLE_INFO AcpiDmTableInfoHest11[] = 1705 { 1706 ACPI_DM_HEST_HEADER, 1707 {ACPI_DMT_UINT16, ACPI_HEST11_OFFSET (Reserved1), "Reserved1", 0}, 1708 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1709 {ACPI_DMT_FLAG0, ACPI_HEST11_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1710 {ACPI_DMT_FLAG2, ACPI_HEST11_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1711 1712 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Enabled), "Enabled", 0}, 1713 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1714 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1715 {ACPI_DMT_HESTNTFY, ACPI_HEST11_OFFSET (Notify), "Notify", 0}, 1716 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1717 {ACPI_DMT_UINT24, ACPI_HEST11_OFFSET (Reserved2[0]), "Reserved2", 0}, 1718 ACPI_DMT_TERMINATOR 1719 }; 1720 1721 /* Notification Structure */ 1722 1723 ACPI_DMTABLE_INFO AcpiDmTableInfoHestNotify[] = 1724 { 1725 {ACPI_DMT_HESTNTYP, ACPI_HESTN_OFFSET (Type), "Notify Type", 0}, 1726 {ACPI_DMT_UINT8, ACPI_HESTN_OFFSET (Length), "Notify Length", DT_LENGTH}, 1727 {ACPI_DMT_UINT16, ACPI_HESTN_OFFSET (ConfigWriteEnable), "Configuration Write Enable", 0}, 1728 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollInterval), "PollInterval", 0}, 1729 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (Vector), "Vector", 0}, 1730 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdValue), "Polling Threshold Value", 0}, 1731 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdWindow), "Polling Threshold Window", 0}, 1732 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdValue), "Error Threshold Value", 0}, 1733 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdWindow), "Error Threshold Window", 0}, 1734 ACPI_DMT_TERMINATOR 1735 }; 1736 1737 1738 /* 1739 * IA32 Error Bank(s) - Follows the ACPI_HEST_IA_MACHINE_CHECK and 1740 * ACPI_HEST_IA_CORRECTED structures. 1741 */ 1742 ACPI_DMTABLE_INFO AcpiDmTableInfoHestBank[] = 1743 { 1744 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (BankNumber), "Bank Number", 0}, 1745 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (ClearStatusOnInit), "Clear Status On Init", 0}, 1746 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (StatusFormat), "Status Format", 0}, 1747 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (Reserved), "Reserved", 0}, 1748 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (ControlRegister), "Control Register", 0}, 1749 {ACPI_DMT_UINT64, ACPI_HESTB_OFFSET (ControlData), "Control Data", 0}, 1750 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (StatusRegister), "Status Register", 0}, 1751 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (AddressRegister), "Address Register", 0}, 1752 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (MiscRegister), "Misc Register", 0}, 1753 ACPI_DMT_TERMINATOR 1754 }; 1755 1756 1757 /******************************************************************************* 1758 * 1759 * HMAT - Heterogeneous Memory Attributes Table 1760 * 1761 ******************************************************************************/ 1762 1763 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat[] = 1764 { 1765 {ACPI_DMT_UINT32, ACPI_HMAT_OFFSET (Reserved), "Reserved", 0}, 1766 ACPI_DMT_TERMINATOR 1767 }; 1768 1769 /* Common HMAT structure header (one per Subtable) */ 1770 1771 ACPI_DMTABLE_INFO AcpiDmTableInfoHmatHdr[] = 1772 { 1773 {ACPI_DMT_HMAT, ACPI_HMATH_OFFSET (Type), "Structure Type", 0}, 1774 {ACPI_DMT_UINT16, ACPI_HMATH_OFFSET (Reserved), "Reserved", 0}, 1775 {ACPI_DMT_UINT32, ACPI_HMATH_OFFSET (Length), "Length", 0}, 1776 ACPI_DMT_TERMINATOR 1777 }; 1778 1779 /* HMAT subtables */ 1780 1781 /* 0x00: Memory proximity domain attributes */ 1782 1783 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat0[] = 1784 { 1785 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1786 {ACPI_DMT_FLAG0, ACPI_HMAT0_FLAG_OFFSET (Flags,0), "Processor Proximity Domain Valid", 0}, 1787 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Reserved1), "Reserved1", 0}, 1788 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (InitiatorPD), "Attached Initiator Proximity Domain", 0}, 1789 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1790 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (Reserved2), "Reserved2", 0}, 1791 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved3), "Reserved3", 0}, 1792 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved4), "Reserved4", 0}, 1793 ACPI_DMT_TERMINATOR 1794 }; 1795 1796 /* 0x01: System Locality Latency and Bandwidth Information */ 1797 1798 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1[] = 1799 { 1800 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Flags), "Flags (decoded below)", 0}, 1801 {ACPI_DMT_FLAGS4_0, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Memory Hierarchy", 0}, /* First 4 bits */ 1802 {ACPI_DMT_FLAG4, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Use Minimum Transfer Size", 0}, 1803 {ACPI_DMT_FLAG5, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Non-sequential Transfers", 0}, 1804 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (DataType), "Data Type", 0}, 1805 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (MinTransferSize), "Minimum Transfer Size", 0}, 1806 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Reserved1), "Reserved1", 0}, 1807 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfInitiatorPDs), "Initiator Proximity Domains #", 0}, 1808 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfTargetPDs), "Target Proximity Domains #", 0}, 1809 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (Reserved2), "Reserved2", 0}, 1810 {ACPI_DMT_UINT64, ACPI_HMAT1_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 1811 ACPI_DMT_TERMINATOR 1812 }; 1813 1814 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1a[] = 1815 { 1816 {ACPI_DMT_UINT32, 0, "Initiator Proximity Domain List", DT_OPTIONAL}, 1817 ACPI_DMT_TERMINATOR 1818 }; 1819 1820 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1b[] = 1821 { 1822 {ACPI_DMT_UINT32, 0, "Target Proximity Domain List", DT_OPTIONAL}, 1823 ACPI_DMT_TERMINATOR 1824 }; 1825 1826 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1c[] = 1827 { 1828 {ACPI_DMT_UINT16, 0, "Entry", DT_OPTIONAL}, 1829 ACPI_DMT_TERMINATOR 1830 }; 1831 1832 /* 0x02: Memory Side Cache Information */ 1833 1834 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2[] = 1835 { 1836 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1837 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (Reserved1), "Reserved1", 0}, 1838 {ACPI_DMT_UINT64, ACPI_HMAT2_OFFSET (CacheSize), "Memory Side Cache Size", 0}, 1839 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (CacheAttributes), "Cache Attributes (decoded below)", 0}, 1840 {ACPI_DMT_FLAGS4_0, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Total Cache Levels", 0}, 1841 {ACPI_DMT_FLAGS4_4, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Level", 0}, 1842 {ACPI_DMT_FLAGS4_8, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Associativity", 0}, 1843 {ACPI_DMT_FLAGS4_12, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Write Policy", 0}, 1844 {ACPI_DMT_FLAGS16_16, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Line Size", 0}, 1845 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (AddressMode), "Address Mode", 0}, 1846 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (NumberOfSMBIOSHandles), "SMBIOS Handle #", 0}, 1847 ACPI_DMT_TERMINATOR 1848 }; 1849 1850 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2a[] = 1851 { 1852 {ACPI_DMT_UINT16, 0, "SMBIOS Handle", DT_OPTIONAL}, 1853 ACPI_DMT_TERMINATOR 1854 }; 1855 1856 1857 /******************************************************************************* 1858 * 1859 * HPET - High Precision Event Timer table 1860 * 1861 ******************************************************************************/ 1862 1863 ACPI_DMTABLE_INFO AcpiDmTableInfoHpet[] = 1864 { 1865 {ACPI_DMT_UINT32, ACPI_HPET_OFFSET (Id), "Hardware Block ID", 0}, 1866 {ACPI_DMT_GAS, ACPI_HPET_OFFSET (Address), "Timer Block Register", 0}, 1867 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Sequence), "Sequence Number", 0}, 1868 {ACPI_DMT_UINT16, ACPI_HPET_OFFSET (MinimumTick), "Minimum Clock Ticks", 0}, 1869 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1870 {ACPI_DMT_FLAG0, ACPI_HPET_FLAG_OFFSET (Flags,0), "4K Page Protect", 0}, 1871 {ACPI_DMT_FLAG1, ACPI_HPET_FLAG_OFFSET (Flags,0), "64K Page Protect", 0}, 1872 ACPI_DMT_TERMINATOR 1873 }; 1874 /*! [End] no source code translation !*/ 1875
Indexes created Sat Feb 21 08:20:20 UTC 2026