1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo1 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /****************************************************************************** 8 * 9 * 1. Copyright Notice 10 * 11 * Some or all of this work - Copyright (c) 1999 - 2025, Intel Corp. 12 * All rights reserved. 13 * 14 * 2. License 15 * 16 * 2.1. This is your license from Intel Corp. under its intellectual property 17 * rights. You may have additional license terms from the party that provided 18 * you this software, covering your right to use that party's intellectual 19 * property rights. 20 * 21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 22 * copy of the source code appearing in this file ("Covered Code") an 23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 24 * base code distributed originally by Intel ("Original Intel Code") to copy, 25 * make derivatives, distribute, use and display any portion of the Covered 26 * Code in any form, with the right to sublicense such rights; and 27 * 28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 29 * license (with the right to sublicense), under only those claims of Intel 30 * patents that are infringed by the Original Intel Code, to make, use, sell, 31 * offer to sell, and import the Covered Code and derivative works thereof 32 * solely to the minimum extent necessary to exercise the above copyright 33 * license, and in no event shall the patent license extend to any additions 34 * to or modifications of the Original Intel Code. No other license or right 35 * is granted directly or by implication, estoppel or otherwise; 36 * 37 * The above copyright and patent license is granted only if the following 38 * conditions are met: 39 * 40 * 3. Conditions 41 * 42 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 43 * Redistribution of source code of any substantial portion of the Covered 44 * Code or modification with rights to further distribute source must include 45 * the above Copyright Notice, the above License, this list of Conditions, 46 * and the following Disclaimer and Export Compliance provision. In addition, 47 * Licensee must cause all Covered Code to which Licensee contributes to 48 * contain a file documenting the changes Licensee made to create that Covered 49 * Code and the date of any change. Licensee must include in that file the 50 * documentation of any changes made by any predecessor Licensee. Licensee 51 * must include a prominent statement that the modification is derived, 52 * directly or indirectly, from Original Intel Code. 53 * 54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 55 * Redistribution of source code of any substantial portion of the Covered 56 * Code or modification without rights to further distribute source must 57 * include the following Disclaimer and Export Compliance provision in the 58 * documentation and/or other materials provided with distribution. In 59 * addition, Licensee may not authorize further sublicense of source of any 60 * portion of the Covered Code, and must include terms to the effect that the 61 * license from Licensee to its licensee is limited to the intellectual 62 * property embodied in the software Licensee provides to its licensee, and 63 * not to intellectual property embodied in modifications its licensee may 64 * make. 65 * 66 * 3.3. Redistribution of Executable. Redistribution in executable form of any 67 * substantial portion of the Covered Code or modification must reproduce the 68 * above Copyright Notice, and the following Disclaimer and Export Compliance 69 * provision in the documentation and/or other materials provided with the 70 * distribution. 71 * 72 * 3.4. Intel retains all right, title, and interest in and to the Original 73 * Intel Code. 74 * 75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 76 * Intel shall be used in advertising or otherwise to promote the sale, use or 77 * other dealings in products derived from or relating to the Covered Code 78 * without prior written authorization from Intel. 79 * 80 * 4. Disclaimer and Export Compliance 81 * 82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 88 * PARTICULAR PURPOSE. 89 * 90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 97 * LIMITED REMEDY. 98 * 99 * 4.3. Licensee shall not export, either directly or indirectly, any of this 100 * software or system incorporating such software without first obtaining any 101 * required license or other approval from the U. S. Department of Commerce or 102 * any other agency or department of the United States Government. In the 103 * event Licensee exports any such software from the United States or 104 * re-exports any such software from a foreign destination, Licensee shall 105 * ensure that the distribution and export/re-export of the software is in 106 * compliance with all laws, regulations, orders, or other restrictions of the 107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 108 * any of its subsidiaries will export/re-export any technical data, process, 109 * software, or service, directly or indirectly, to any country for which the 110 * United States government or any agency thereof requires an export license, 111 * other governmental approval, or letter of assurance, without first obtaining 112 * such license, approval or letter. 113 * 114 ***************************************************************************** 115 * 116 * Alternatively, you may choose to be licensed under the terms of the 117 * following license: 118 * 119 * Redistribution and use in source and binary forms, with or without 120 * modification, are permitted provided that the following conditions 121 * are met: 122 * 1. Redistributions of source code must retain the above copyright 123 * notice, this list of conditions, and the following disclaimer, 124 * without modification. 125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 126 * substantially similar to the "NO WARRANTY" disclaimer below 127 * ("Disclaimer") and any redistribution must be conditioned upon 128 * including a substantially similar Disclaimer requirement for further 129 * binary redistribution. 130 * 3. Neither the names of the above-listed copyright holders nor the names 131 * of any contributors may be used to endorse or promote products derived 132 * from this software without specific prior written permission. 133 * 134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 145 * 146 * Alternatively, you may choose to be licensed under the terms of the 147 * GNU General Public License ("GPL") version 2 as published by the Free 148 * Software Foundation. 149 * 150 *****************************************************************************/ 151 152 #include "acpi.h" 153 #include "accommon.h" 154 #include "acdisasm.h" 155 #include "actbinfo.h" 156 157 /* This module used for application-level code only */ 158 159 #define _COMPONENT ACPI_CA_DISASSEMBLER 160 ACPI_MODULE_NAME ("dmtbinfo1") 161 162 /* 163 * How to add a new table: 164 * 165 * - Add the C table definition to the actbl1.h or actbl2.h header. 166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 167 * - Define the table in this file (for the disassembler). If any 168 * new data types are required (ACPI_DMT_*), see below. 169 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 170 * in acdisam.h 171 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 172 * If a simple table (with no subtables), no disassembly code is needed. 173 * Otherwise, create the AcpiDmDump* function for to disassemble the table 174 * and add it to the dmtbdump.c file. 175 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 176 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 177 * - Create a template for the new table 178 * - Add data table compiler support 179 * 180 * How to add a new data type (ACPI_DMT_*): 181 * 182 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 183 * - Add length and implementation cases in dmtable.c (disassembler) 184 * - Add type and length cases in dtutils.c (DT compiler) 185 */ 186 187 /* 188 * ACPI Table Information, used to dump formatted ACPI tables 189 * 190 * Each entry is of the form: <Field Type, Field Offset, Field Name> 191 */ 192 193 194 /******************************************************************************* 195 * 196 * AEST - ARM Error Source table. Conforms to: 197 * ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document Sep 2020 198 * 199 ******************************************************************************/ 200 201 /* Common Subtable header (one per Subtable) */ 202 203 ACPI_DMTABLE_INFO AcpiDmTableInfoAestHdr[] = 204 { 205 {ACPI_DMT_AEST, ACPI_AESTH_OFFSET (Type), "Subtable Type", 0}, 206 {ACPI_DMT_UINT16, ACPI_AESTH_OFFSET (Length), "Length", DT_LENGTH}, 207 {ACPI_DMT_UINT8, ACPI_AESTH_OFFSET (Reserved), "Reserved", 0}, 208 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeSpecificOffset), "Node Specific Offset", 0}, 209 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterfaceOffset), "Node Interface Offset", 0}, 210 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterruptOffset), "Node Interrupt Array Offset", 0}, 211 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterruptCount), "Node Interrupt Array Count", 0}, 212 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (TimestampRate), "Timestamp Rate", 0}, 213 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (Reserved1), "Reserved", 0}, 214 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (ErrorInjectionRate), "Error Injection Rate", 0}, 215 ACPI_DMT_TERMINATOR 216 }; 217 218 /* 219 * AEST subtables (nodes) 220 */ 221 222 /* 0: Processor Error */ 223 224 ACPI_DMTABLE_INFO AcpiDmTableInfoAestProcError[] = 225 { 226 {ACPI_DMT_UINT32, ACPI_AEST0_OFFSET (ProcessorId), "Processor ID", 0}, 227 {ACPI_DMT_AEST_RES, ACPI_AEST0_OFFSET (ResourceType), "Resource Type", 0}, 228 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Reserved), "Reserved", 0}, 229 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Flags), "Flags (decoded Below)", 0}, 230 {ACPI_DMT_FLAG0, ACPI_AEST0_FLAG_OFFSET (Flags, 0), "Global", 0}, 231 {ACPI_DMT_FLAG1, ACPI_AEST0_FLAG_OFFSET (Flags, 0), "Shared", 0}, 232 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Revision), "Revision", 0}, 233 {ACPI_DMT_UINT64, ACPI_AEST0_OFFSET (ProcessorAffinity), "Processor Affinity Structure", 0}, 234 ACPI_DMT_TERMINATOR 235 }; 236 237 /* 0RT: Processor Cache Resource */ 238 239 ACPI_DMTABLE_INFO AcpiDmTableInfoAestCacheRsrc[] = 240 { 241 {ACPI_DMT_UINT32, ACPI_AEST0A_OFFSET (CacheReference), "Cache Reference", 0}, 242 {ACPI_DMT_UINT32, ACPI_AEST0A_OFFSET (Reserved), "Reserved", 0}, 243 ACPI_DMT_TERMINATOR 244 }; 245 246 /* 1RT: ProcessorTLB Resource */ 247 248 ACPI_DMTABLE_INFO AcpiDmTableInfoAestTlbRsrc[] = 249 { 250 {ACPI_DMT_UINT32, ACPI_AEST0B_OFFSET (TlbLevel), "TLB Level", 0}, 251 {ACPI_DMT_UINT32, ACPI_AEST0B_OFFSET (Reserved), "Reserved", 0}, 252 ACPI_DMT_TERMINATOR 253 }; 254 255 /* 2RT: Processor Generic Resource */ 256 257 ACPI_DMTABLE_INFO AcpiDmTableInfoAestGenRsrc[] = 258 { 259 {ACPI_DMT_RAW_BUFFER, 0, "Resource", 0}, 260 ACPI_DMT_TERMINATOR 261 }; 262 263 /* 1: Memory Error */ 264 265 ACPI_DMTABLE_INFO AcpiDmTableInfoAestMemError[] = 266 { 267 {ACPI_DMT_UINT32, ACPI_AEST1_OFFSET (SratProximityDomain), "Srat Proximity Domain", 0}, 268 ACPI_DMT_TERMINATOR 269 }; 270 271 /* 2: Smmu Error */ 272 273 ACPI_DMTABLE_INFO AcpiDmTableInfoAestSmmuError[] = 274 { 275 {ACPI_DMT_UINT32, ACPI_AEST2_OFFSET (IortNodeReference), "Iort Node Reference", 0}, 276 {ACPI_DMT_UINT32, ACPI_AEST2_OFFSET (SubcomponentReference), "Subcomponent Reference", 0}, 277 ACPI_DMT_TERMINATOR 278 }; 279 280 /* 3: Vendor Defined */ 281 282 ACPI_DMTABLE_INFO AcpiDmTableInfoAestVendorError[] = 283 { 284 {ACPI_DMT_UINT32, ACPI_AEST3_OFFSET (AcpiHid), "ACPI HID", 0}, 285 {ACPI_DMT_UINT32, ACPI_AEST3_OFFSET (AcpiUid), "ACPI UID", 0}, 286 {ACPI_DMT_BUF16, ACPI_AEST3_OFFSET (VendorSpecificData), "Vendor Specific Data", 0}, 287 ACPI_DMT_TERMINATOR 288 }; 289 290 /* 3: Vendor Defined V2 */ 291 292 ACPI_DMTABLE_INFO AcpiDmTableInfoAestVendorV2Error[] = 293 { 294 {ACPI_DMT_UINT64, ACPI_AEST3A_OFFSET (AcpiHid), "ACPI HID", 0}, 295 {ACPI_DMT_UINT32, ACPI_AEST3A_OFFSET (AcpiUid), "ACPI UID", 0}, 296 {ACPI_DMT_BUF16, ACPI_AEST3A_OFFSET (VendorSpecificData), "Vendor Specific Data", 0}, 297 ACPI_DMT_TERMINATOR 298 }; 299 300 /* 4: Gic Error */ 301 302 ACPI_DMTABLE_INFO AcpiDmTableInfoAestGicError[] = 303 { 304 {ACPI_DMT_AEST_GIC, ACPI_AEST4_OFFSET (InterfaceType), "GIC Interface Type", 0}, 305 {ACPI_DMT_UINT32, ACPI_AEST4_OFFSET (InstanceId), "Instance ID", 0}, 306 ACPI_DMT_TERMINATOR 307 }; 308 309 /* 5: PCIe Error */ 310 311 ACPI_DMTABLE_INFO AcpiDmTableInfoAestPCIeError[] = 312 { 313 {ACPI_DMT_UINT32, ACPI_AEST5_OFFSET (IortNodeReference), "Iort Node Reference", 0}, 314 ACPI_DMT_TERMINATOR 315 }; 316 317 /* 6: Proxy Error */ 318 319 ACPI_DMTABLE_INFO AcpiDmTableInfoAestProxyError[] = 320 { 321 {ACPI_DMT_UINT64, ACPI_AEST6_OFFSET (NodeAddress), "Proxy Node Address", 0}, 322 ACPI_DMT_TERMINATOR 323 }; 324 325 /* Common AEST structures for subtables */ 326 327 #define ACPI_DM_AEST_INTERFACE_COMMON(a) \ 328 {ACPI_DMT_UINT32, ACPI_AEST0D##a##_OFFSET (Common.ErrorNodeDevice), "Arm Error Node Device", 0},\ 329 {ACPI_DMT_UINT32, ACPI_AEST0D##a##_OFFSET (Common.ProcessorAffinity), "Processor Affinity", 0}, \ 330 {ACPI_DMT_UINT64, ACPI_AEST0D##a##_OFFSET (Common.ErrorGroupRegisterBase), "Err-Group Register Addr", 0}, \ 331 {ACPI_DMT_UINT64, ACPI_AEST0D##a##_OFFSET (Common.FaultInjectRegisterBase), "Err-Inject Register Addr", 0}, \ 332 {ACPI_DMT_UINT64, ACPI_AEST0D##a##_OFFSET (Common.InterruptConfigRegisterBase), "IRQ-Config Register Addr", 0}, 333 334 /* AestXface: Node Interface Structure */ 335 336 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface[] = 337 { 338 {ACPI_DMT_AEST_XFACE, ACPI_AEST0D_OFFSET (Type), "Interface Type", 0}, 339 {ACPI_DMT_UINT24, ACPI_AEST0D_OFFSET (Reserved[0]), "Reserved", 0}, 340 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (Flags), "Flags (decoded below)", 0}, 341 {ACPI_DMT_FLAG0, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Shared Interface", 0}, 342 {ACPI_DMT_FLAG1, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Clear MISCx Registers", 0}, 343 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (Address), "Address", 0}, 344 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (ErrorRecordIndex), "Error Record Index", 0}, 345 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (ErrorRecordCount), "Error Record Count", 0}, 346 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (ErrorRecordImplemented),"Error Record Implemented", 0}, 347 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (ErrorStatusReporting), "Error Status Reporting", 0}, 348 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (AddressingMode), "Addressing Mode", 0}, 349 ACPI_DMT_TERMINATOR 350 }; 351 352 /* AestXface: Node Interface Structure V2 Header */ 353 354 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXfaceHeader[] = 355 { 356 {ACPI_DMT_AEST_XFACE, ACPI_AEST0DH_OFFSET (Type), "Interface Type", 0}, 357 {ACPI_DMT_UINT8, ACPI_AEST0DH_OFFSET (GroupFormat), "Group Format", 0}, 358 {ACPI_DMT_UINT16, ACPI_AEST0DH_OFFSET (Reserved[0]), "Reserved", 0}, 359 {ACPI_DMT_UINT32, ACPI_AEST0DH_OFFSET (Flags), "Flags (decoded below)", 0}, 360 {ACPI_DMT_FLAG0, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Shared Interface", 0}, 361 {ACPI_DMT_FLAG1, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Clear MISCx Registers", 0}, 362 {ACPI_DMT_FLAG2, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Error Node Device Valid", 0}, 363 {ACPI_DMT_FLAG3, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Affinity Type", 0}, 364 {ACPI_DMT_FLAG4, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Error group Address Valid", 0}, 365 {ACPI_DMT_FLAG5, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Fault Injection Address Valid", 0}, 366 {ACPI_DMT_FLAG7, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Interrupt Config Address valid", 0}, 367 {ACPI_DMT_UINT64, ACPI_AEST0DH_OFFSET (Address), "Address", 0}, 368 {ACPI_DMT_UINT32, ACPI_AEST0DH_OFFSET (ErrorRecordIndex), "Error Record Index", 0}, 369 {ACPI_DMT_UINT32, ACPI_AEST0DH_OFFSET (ErrorRecordCount), "Error Record Count", 0}, 370 ACPI_DMT_TERMINATOR 371 }; 372 373 /* AestXface: Node Interface Structure V2 4K Group Format */ 374 375 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface4k[] = 376 { 377 {ACPI_DMT_UINT64, ACPI_AEST0D4_OFFSET (ErrorRecordImplemented),"Error Record Implemented", 0}, 378 {ACPI_DMT_UINT64, ACPI_AEST0D4_OFFSET (ErrorStatusReporting), "Error Status Reporting", 0}, 379 {ACPI_DMT_UINT64, ACPI_AEST0D4_OFFSET (AddressingMode), "Addressing Mode", 0}, 380 ACPI_DM_AEST_INTERFACE_COMMON(4) 381 ACPI_DMT_TERMINATOR 382 }; 383 384 /* AestXface: Node Interface Structure V2 16K Group Format */ 385 386 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface16k[] = 387 { 388 {ACPI_DMT_BUF32, ACPI_AEST0D16_OFFSET (ErrorRecordImplemented[0]),"Error Record Implemented", 0}, 389 {ACPI_DMT_BUF32, ACPI_AEST0D16_OFFSET (ErrorStatusReporting[0]), "Error Status Reporting", 0}, 390 {ACPI_DMT_BUF32, ACPI_AEST0D16_OFFSET (AddressingMode[0]), "Addressing Mode", 0}, 391 ACPI_DM_AEST_INTERFACE_COMMON(16) 392 ACPI_DMT_TERMINATOR 393 }; 394 395 /* AestXface: Node Interface Structure V2 64K Group Format */ 396 397 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface64k[] = 398 { 399 {ACPI_DMT_BUF112, ACPI_AEST0D64_OFFSET (ErrorRecordImplemented[0]),"Error Record Implemented", 0}, 400 {ACPI_DMT_BUF112, ACPI_AEST0D64_OFFSET (ErrorStatusReporting[0]), "Error Status Reporting", 0}, 401 {ACPI_DMT_BUF112, ACPI_AEST0D64_OFFSET (AddressingMode[0]), "Addressing Mode", 0}, 402 ACPI_DM_AEST_INTERFACE_COMMON(64) 403 ACPI_DMT_TERMINATOR 404 }; 405 406 /* AestXrupt: Node Interrupt Structure */ 407 408 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXrupt[] = 409 { 410 {ACPI_DMT_AEST_XRUPT, ACPI_AEST0E_OFFSET (Type), "Interrupt Type", 0}, 411 {ACPI_DMT_UINT16, ACPI_AEST0E_OFFSET (Reserved), "Reserved", 0}, 412 {ACPI_DMT_UINT8, ACPI_AEST0E_OFFSET (Flags), "Flags (decoded below)", 0}, 413 {ACPI_DMT_FLAG0, ACPI_AEST0E_FLAG_OFFSET (Flags, 0), "Level Triggered", 0}, 414 {ACPI_DMT_UINT32, ACPI_AEST0E_OFFSET (Gsiv), "Gsiv", 0}, 415 {ACPI_DMT_UINT8, ACPI_AEST0E_OFFSET (IortId), "IortId", 0}, 416 {ACPI_DMT_UINT24, ACPI_AEST0E_OFFSET (Reserved1[0]), "Reserved", 0}, 417 ACPI_DMT_TERMINATOR 418 }; 419 420 421 /* AestXrupt: Node Interrupt Structure V2 */ 422 423 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXruptV2[] = 424 { 425 {ACPI_DMT_AEST_XRUPT, ACPI_AEST0EA_OFFSET (Type), "Interrupt Type", 0}, 426 {ACPI_DMT_UINT16, ACPI_AEST0EA_OFFSET (Reserved), "Reserved", 0}, 427 {ACPI_DMT_UINT8, ACPI_AEST0EA_OFFSET (Flags), "Flags (decoded below)", 0}, 428 {ACPI_DMT_FLAG0, ACPI_AEST0EA_FLAG_OFFSET (Flags, 0), "Level Triggered", 0}, 429 {ACPI_DMT_UINT32, ACPI_AEST0EA_OFFSET (Gsiv), "Gsiv", 0}, 430 {ACPI_DMT_UINT32, ACPI_AEST0EA_OFFSET (Reserved1[0]), "Reserved", 0}, 431 ACPI_DMT_TERMINATOR 432 }; 433 434 435 /******************************************************************************* 436 * 437 * ASF - Alert Standard Format table (Signature "ASF!") 438 * 439 ******************************************************************************/ 440 441 /* Common Subtable header (one per Subtable) */ 442 443 ACPI_DMTABLE_INFO AcpiDmTableInfoAsfHdr[] = 444 { 445 {ACPI_DMT_ASF, ACPI_ASF0_OFFSET (Header.Type), "Subtable Type", 0}, 446 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Header.Reserved), "Reserved", 0}, 447 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (Header.Length), "Length", DT_LENGTH}, 448 ACPI_DMT_TERMINATOR 449 }; 450 451 /* 0: ASF Information */ 452 453 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf0[] = 454 { 455 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinResetValue), "Minimum Reset Value", 0}, 456 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinPollInterval), "Minimum Polling Interval", 0}, 457 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (SystemId), "System ID", 0}, 458 {ACPI_DMT_UINT32, ACPI_ASF0_OFFSET (MfgId), "Manufacturer ID", 0}, 459 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Flags), "Flags", 0}, 460 {ACPI_DMT_UINT24, ACPI_ASF0_OFFSET (Reserved2[0]), "Reserved", 0}, 461 ACPI_DMT_TERMINATOR 462 }; 463 464 /* 1: ASF Alerts */ 465 466 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1[] = 467 { 468 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (AssertMask), "AssertMask", 0}, 469 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DeassertMask), "DeassertMask", 0}, 470 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (Alerts), "Alert Count", 0}, 471 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DataLength), "Alert Data Length", 0}, 472 ACPI_DMT_TERMINATOR 473 }; 474 475 /* 1a: ASF Alert data */ 476 477 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1a[] = 478 { 479 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Address), "Address", 0}, 480 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Command), "Command", 0}, 481 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Mask), "Mask", 0}, 482 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Value), "Value", 0}, 483 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorType), "SensorType", 0}, 484 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Type), "Type", 0}, 485 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Offset), "Offset", 0}, 486 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SourceType), "SourceType", 0}, 487 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Severity), "Severity", 0}, 488 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorNumber), "SensorNumber", 0}, 489 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Entity), "Entity", 0}, 490 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Instance), "Instance", 0}, 491 ACPI_DMT_TERMINATOR 492 }; 493 494 /* 2: ASF Remote Control */ 495 496 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2[] = 497 { 498 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (Controls), "Control Count", 0}, 499 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (DataLength), "Control Data Length", 0}, 500 {ACPI_DMT_UINT16, ACPI_ASF2_OFFSET (Reserved2), "Reserved", 0}, 501 ACPI_DMT_TERMINATOR 502 }; 503 504 /* 2a: ASF Control data */ 505 506 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2a[] = 507 { 508 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Function), "Function", 0}, 509 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Address), "Address", 0}, 510 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Command), "Command", 0}, 511 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Value), "Value", 0}, 512 ACPI_DMT_TERMINATOR 513 }; 514 515 /* 3: ASF RMCP Boot Options */ 516 517 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf3[] = 518 { 519 {ACPI_DMT_BUF7, ACPI_ASF3_OFFSET (Capabilities[0]), "Capabilities", 0}, 520 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (CompletionCode), "Completion Code", 0}, 521 {ACPI_DMT_UINT32, ACPI_ASF3_OFFSET (EnterpriseId), "Enterprise ID", 0}, 522 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (Command), "Command", 0}, 523 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (Parameter), "Parameter", 0}, 524 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (BootOptions), "Boot Options", 0}, 525 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (OemParameters), "Oem Parameters", 0}, 526 ACPI_DMT_TERMINATOR 527 }; 528 529 /* 4: ASF Address */ 530 531 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf4[] = 532 { 533 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (EpromAddress), "Eprom Address", 0}, 534 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (Devices), "Device Count", DT_COUNT}, 535 ACPI_DMT_TERMINATOR 536 }; 537 538 539 /******************************************************************************* 540 * 541 * ASPT - AMD Secure Processor table (Signature "ASPT") 542 * 543 ******************************************************************************/ 544 545 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt[] = 546 { 547 {ACPI_DMT_UINT32, ACPI_ASPT_OFFSET(NumEntries), "Number of Subtables", 0}, 548 ACPI_DMT_TERMINATOR 549 }; 550 551 /* Common Subtable header (one per Subtable) */ 552 ACPI_DMTABLE_INFO AcpiDmTableInfoAsptHdr[] = 553 { 554 {ACPI_DMT_ASPT, ACPI_ASPTH_OFFSET(Type), "Type", 0}, 555 {ACPI_DMT_UINT16, ACPI_ASPTH_OFFSET(Length), "Length", 0}, 556 ACPI_DMT_TERMINATOR 557 }; 558 559 /* 0: ASPT Global Registers */ 560 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt0[] = 561 { 562 {ACPI_DMT_UINT32, ACPI_ASPT0_OFFSET(Reserved), "Reserved", 0}, 563 {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(FeatureRegAddr), "Feature Register Address", 0}, 564 {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(IrqEnRegAddr), "Interrupt Enable Register Address", 0}, 565 {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(IrqStRegAddr), "Interrupt Status Register Address", 0}, 566 ACPI_DMT_TERMINATOR 567 }; 568 569 /* 1: ASPT SEV Mailbox Registers */ 570 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt1[] = 571 { 572 {ACPI_DMT_UINT8, ACPI_ASPT1_OFFSET(MboxIrqId), "Mailbox Interrupt ID", 0}, 573 {ACPI_DMT_UINT24, ACPI_ASPT1_OFFSET(Reserved[0]), "Reserved", 0}, 574 {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdRespRegAddr), "CmdResp Register Address", 0}, 575 {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdBufLoRegAddr), "CmdBufAddr_Lo Register Address", 0}, 576 {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdBufHiRegAddr), "CmdBufAddr_Hi Register Address", 0}, 577 ACPI_DMT_TERMINATOR 578 }; 579 580 /* 2: ASPT ACPI Maiblox Registers */ 581 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt2[] = 582 { 583 {ACPI_DMT_UINT32, ACPI_ASPT2_OFFSET(Reserved1), "Reserved", 0}, 584 {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(CmdRespRegAddr), "CmdResp Register Address", 0}, 585 {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(Reserved2[0]), "Reserved", 0}, 586 {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(Reserved2[1]), "Reserved", 0}, 587 ACPI_DMT_TERMINATOR 588 }; 589 590 /******************************************************************************* 591 * 592 * BDAT - BIOS Data ACPI Table 593 * 594 ******************************************************************************/ 595 596 ACPI_DMTABLE_INFO AcpiDmTableInfoBdat[] = 597 { 598 {ACPI_DMT_GAS, ACPI_BDAT_OFFSET (Gas), "BDAT Generic Address", 0}, 599 ACPI_DMT_TERMINATOR 600 }; 601 602 603 /******************************************************************************* 604 * 605 * BERT - Boot Error Record table 606 * 607 ******************************************************************************/ 608 609 ACPI_DMTABLE_INFO AcpiDmTableInfoBert[] = 610 { 611 {ACPI_DMT_UINT32, ACPI_BERT_OFFSET (RegionLength), "Boot Error Region Length", 0}, 612 {ACPI_DMT_UINT64, ACPI_BERT_OFFSET (Address), "Boot Error Region Address", 0}, 613 ACPI_DMT_TERMINATOR 614 }; 615 616 617 /******************************************************************************* 618 * 619 * BGRT - Boot Graphics Resource Table (ACPI 5.0) 620 * 621 ******************************************************************************/ 622 623 ACPI_DMTABLE_INFO AcpiDmTableInfoBgrt[] = 624 { 625 {ACPI_DMT_UINT16, ACPI_BGRT_OFFSET (Version), "Version", 0}, 626 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (Status), "Status (decoded below)", DT_FLAG}, 627 {ACPI_DMT_FLAG0, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Displayed", 0}, 628 {ACPI_DMT_FLAGS1, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Orientation Offset", 0}, 629 630 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (ImageType), "Image Type", 0}, 631 {ACPI_DMT_UINT64, ACPI_BGRT_OFFSET (ImageAddress), "Image Address", 0}, 632 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetX), "Image OffsetX", 0}, 633 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetY), "Image OffsetY", 0}, 634 ACPI_DMT_TERMINATOR 635 }; 636 637 638 /******************************************************************************* 639 * 640 * BOOT - Simple Boot Flag Table 641 * 642 ******************************************************************************/ 643 644 ACPI_DMTABLE_INFO AcpiDmTableInfoBoot[] = 645 { 646 {ACPI_DMT_UINT8, ACPI_BOOT_OFFSET (CmosIndex), "Boot Register Index", 0}, 647 {ACPI_DMT_UINT24, ACPI_BOOT_OFFSET (Reserved[0]), "Reserved", 0}, 648 ACPI_DMT_TERMINATOR 649 }; 650 651 /******************************************************************************* 652 * 653 * CDAT - Coherent Device Attribute Table 654 * 655 ******************************************************************************/ 656 657 /* Table header (not ACPI-compliant) */ 658 659 ACPI_DMTABLE_INFO AcpiDmTableInfoCdatTableHdr[] = 660 { 661 {ACPI_DMT_UINT32, ACPI_CDAT_OFFSET (Length), "CDAT Table Length", DT_LENGTH}, 662 {ACPI_DMT_UINT8, ACPI_CDAT_OFFSET (Revision), "Revision", 0}, 663 {ACPI_DMT_UINT8, ACPI_CDAT_OFFSET (Checksum), "Checksum", 0}, 664 {ACPI_DMT_UINT48, ACPI_CDAT_OFFSET (Reserved), "Reserved", 0}, 665 {ACPI_DMT_UINT32, ACPI_CDAT_OFFSET (Sequence), "Sequence", 0}, 666 ACPI_DMT_TERMINATOR 667 }; 668 669 /* Common subtable header */ 670 671 ACPI_DMTABLE_INFO AcpiDmTableInfoCdatHeader[] = 672 { 673 {ACPI_DMT_CDAT, ACPI_CDATH_OFFSET (Type), "Subtable Type", 0}, 674 {ACPI_DMT_UINT8, ACPI_CDATH_OFFSET (Reserved), "Reserved", 0}, 675 {ACPI_DMT_UINT16, ACPI_CDATH_OFFSET (Length), "Length", DT_LENGTH}, 676 ACPI_DMT_TERMINATOR 677 }; 678 679 /* Subtable 0: Device Scoped Memory Affinity Structure (DSMAS) */ 680 681 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat0[] = 682 { 683 {ACPI_DMT_UINT8, ACPI_CDAT0_OFFSET (DsmadHandle), "DSMAD Handle", 0}, 684 {ACPI_DMT_UINT8, ACPI_CDAT0_OFFSET (Flags), "Flags", 0}, 685 {ACPI_DMT_UINT16, ACPI_CDAT0_OFFSET (Reserved), "Reserved", 0}, 686 {ACPI_DMT_UINT64, ACPI_CDAT0_OFFSET (DpaBaseAddress), "DPA Base Address", 0}, 687 {ACPI_DMT_UINT64, ACPI_CDAT0_OFFSET (DpaLength), "DPA Length", 0}, 688 ACPI_DMT_TERMINATOR 689 }; 690 691 /* Subtable 1: Device scoped Latency and Bandwidth Information Structure (DSLBIS) */ 692 693 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat1[] = 694 { 695 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Handle), "Handle", 0}, 696 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Flags), "Flags", 0}, 697 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (DataType), "Data Type", 0}, 698 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Reserved), "Reserved", 0}, 699 {ACPI_DMT_UINT64, ACPI_CDAT1_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 700 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[0]), "Entry0", 0}, 701 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[1]), "Entry1", 0}, 702 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[2]), "Entry2", 0}, 703 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Reserved2), "Reserved", 0}, 704 ACPI_DMT_TERMINATOR 705 }; 706 707 /* Subtable 2: Device Scoped Memory Side Cache Information Structure (DSMSCIS) */ 708 709 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat2[] = 710 { 711 {ACPI_DMT_UINT8, ACPI_CDAT2_OFFSET (DsmasHandle), "DSMAS Handle", 0}, 712 {ACPI_DMT_UINT24, ACPI_CDAT2_OFFSET (Reserved[3]), "Reserved", 0}, 713 {ACPI_DMT_UINT64, ACPI_CDAT2_OFFSET (SideCacheSize), "Side Cache Size", 0}, 714 {ACPI_DMT_UINT32, ACPI_CDAT2_OFFSET (CacheAttributes), "Cache Attributes", 0}, 715 ACPI_DMT_TERMINATOR 716 }; 717 718 /* Subtable 3: Device Scoped Initiator Structure (DSIS) */ 719 720 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat3[] = 721 { 722 {ACPI_DMT_UINT8, ACPI_CDAT3_OFFSET (Flags), "Flags", 0}, 723 {ACPI_DMT_UINT8, ACPI_CDAT3_OFFSET (Handle), "Handle", 0}, 724 {ACPI_DMT_UINT16, ACPI_CDAT3_OFFSET (Reserved), "Reserved", 0}, 725 ACPI_DMT_TERMINATOR 726 }; 727 728 /* Subtable 4: Device Scoped EFI Memory Type Structure (DSEMTS) */ 729 730 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat4[] = 731 { 732 {ACPI_DMT_UINT8, ACPI_CDAT4_OFFSET (DsmasHandle), "DSMAS Handle", 0}, 733 {ACPI_DMT_UINT8, ACPI_CDAT4_OFFSET (MemoryType), "Memory Type", 0}, 734 {ACPI_DMT_UINT16, ACPI_CDAT4_OFFSET (Reserved), "Reserved", 0}, 735 {ACPI_DMT_UINT64, ACPI_CDAT4_OFFSET (DpaOffset), "DPA Offset", 0}, 736 {ACPI_DMT_UINT64, ACPI_CDAT4_OFFSET (RangeLength), "DPA Range Length", 0}, 737 ACPI_DMT_TERMINATOR 738 }; 739 740 /* Subtable 5: Switch Scoped Latency and Bandwidth Information Structure (SSLBIS) */ 741 742 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat5[] = 743 { 744 {ACPI_DMT_UINT8, ACPI_CDAT5_OFFSET (DataType), "Data Type", 0}, 745 {ACPI_DMT_UINT24, ACPI_CDAT5_OFFSET (Reserved), "Reserved", 0}, 746 {ACPI_DMT_UINT64, ACPI_CDAT5_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 747 ACPI_DMT_TERMINATOR 748 }; 749 750 /* Switch Scoped Latency and Bandwidth Entry (SSLBE) (For subtable 5 above) */ 751 752 ACPI_DMTABLE_INFO AcpiDmTableInfoCdatEntries[] = 753 { 754 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (PortxId), "Port X Id", 0}, 755 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (PortyId), "Port Y Id", 0}, 756 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (LatencyOrBandwidth), "Latency or Bandwidth", 0}, 757 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (Reserved), "Reserved", 0}, 758 ACPI_DMT_TERMINATOR 759 }; 760 761 762 /******************************************************************************* 763 * 764 * CEDT - CXL Early Discovery Table 765 * 766 ******************************************************************************/ 767 768 ACPI_DMTABLE_INFO AcpiDmTableInfoCedtHdr[] = 769 { 770 {ACPI_DMT_CEDT, ACPI_CEDT_OFFSET (Type), "Subtable Type", 0}, 771 {ACPI_DMT_UINT8, ACPI_CEDT_OFFSET (Reserved), "Reserved", 0}, 772 {ACPI_DMT_UINT16, ACPI_CEDT_OFFSET (Length), "Length", DT_LENGTH}, 773 ACPI_DMT_TERMINATOR 774 }; 775 776 /* 0: CXL Host Bridge Structure */ 777 778 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt0[] = 779 { 780 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Uid), "Associated host bridge", 0}, 781 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (CxlVersion), "Specification version", 0}, 782 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Reserved), "Reserved", 0}, 783 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Base), "Register base", 0}, 784 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Length), "Register length", 0}, 785 ACPI_DMT_TERMINATOR 786 }; 787 788 /* 1: CXL Fixed Memory Window Structure */ 789 790 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt1[] = 791 { 792 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (Reserved1), "Reserved", 0}, 793 {ACPI_DMT_UINT64, ACPI_CEDT1_OFFSET (BaseHpa), "Window base address", 0}, 794 {ACPI_DMT_UINT64, ACPI_CEDT1_OFFSET (WindowSize), "Window size", 0}, 795 {ACPI_DMT_UINT8, ACPI_CEDT1_OFFSET (InterleaveWays), "Interleave Members", 0}, 796 {ACPI_DMT_UINT8, ACPI_CEDT1_OFFSET (InterleaveArithmetic), "Interleave Arithmetic", 0}, 797 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (Reserved2), "Reserved", 0}, 798 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (Granularity), "Granularity", 0}, 799 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (Restrictions), "Restrictions", 0}, 800 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (QtgId), "QtgId", 0}, 801 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (InterleaveTargets), "First Target", 0}, 802 ACPI_DMT_TERMINATOR 803 }; 804 805 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt1_te[] = 806 { 807 {ACPI_DMT_UINT32, ACPI_CEDT1_TE_OFFSET (InterleaveTarget), "Next Target", 0}, 808 ACPI_DMT_TERMINATOR 809 }; 810 811 /* 2: CXL XOR Interleave Math Structure */ 812 813 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt2[] = 814 { 815 {ACPI_DMT_UINT16, ACPI_CEDT2_OFFSET (Reserved1), "Reserved", 0}, 816 {ACPI_DMT_UINT8, ACPI_CEDT2_OFFSET (Hbig), "Interleave Granularity", 0}, 817 {ACPI_DMT_UINT8, ACPI_CEDT2_OFFSET (NrXormaps), "Xormap List Count", 0}, 818 {ACPI_DMT_UINT64, ACPI_CEDT2_OFFSET (XormapList), "First Xormap", 0}, 819 ACPI_DMT_TERMINATOR 820 }; 821 822 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt2_te[] = 823 { 824 {ACPI_DMT_UINT64, ACPI_CEDT2_TE_OFFSET (Xormap), "Next Xormap", 0}, 825 ACPI_DMT_TERMINATOR 826 }; 827 828 /******************************************************************************* 829 * 830 * CPEP - Corrected Platform Error Polling table 831 * 832 ******************************************************************************/ 833 834 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep[] = 835 { 836 {ACPI_DMT_UINT64, ACPI_CPEP_OFFSET (Reserved), "Reserved", 0}, 837 ACPI_DMT_TERMINATOR 838 }; 839 840 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep0[] = 841 { 842 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Type), "Subtable Type", 0}, 843 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Length), "Length", DT_LENGTH}, 844 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Id), "Processor ID", 0}, 845 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Eid), "Processor EID", 0}, 846 {ACPI_DMT_UINT32, ACPI_CPEP0_OFFSET (Interval), "Polling Interval", 0}, 847 ACPI_DMT_TERMINATOR 848 }; 849 850 851 /******************************************************************************* 852 * 853 * CSRT - Core System Resource Table 854 * 855 ******************************************************************************/ 856 857 /* Main table consists only of the standard ACPI table header */ 858 859 /* Resource Group subtable */ 860 861 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt0[] = 862 { 863 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (Length), "Length", DT_LENGTH}, 864 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (VendorId), "Vendor ID", 0}, 865 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SubvendorId), "Subvendor ID", 0}, 866 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (DeviceId), "Device ID", 0}, 867 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (SubdeviceId), "Subdevice ID", 0}, 868 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Revision), "Revision", 0}, 869 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Reserved), "Reserved", 0}, 870 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SharedInfoLength), "Shared Info Length", 0}, 871 ACPI_DMT_TERMINATOR 872 }; 873 874 /* Shared Info subtable */ 875 876 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt1[] = 877 { 878 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MajorVersion), "Major Version", 0}, 879 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MinorVersion), "Minor Version", 0}, 880 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseLow), "MMIO Base Address Low", 0}, 881 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseHigh), "MMIO Base Address High", 0}, 882 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (GsiInterrupt), "GSI Interrupt", 0}, 883 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptPolarity), "Interrupt Polarity", 0}, 884 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptMode), "Interrupt Mode", 0}, 885 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (NumChannels), "Num Channels", 0}, 886 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (DmaAddressWidth), "DMA Address Width", 0}, 887 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (BaseRequestLine), "Base Request Line", 0}, 888 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (NumHandshakeSignals), "Num Handshake Signals", 0}, 889 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MaxBlockSize), "Max Block Size", 0}, 890 ACPI_DMT_TERMINATOR 891 }; 892 893 /* Resource Descriptor subtable */ 894 895 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2[] = 896 { 897 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Length), "Length", DT_LENGTH}, 898 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Type), "Type", 0}, 899 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Subtype), "Subtype", 0}, 900 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Uid), "UID", 0}, 901 ACPI_DMT_TERMINATOR 902 }; 903 904 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2a[] = 905 { 906 {ACPI_DMT_RAW_BUFFER, 0, "ResourceInfo", DT_OPTIONAL}, 907 ACPI_DMT_TERMINATOR 908 }; 909 910 911 /******************************************************************************* 912 * 913 * DBG2 - Debug Port Table 2 914 * 915 ******************************************************************************/ 916 917 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2[] = 918 { 919 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoOffset), "Info Offset", 0}, 920 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoCount), "Info Count", 0}, 921 ACPI_DMT_TERMINATOR 922 }; 923 924 /* Debug Device Information Subtable */ 925 926 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Device[] = 927 { 928 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (Revision), "Revision", 0}, 929 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Length), "Length", DT_LENGTH}, 930 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (RegisterCount), "Register Count", 0}, 931 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathLength), "Namepath Length", 0}, 932 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathOffset), "Namepath Offset", 0}, 933 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataLength), "OEM Data Length", DT_DESCRIBES_OPTIONAL}, 934 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataOffset), "OEM Data Offset", DT_DESCRIBES_OPTIONAL}, 935 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortType), "Port Type", 0}, 936 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortSubtype), "Port Subtype", 0}, 937 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Reserved), "Reserved", 0}, 938 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (BaseAddressOffset), "Base Address Offset", 0}, 939 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (AddressSizeOffset), "Address Size Offset", 0}, 940 ACPI_DMT_TERMINATOR 941 }; 942 943 /* Variable-length data for the subtable */ 944 945 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Addr[] = 946 { 947 {ACPI_DMT_GAS, 0, "Base Address Register", 0}, 948 ACPI_DMT_TERMINATOR 949 }; 950 951 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Size[] = 952 { 953 {ACPI_DMT_UINT32, 0, "Address Size", 0}, 954 ACPI_DMT_TERMINATOR 955 }; 956 957 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Name[] = 958 { 959 {ACPI_DMT_STRING, 0, "Namepath", 0}, 960 ACPI_DMT_TERMINATOR 961 }; 962 963 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2OemData[] = 964 { 965 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", DT_OPTIONAL}, 966 ACPI_DMT_TERMINATOR 967 }; 968 969 970 /******************************************************************************* 971 * 972 * DBGP - Debug Port 973 * 974 ******************************************************************************/ 975 976 ACPI_DMTABLE_INFO AcpiDmTableInfoDbgp[] = 977 { 978 {ACPI_DMT_UINT8, ACPI_DBGP_OFFSET (Type), "Interface Type", 0}, 979 {ACPI_DMT_UINT24, ACPI_DBGP_OFFSET (Reserved[0]), "Reserved", 0}, 980 {ACPI_DMT_GAS, ACPI_DBGP_OFFSET (DebugPort), "Debug Port Register", 0}, 981 ACPI_DMT_TERMINATOR 982 }; 983 984 985 /******************************************************************************* 986 * 987 * DMAR - DMA Remapping table 988 * 989 ******************************************************************************/ 990 991 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar[] = 992 { 993 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Width), "Host Address Width", 0}, 994 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Flags), "Flags", 0}, 995 {ACPI_DMT_BUF10, ACPI_DMAR_OFFSET (Reserved[0]), "Reserved", 0}, 996 ACPI_DMT_TERMINATOR 997 }; 998 999 /* Common Subtable header (one per Subtable) */ 1000 1001 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarHdr[] = 1002 { 1003 {ACPI_DMT_DMAR, ACPI_DMAR0_OFFSET (Header.Type), "Subtable Type", 0}, 1004 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Header.Length), "Length", DT_LENGTH}, 1005 ACPI_DMT_TERMINATOR 1006 }; 1007 1008 /* Common device scope entry */ 1009 1010 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarScope[] = 1011 { 1012 {ACPI_DMT_DMAR_SCOPE, ACPI_DMARS_OFFSET (EntryType), "Device Scope Type", 0}, 1013 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Length), "Entry Length", DT_LENGTH}, 1014 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Flags), "Flags", 0}, 1015 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Reserved), "Reserved", 0}, 1016 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (EnumerationId), "Enumeration ID", 0}, 1017 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Bus), "PCI Bus Number", 0}, 1018 ACPI_DMT_TERMINATOR 1019 }; 1020 1021 /* DMAR Subtables */ 1022 1023 /* 0: Hardware Unit Definition */ 1024 1025 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar0[] = 1026 { 1027 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Flags), "Flags", 0}, 1028 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Size), "Size (decoded below)", 0}, 1029 {ACPI_DMT_FLAGS4_0, ACPI_DMAR0_FLAG_OFFSET (Size,0), "Size (pages, log2)", 0}, 1030 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Segment), "PCI Segment Number", 0}, 1031 {ACPI_DMT_UINT64, ACPI_DMAR0_OFFSET (Address), "Register Base Address", 0}, 1032 ACPI_DMT_TERMINATOR 1033 }; 1034 1035 /* 1: Reserved Memory Definition */ 1036 1037 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar1[] = 1038 { 1039 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Reserved), "Reserved", 0}, 1040 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Segment), "PCI Segment Number", 0}, 1041 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (BaseAddress), "Base Address", 0}, 1042 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (EndAddress), "End Address (limit)", 0}, 1043 ACPI_DMT_TERMINATOR 1044 }; 1045 1046 /* 2: Root Port ATS Capability Definition */ 1047 1048 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar2[] = 1049 { 1050 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Flags), "Flags", 0}, 1051 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Reserved), "Reserved", 0}, 1052 {ACPI_DMT_UINT16, ACPI_DMAR2_OFFSET (Segment), "PCI Segment Number", 0}, 1053 ACPI_DMT_TERMINATOR 1054 }; 1055 1056 /* 3: Remapping Hardware Static Affinity Structure */ 1057 1058 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar3[] = 1059 { 1060 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (Reserved), "Reserved", 0}, 1061 {ACPI_DMT_UINT64, ACPI_DMAR3_OFFSET (BaseAddress), "Base Address", 0}, 1062 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (ProximityDomain), "Proximity Domain", 0}, 1063 ACPI_DMT_TERMINATOR 1064 }; 1065 1066 /* 4: ACPI Namespace Device Declaration Structure */ 1067 1068 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar4[] = 1069 { 1070 {ACPI_DMT_UINT24, ACPI_DMAR4_OFFSET (Reserved[0]), "Reserved", 0}, 1071 {ACPI_DMT_UINT8, ACPI_DMAR4_OFFSET (DeviceNumber), "Device Number", 0}, 1072 {ACPI_DMT_STRING, ACPI_DMAR4_OFFSET (DeviceName[0]), "Device Name", 0}, 1073 ACPI_DMT_TERMINATOR 1074 }; 1075 1076 /* 5: SoC Integrated Address Translation Cache */ 1077 1078 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar5[] = 1079 { 1080 {ACPI_DMT_UINT8, ACPI_DMAR5_OFFSET (Flags), "Flags", 0}, 1081 {ACPI_DMT_UINT8, ACPI_DMAR5_OFFSET (Reserved), "Reserved", 0}, 1082 {ACPI_DMT_UINT16, ACPI_DMAR5_OFFSET (Segment), "PCI Segment Number", 0}, 1083 ACPI_DMT_TERMINATOR 1084 }; 1085 1086 /* 6: SoC Integrated Device Property */ 1087 1088 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar6[] = 1089 { 1090 {ACPI_DMT_UINT16, ACPI_DMAR6_OFFSET (Reserved), "Reserved", 0}, 1091 {ACPI_DMT_UINT16, ACPI_DMAR6_OFFSET (Segment), "PCI Segment Number", 0}, 1092 ACPI_DMT_TERMINATOR 1093 }; 1094 1095 1096 /******************************************************************************* 1097 * 1098 * DRTM - Dynamic Root of Trust for Measurement table 1099 * 1100 ******************************************************************************/ 1101 1102 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm[] = 1103 { 1104 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryBaseAddress), "Entry Base Address", 0}, 1105 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryLength), "Entry Length", 0}, 1106 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (EntryAddress32), "Entry 32", 0}, 1107 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryAddress64), "Entry 64", 0}, 1108 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ExitAddress), "Exit Address", 0}, 1109 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (LogAreaAddress), "Log Area Start", 0}, 1110 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (LogAreaLength), "Log Area Length", 0}, 1111 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ArchDependentAddress), "Arch Dependent Address", 0}, 1112 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (Flags), "Flags (decoded below)", 0}, 1113 {ACPI_DMT_FLAG0, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Namespace in TCB", 0}, 1114 {ACPI_DMT_FLAG1, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on S3 Resume", 0}, 1115 {ACPI_DMT_FLAG2, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on DLME_Exit", 0}, 1116 {ACPI_DMT_FLAG3, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "PCR_Authorities Changed", 0}, 1117 ACPI_DMT_TERMINATOR 1118 }; 1119 1120 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0[] = 1121 { 1122 {ACPI_DMT_UINT32, ACPI_DRTM0_OFFSET (ValidatedTableCount), "Validated Table Count", DT_COUNT}, 1123 ACPI_DMT_TERMINATOR 1124 }; 1125 1126 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0a[] = 1127 { 1128 {ACPI_DMT_UINT64, 0, "Table Address", DT_OPTIONAL}, 1129 ACPI_DMT_TERMINATOR 1130 }; 1131 1132 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1[] = 1133 { 1134 {ACPI_DMT_UINT32, ACPI_DRTM1_OFFSET (ResourceCount), "Resource Count", DT_COUNT}, 1135 ACPI_DMT_TERMINATOR 1136 }; 1137 1138 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1a[] = 1139 { 1140 {ACPI_DMT_UINT56, ACPI_DRTM1a_OFFSET (Size[0]), "Size", DT_OPTIONAL}, 1141 {ACPI_DMT_UINT8, ACPI_DRTM1a_OFFSET (Type), "Type", 0}, 1142 {ACPI_DMT_FLAG0, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Resource Type", 0}, 1143 {ACPI_DMT_FLAG7, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Protections", 0}, 1144 {ACPI_DMT_UINT64, ACPI_DRTM1a_OFFSET (Address), "Address", 0}, 1145 ACPI_DMT_TERMINATOR 1146 }; 1147 1148 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm2[] = 1149 { 1150 {ACPI_DMT_UINT32, ACPI_DRTM2_OFFSET (DpsIdLength), "DLME Platform Id Length", DT_COUNT}, 1151 {ACPI_DMT_BUF16, ACPI_DRTM2_OFFSET (DpsId), "DLME Platform Id", DT_COUNT}, 1152 ACPI_DMT_TERMINATOR 1153 }; 1154 1155 1156 /******************************************************************************* 1157 * 1158 * ECDT - Embedded Controller Boot Resources Table 1159 * 1160 ******************************************************************************/ 1161 1162 ACPI_DMTABLE_INFO AcpiDmTableInfoEcdt[] = 1163 { 1164 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Control), "Command/Status Register", 0}, 1165 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Data), "Data Register", 0}, 1166 {ACPI_DMT_UINT32, ACPI_ECDT_OFFSET (Uid), "UID", 0}, 1167 {ACPI_DMT_UINT8, ACPI_ECDT_OFFSET (Gpe), "GPE Number", 0}, 1168 {ACPI_DMT_STRING, ACPI_ECDT_OFFSET (Id[0]), "Namepath", 0}, 1169 ACPI_DMT_TERMINATOR 1170 }; 1171 1172 1173 /******************************************************************************* 1174 * 1175 * EINJ - Error Injection table 1176 * 1177 ******************************************************************************/ 1178 1179 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj[] = 1180 { 1181 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (HeaderLength), "Injection Header Length", 0}, 1182 {ACPI_DMT_UINT8, ACPI_EINJ_OFFSET (Flags), "Flags", 0}, 1183 {ACPI_DMT_UINT24, ACPI_EINJ_OFFSET (Reserved[0]), "Reserved", 0}, 1184 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (Entries), "Injection Entry Count", 0}, 1185 ACPI_DMT_TERMINATOR 1186 }; 1187 1188 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj0[] = 1189 { 1190 {ACPI_DMT_EINJACT, ACPI_EINJ0_OFFSET (Action), "Action", 0}, 1191 {ACPI_DMT_EINJINST, ACPI_EINJ0_OFFSET (Instruction), "Instruction", 0}, 1192 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1193 {ACPI_DMT_FLAG0, ACPI_EINJ0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 1194 1195 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Reserved), "Reserved", 0}, 1196 {ACPI_DMT_GAS, ACPI_EINJ0_OFFSET (RegisterRegion), "Register Region", 0}, 1197 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Value), "Value", 0}, 1198 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Mask), "Mask", 0}, 1199 ACPI_DMT_TERMINATOR 1200 }; 1201 1202 1203 /******************************************************************************* 1204 * 1205 * ERDT - Enhanced Resource Director Technology table 1206 * 1207 ******************************************************************************/ 1208 1209 ACPI_DMTABLE_INFO AcpiDmTableInfoErdt[] = 1210 { 1211 {ACPI_DMT_UINT32, ACPI_ERDT_OFFSET (MaxClos), "Maximum supported CLOSID", 0}, 1212 {ACPI_DMT_BUF24, ACPI_ERDT_OFFSET (Reserved), "Reserved", 0}, 1213 ACPI_DMT_TERMINATOR 1214 }; 1215 1216 1217 /******************************************************************************* 1218 * 1219 * ERDT - Common Subtable Header 1220 * 1221 ******************************************************************************/ 1222 1223 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtHdr[] = 1224 { 1225 {ACPI_DMT_ERDT, ACPI_ERDT_HDR_OFFSET (Type), "Type", 0}, 1226 {ACPI_DMT_UINT16, ACPI_ERDT_HDR_OFFSET (Length), "Length", DT_LENGTH}, 1227 ACPI_DMT_TERMINATOR 1228 }; 1229 1230 1231 /******************************************************************************* 1232 * 1233 * RMDD - ERDT Resource Management Domain Description subtable 1234 * 1235 ******************************************************************************/ 1236 1237 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtRmdd[] = 1238 { 1239 {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1240 {ACPI_DMT_FLAG0, ACPI_ERDT_RMDD_FLAG_OFFSET (Flags,0), "L3 Domain", 0}, 1241 {ACPI_DMT_FLAG1, ACPI_ERDT_RMDD_FLAG_OFFSET (Flags,0), "I/O L3 Domain", 0}, 1242 {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (IO_l3_Slices), "I/O L3 Slices", 0}, 1243 {ACPI_DMT_UINT8, ACPI_ERDT_RMDD_OFFSET (IO_l3_Sets), "I/O L3 Sets", 0}, 1244 {ACPI_DMT_UINT8, ACPI_ERDT_RMDD_OFFSET (IO_l3_Ways), "I/O L3 Ways", 0}, 1245 {ACPI_DMT_UINT64, ACPI_ERDT_RMDD_OFFSET (Reserved), "Reserved", 0}, 1246 {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (DomainId), "Domain ID", 0}, 1247 {ACPI_DMT_UINT32, ACPI_ERDT_RMDD_OFFSET (MaxRmid), "Maximum supported RMID", 0}, 1248 {ACPI_DMT_UINT64, ACPI_ERDT_RMDD_OFFSET (CregBase), "Control Register Base Address", 0}, 1249 {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (CregSize), "Control Register Base Size", 0}, 1250 ACPI_DMT_TERMINATOR 1251 }; 1252 1253 1254 /******************************************************************************* 1255 * 1256 * RMDD - CACD CPU Agent Collection Description subtable 1257 * 1258 ******************************************************************************/ 1259 1260 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCacd[] = 1261 { 1262 {ACPI_DMT_UINT16, ACPI_ERDT_CACD_OFFSET (Reserved), "Reserved", 0}, 1263 {ACPI_DMT_UINT16, ACPI_ERDT_CACD_OFFSET (DomainId), "Domain ID", 0}, 1264 ACPI_DMT_TERMINATOR 1265 }; 1266 1267 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCacdX2apic[] = 1268 { 1269 {ACPI_DMT_UINT32, 0, "X2ApicID", DT_OPTIONAL}, 1270 ACPI_DMT_TERMINATOR 1271 }; 1272 1273 1274 /******************************************************************************* 1275 * 1276 * RMDD - DACD Device Agent Collection Description subtable 1277 * 1278 ******************************************************************************/ 1279 1280 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtDacd[] = 1281 { 1282 {ACPI_DMT_UINT16, ACPI_ERDT_DACD_OFFSET (Reserved), "Reserved", 0}, 1283 {ACPI_DMT_UINT16, ACPI_ERDT_DACD_OFFSET (DomainId), "Domain ID", 0}, 1284 ACPI_DMT_TERMINATOR 1285 }; 1286 1287 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtDacdScope[] = 1288 { 1289 {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (Header.Type), "PCIType", DT_OPTIONAL}, 1290 {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (Header.Length), "Length", DT_OPTIONAL}, 1291 {ACPI_DMT_UINT16, ACPI_ERDT_DACD_PATH_OFFSET (Segment), "Segment", DT_OPTIONAL}, 1292 {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (Reserved), "Reserved", DT_OPTIONAL}, 1293 {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (StartBus), "StartBus", DT_OPTIONAL}, 1294 ACPI_DMT_TERMINATOR 1295 }; 1296 1297 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtDacdPath[] = 1298 { 1299 {ACPI_DMT_UINT8, 0, "Path", DT_OPTIONAL}, 1300 ACPI_DMT_TERMINATOR 1301 }; 1302 1303 1304 /******************************************************************************* 1305 * 1306 * RMDD - Cache Monitoring Registers for CPU Agents subtable 1307 * 1308 ******************************************************************************/ 1309 1310 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCmrc[] = 1311 { 1312 {ACPI_DMT_UINT32, ACPI_ERDT_CMRC_OFFSET (Reserved1), "Reserved", 0}, 1313 {ACPI_DMT_UINT32, ACPI_ERDT_CMRC_OFFSET (Flags), "Flags", 0}, 1314 {ACPI_DMT_UINT8, ACPI_ERDT_CMRC_OFFSET (IndexFn), "Register Index Function", 0}, 1315 {ACPI_DMT_BUF11, ACPI_ERDT_CMRC_OFFSET (Reserved2), "Reserved", 0}, 1316 {ACPI_DMT_UINT64, ACPI_ERDT_CMRC_OFFSET (CmtRegBase), "CMT Register Base Address", 0}, 1317 {ACPI_DMT_UINT32, ACPI_ERDT_CMRC_OFFSET (CmtRegSize), "CMT Register Size", 0}, 1318 {ACPI_DMT_UINT16, ACPI_ERDT_CMRC_OFFSET (ClumpSize), "Clump Size", 0}, 1319 {ACPI_DMT_UINT16, ACPI_ERDT_CMRC_OFFSET (ClumpStride), "Clump Stride", 0}, 1320 {ACPI_DMT_UINT64, ACPI_ERDT_CMRC_OFFSET (UpScale), "Upscale factor", 0}, 1321 ACPI_DMT_TERMINATOR 1322 }; 1323 1324 1325 /******************************************************************************* 1326 * 1327 * RMDD - Memory-bandwidth Monitoring Registers for CPU agents subtable 1328 * 1329 ******************************************************************************/ 1330 1331 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtMmrc[] = 1332 { 1333 {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (Reserved1), "Reserved", 0}, 1334 {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (Flags), "Flags", 0}, 1335 {ACPI_DMT_UINT8, ACPI_ERDT_MMRC_OFFSET (IndexFn), "Register Index Function", 0}, 1336 {ACPI_DMT_BUF11, ACPI_ERDT_MMRC_OFFSET (Reserved2), "Reserved", 0}, 1337 {ACPI_DMT_UINT64, ACPI_ERDT_MMRC_OFFSET (RegBase), "MBM Register Base Address", 0}, 1338 {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (RegSize), "MBM Register Size", 0}, 1339 {ACPI_DMT_UINT8, ACPI_ERDT_MMRC_OFFSET (CounterWidth), "MBM Counter Width", 0}, 1340 {ACPI_DMT_UINT64, ACPI_ERDT_MMRC_OFFSET (UpScale), "Upscale factor", 0}, 1341 {ACPI_DMT_UINT56, ACPI_ERDT_MMRC_OFFSET (Reserved3), "Reserved", 0}, 1342 {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (CorrFactorListLen), "Corr Factor List Length", 0}, 1343 ACPI_DMT_TERMINATOR 1344 }; 1345 1346 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtMmrcCorrFactor[] = 1347 { 1348 {ACPI_DMT_UINT32, 0, "CorrFactor", DT_OPTIONAL}, 1349 ACPI_DMT_TERMINATOR 1350 }; 1351 1352 1353 /******************************************************************************* 1354 * 1355 * RMDD - Memory-bandwidth Allocation Registers for CPU agents subtable 1356 * 1357 ******************************************************************************/ 1358 1359 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtMarc[] = 1360 { 1361 {ACPI_DMT_UINT16, ACPI_ERDT_MARC_OFFSET (Reserved1), "Reserved", 0}, 1362 {ACPI_DMT_UINT16, ACPI_ERDT_MARC_OFFSET (Flags), "Flags", 0}, 1363 {ACPI_DMT_UINT8, ACPI_ERDT_MARC_OFFSET (IndexFn), "Register Index Function", 0}, 1364 {ACPI_DMT_UINT56, ACPI_ERDT_MARC_OFFSET (Reserved2), "Reserved", 0}, 1365 {ACPI_DMT_UINT64, ACPI_ERDT_MARC_OFFSET (RegBaseOpt), "MBA Register Opt Base Address", 0}, 1366 {ACPI_DMT_UINT64, ACPI_ERDT_MARC_OFFSET (RegBaseMin), "MBA Register Min Base Address", 0}, 1367 {ACPI_DMT_UINT64, ACPI_ERDT_MARC_OFFSET (RegBaseMax), "MBA Register Max Base Address", 0}, 1368 {ACPI_DMT_UINT32, ACPI_ERDT_MARC_OFFSET (MbaRegSize), "MBA Register Size", 0}, 1369 {ACPI_DMT_UINT32, ACPI_ERDT_MARC_OFFSET (MbaCtrlRange), "MBA Control Range", 0}, 1370 ACPI_DMT_TERMINATOR 1371 }; 1372 1373 1374 /******************************************************************************* 1375 * 1376 * RMDD - Cache Allocation Registers for CPU Agents subtable 1377 * 1378 ******************************************************************************/ 1379 1380 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCarc[] = 1381 { 1382 ACPI_DMT_TERMINATOR 1383 }; 1384 1385 1386 /******************************************************************************* 1387 * 1388 * RMDD - Cache Monitoring Registers for Device Agents subtable 1389 * 1390 ******************************************************************************/ 1391 1392 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCmrd[] = 1393 { 1394 {ACPI_DMT_UINT32, ACPI_ERDT_CMRD_OFFSET (Reserved1), "Reserved", 0}, 1395 {ACPI_DMT_UINT32, ACPI_ERDT_CMRD_OFFSET (Flags), "Flags", 0}, 1396 {ACPI_DMT_UINT8, ACPI_ERDT_CMRD_OFFSET (IndexFn), "Register Index Function", 0}, 1397 {ACPI_DMT_BUF11, ACPI_ERDT_CMRD_OFFSET (Reserved2), "Reserved", 0}, 1398 {ACPI_DMT_UINT64, ACPI_ERDT_CMRD_OFFSET (RegBase), "CMRD Register Base Address", 0}, 1399 {ACPI_DMT_UINT32, ACPI_ERDT_CMRD_OFFSET (RegSize), "CMRD Register Size", 0}, 1400 {ACPI_DMT_UINT16, ACPI_ERDT_CMRD_OFFSET (CmtRegOff), "Register Offset", 0}, 1401 {ACPI_DMT_UINT16, ACPI_ERDT_CMRD_OFFSET (CmtClumpSize), "Clump Size", 0}, 1402 {ACPI_DMT_UINT64, ACPI_ERDT_CMRD_OFFSET (UpScale), "Upscale factor", 0}, 1403 ACPI_DMT_TERMINATOR 1404 }; 1405 1406 1407 /******************************************************************************* 1408 * 1409 * RMDD - O Bandwidth Monitoring Registers for Device Agents subtable 1410 * 1411 ******************************************************************************/ 1412 1413 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtIbrd[] = 1414 { 1415 {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (Reserved1), "Reserved", 0}, 1416 {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (Flags), "Flags", 0}, 1417 {ACPI_DMT_UINT8, ACPI_ERDT_IBRD_OFFSET (IndexFn), "Register Index Function", 0}, 1418 {ACPI_DMT_BUF11, ACPI_ERDT_IBRD_OFFSET (Reserved2), "Reserved", 0}, 1419 {ACPI_DMT_UINT64, ACPI_ERDT_IBRD_OFFSET (RegBase), "IBRD Register Base Address", 0}, 1420 {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (RegSize), "IBRD Register Size", 0}, 1421 {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (TotalBwOffset), "TotalBw Offset", 0}, 1422 {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (IOMissBwOffset), "IO Miss Offset", 0}, 1423 {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (TotalBwClump), "TotalBw Clump", 0}, 1424 {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (IOMissBwClump), "IO Miss Clump", 0}, 1425 {ACPI_DMT_UINT56, ACPI_ERDT_IBRD_OFFSET (Reserved3), "Reserved", 0}, 1426 {ACPI_DMT_UINT8, ACPI_ERDT_IBRD_OFFSET (CounterWidth), "Counter Width", 0}, 1427 {ACPI_DMT_UINT64, ACPI_ERDT_IBRD_OFFSET (UpScale), "Upscale factor", 0}, 1428 {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (CorrFactorListLen), "Corr Factor List Length", 0}, 1429 ACPI_DMT_TERMINATOR 1430 }; 1431 1432 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtIbrdCorrFactor[] = 1433 { 1434 {ACPI_DMT_UINT32, 0, "CorrFactor", DT_OPTIONAL}, 1435 ACPI_DMT_TERMINATOR 1436 }; 1437 1438 1439 /******************************************************************************* 1440 * 1441 * RMDD - O bandwidth Allocation Registers for Device Agents subtable 1442 * 1443 ******************************************************************************/ 1444 1445 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtIbad[] = 1446 { 1447 ACPI_DMT_TERMINATOR 1448 }; 1449 1450 1451 /******************************************************************************* 1452 * 1453 * RMDD - Cache Allocation Registers for Device Agents subtable 1454 * 1455 ******************************************************************************/ 1456 1457 ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCard[] = 1458 { 1459 {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (Reserved1), "Reserved", 0}, 1460 {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (Flags), "Flags", 0}, 1461 {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (ContentionMask), "ContentionMask", 0}, 1462 {ACPI_DMT_UINT8, ACPI_ERDT_CARD_OFFSET (IndexFn), "Register Index Function", 0}, 1463 {ACPI_DMT_UINT56, ACPI_ERDT_CARD_OFFSET (Reserved2), "Register Index Function", 0}, 1464 {ACPI_DMT_UINT64, ACPI_ERDT_CARD_OFFSET (RegBase), "CARD Register Base Address", 0}, 1465 {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (RegSize), "CARD Register Size", 0}, 1466 {ACPI_DMT_UINT16, ACPI_ERDT_CARD_OFFSET (CatRegOffset), "CARD Register Offset", 0}, 1467 {ACPI_DMT_UINT16, ACPI_ERDT_CARD_OFFSET (CatRegBlockSize), "CARD Register Block Size", 0}, 1468 1469 ACPI_DMT_TERMINATOR 1470 }; 1471 1472 1473 /******************************************************************************* 1474 * 1475 * ERST - Error Record Serialization table 1476 * 1477 ******************************************************************************/ 1478 1479 ACPI_DMTABLE_INFO AcpiDmTableInfoErst[] = 1480 { 1481 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (HeaderLength), "Serialization Header Length", 0}, 1482 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Reserved), "Reserved", 0}, 1483 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Entries), "Instruction Entry Count", 0}, 1484 ACPI_DMT_TERMINATOR 1485 }; 1486 1487 ACPI_DMTABLE_INFO AcpiDmTableInfoErst0[] = 1488 { 1489 {ACPI_DMT_ERSTACT, ACPI_ERST0_OFFSET (Action), "Action", 0}, 1490 {ACPI_DMT_ERSTINST, ACPI_ERST0_OFFSET (Instruction), "Instruction", 0}, 1491 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1492 {ACPI_DMT_FLAG0, ACPI_ERST0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 1493 1494 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Reserved), "Reserved", 0}, 1495 {ACPI_DMT_GAS, ACPI_ERST0_OFFSET (RegisterRegion), "Register Region", 0}, 1496 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Value), "Value", 0}, 1497 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Mask), "Mask", 0}, 1498 ACPI_DMT_TERMINATOR 1499 }; 1500 1501 1502 /******************************************************************************* 1503 * 1504 * FPDT - Firmware Performance Data Table (ACPI 5.0) 1505 * 1506 ******************************************************************************/ 1507 1508 /* Main table consists of only the standard ACPI header - subtables follow */ 1509 1510 /* FPDT subtable header */ 1511 1512 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdtHdr[] = 1513 { 1514 {ACPI_DMT_UINT16, ACPI_FPDTH_OFFSET (Type), "Subtable Type", 0}, 1515 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Length), "Length", DT_LENGTH}, 1516 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Revision), "Revision", 0}, 1517 ACPI_DMT_TERMINATOR 1518 }; 1519 1520 /* 0: Firmware Basic Boot Performance Record */ 1521 1522 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt0[] = 1523 { 1524 {ACPI_DMT_UINT32, ACPI_FPDT0_OFFSET (Reserved), "Reserved", 0}, 1525 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "FPDT Boot Record Address", 0}, 1526 ACPI_DMT_TERMINATOR 1527 }; 1528 1529 /* 1: S3 Performance Table Pointer Record */ 1530 1531 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt1[] = 1532 { 1533 {ACPI_DMT_UINT32, ACPI_FPDT1_OFFSET (Reserved), "Reserved", 0}, 1534 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "S3PT Record Address", 0}, 1535 ACPI_DMT_TERMINATOR 1536 }; 1537 1538 #if 0 1539 /* Boot Performance Record, not supported at this time. */ 1540 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ResetEnd), "Reset End", 0}, 1541 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (LoadStart), "Load Image Start", 0}, 1542 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (StartupStart), "Start Image Start", 0}, 1543 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesEntry), "Exit Services Entry", 0}, 1544 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesExit), "Exit Services Exit", 0}, 1545 #endif 1546 1547 1548 /******************************************************************************* 1549 * 1550 * GTDT - Generic Timer Description Table 1551 * 1552 ******************************************************************************/ 1553 1554 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt[] = 1555 { 1556 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterBlockAddresss), "Counter Block Address", 0}, 1557 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (Reserved), "Reserved", 0}, 1558 ACPI_DMT_NEW_LINE, 1559 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Interrupt), "Secure EL1 Interrupt", 0}, 1560 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Flags), "EL1 Flags (decoded below)", DT_FLAG}, 1561 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Trigger Mode", 0}, 1562 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Polarity", 0}, 1563 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Always On", 0}, 1564 ACPI_DMT_NEW_LINE, 1565 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Interrupt), "Non-Secure EL1 Interrupt", 0}, 1566 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Flags), "NEL1 Flags (decoded below)", DT_FLAG}, 1567 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Trigger Mode", 0}, 1568 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Polarity", 0}, 1569 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Always On", 0}, 1570 ACPI_DMT_NEW_LINE, 1571 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 1572 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerFlags), "VT Flags (decoded below)", DT_FLAG}, 1573 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Trigger Mode", 0}, 1574 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Polarity", 0}, 1575 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Always On", 0}, 1576 ACPI_DMT_NEW_LINE, 1577 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Interrupt), "Non-Secure EL2 Interrupt", 0}, 1578 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Flags), "NEL2 Flags (decoded below)", DT_FLAG}, 1579 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Trigger Mode", 0}, 1580 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Polarity", 0}, 1581 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Always On", 0}, 1582 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterReadBlockAddress), "Counter Read Block Address", 0}, 1583 ACPI_DMT_NEW_LINE, 1584 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerCount), "Platform Timer Count", 0}, 1585 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerOffset), "Platform Timer Offset", 0}, 1586 ACPI_DMT_TERMINATOR 1587 }; 1588 1589 /* GDTD EL2 timer info. This table is appended to AcpiDmTableInfoGtdt for rev 3 and later */ 1590 1591 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtEl2[] = 1592 { 1593 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerGsiv), "Virtual EL2 Timer GSIV", 0}, 1594 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerFlags), "Virtual EL2 Timer Flags", 0}, 1595 ACPI_DMT_TERMINATOR 1596 }; 1597 1598 /* GTDT Subtable header (one per Subtable) */ 1599 1600 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtHdr[] = 1601 { 1602 {ACPI_DMT_GTDT, ACPI_GTDTH_OFFSET (Type), "Subtable Type", 0}, 1603 {ACPI_DMT_UINT16, ACPI_GTDTH_OFFSET (Length), "Length", DT_LENGTH}, 1604 ACPI_DMT_TERMINATOR 1605 }; 1606 1607 /* GTDT Subtables */ 1608 1609 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0[] = 1610 { 1611 {ACPI_DMT_UINT8, ACPI_GTDT0_OFFSET (Reserved), "Reserved", 0}, 1612 {ACPI_DMT_UINT64, ACPI_GTDT0_OFFSET (BlockAddress), "Block Address", 0}, 1613 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerCount), "Timer Count", 0}, 1614 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerOffset), "Timer Offset", 0}, 1615 ACPI_DMT_TERMINATOR 1616 }; 1617 1618 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0a[] = 1619 { 1620 {ACPI_DMT_UINT8 , ACPI_GTDT0a_OFFSET (FrameNumber), "Frame Number", 0}, 1621 {ACPI_DMT_UINT24, ACPI_GTDT0a_OFFSET (Reserved[0]), "Reserved", 0}, 1622 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (BaseAddress), "Base Address", 0}, 1623 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (El0BaseAddress), "EL0 Base Address", 0}, 1624 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1625 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerFlags), "Timer Flags (decoded below)", 0}, 1626 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1627 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1628 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 1629 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerFlags), "Virtual Timer Flags (decoded below)", 0}, 1630 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Trigger Mode", 0}, 1631 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Polarity", 0}, 1632 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (CommonFlags), "Common Flags (decoded below)", 0}, 1633 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Secure", 0}, 1634 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Always On", 0}, 1635 ACPI_DMT_TERMINATOR 1636 }; 1637 1638 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt1[] = 1639 { 1640 {ACPI_DMT_UINT8, ACPI_GTDT1_OFFSET (Reserved), "Reserved", 0}, 1641 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (RefreshFrameAddress), "Refresh Frame Address", 0}, 1642 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (ControlFrameAddress), "Control Frame Address", 0}, 1643 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1644 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerFlags), "Timer Flags (decoded below)", DT_FLAG}, 1645 {ACPI_DMT_FLAG0, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1646 {ACPI_DMT_FLAG1, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1647 {ACPI_DMT_FLAG2, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Security", 0}, 1648 ACPI_DMT_TERMINATOR 1649 }; 1650 1651 1652 /******************************************************************************* 1653 * 1654 * HEST - Hardware Error Source table 1655 * 1656 ******************************************************************************/ 1657 1658 ACPI_DMTABLE_INFO AcpiDmTableInfoHest[] = 1659 { 1660 {ACPI_DMT_UINT32, ACPI_HEST_OFFSET (ErrorSourceCount), "Error Source Count", 0}, 1661 ACPI_DMT_TERMINATOR 1662 }; 1663 1664 /* Common HEST structures for subtables */ 1665 1666 #define ACPI_DM_HEST_HEADER \ 1667 {ACPI_DMT_HEST, ACPI_HEST0_OFFSET (Header.Type), "Subtable Type", 0}, \ 1668 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Header.SourceId), "Source Id", 0} 1669 1670 #define ACPI_DM_HEST_AER \ 1671 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved1), "Reserved", 0}, \ 1672 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Flags), "Flags (decoded below)", DT_FLAG}, \ 1673 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Firmware First", 0}, \ 1674 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Global", 0}, \ 1675 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Enabled), "Enabled", 0}, \ 1676 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.RecordsToPreallocate), "Records To Preallocate", 0}, \ 1677 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.MaxSectionsPerRecord), "Max Sections Per Record", 0}, \ 1678 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.Bus), "Bus", 0}, \ 1679 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Device), "Device", 0}, \ 1680 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Function), "Function", 0}, \ 1681 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.DeviceControl), "DeviceControl", 0}, \ 1682 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved2), "Reserved", 0}, \ 1683 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableMask), "Uncorrectable Mask", 0}, \ 1684 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableSeverity), "Uncorrectable Severity", 0}, \ 1685 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.CorrectableMask), "Correctable Mask", 0}, \ 1686 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.AdvancedCapabilities), "Advanced Capabilities", 0} 1687 1688 1689 /* HEST Subtables */ 1690 1691 /* 0: IA32 Machine Check Exception */ 1692 1693 ACPI_DMTABLE_INFO AcpiDmTableInfoHest0[] = 1694 { 1695 ACPI_DM_HEST_HEADER, 1696 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Reserved1), "Reserved1", 0}, 1697 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1698 {ACPI_DMT_FLAG0, ACPI_HEST0_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1699 {ACPI_DMT_FLAG2, ACPI_HEST0_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1700 1701 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Enabled), "Enabled", 0}, 1702 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1703 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1704 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalCapabilityData), "Global Capability Data", 0}, 1705 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalControlData), "Global Control Data", 0}, 1706 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1707 {ACPI_DMT_UINT56, ACPI_HEST0_OFFSET (Reserved3[0]), "Reserved2", 0}, 1708 ACPI_DMT_TERMINATOR 1709 }; 1710 1711 /* 1: IA32 Corrected Machine Check */ 1712 1713 ACPI_DMTABLE_INFO AcpiDmTableInfoHest1[] = 1714 { 1715 ACPI_DM_HEST_HEADER, 1716 {ACPI_DMT_UINT16, ACPI_HEST1_OFFSET (Reserved1), "Reserved1", 0}, 1717 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1718 {ACPI_DMT_FLAG0, ACPI_HEST1_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1719 {ACPI_DMT_FLAG2, ACPI_HEST1_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1720 1721 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Enabled), "Enabled", 0}, 1722 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1723 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1724 {ACPI_DMT_HESTNTFY, ACPI_HEST1_OFFSET (Notify), "Notify", 0}, 1725 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1726 {ACPI_DMT_UINT24, ACPI_HEST1_OFFSET (Reserved2[0]), "Reserved2", 0}, 1727 ACPI_DMT_TERMINATOR 1728 }; 1729 1730 /* 2: IA32 Non-Maskable Interrupt */ 1731 1732 ACPI_DMTABLE_INFO AcpiDmTableInfoHest2[] = 1733 { 1734 ACPI_DM_HEST_HEADER, 1735 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (Reserved), "Reserved", 0}, 1736 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1737 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1738 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1739 ACPI_DMT_TERMINATOR 1740 }; 1741 1742 /* 6: PCI Express Root Port AER */ 1743 1744 ACPI_DMTABLE_INFO AcpiDmTableInfoHest6[] = 1745 { 1746 ACPI_DM_HEST_HEADER, 1747 ACPI_DM_HEST_AER, 1748 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (RootErrorCommand), "Root Error Command", 0}, 1749 ACPI_DMT_TERMINATOR 1750 }; 1751 1752 /* 7: PCI Express AER (AER Endpoint) */ 1753 1754 ACPI_DMTABLE_INFO AcpiDmTableInfoHest7[] = 1755 { 1756 ACPI_DM_HEST_HEADER, 1757 ACPI_DM_HEST_AER, 1758 ACPI_DMT_TERMINATOR 1759 }; 1760 1761 /* 8: PCI Express/PCI-X Bridge AER */ 1762 1763 ACPI_DMTABLE_INFO AcpiDmTableInfoHest8[] = 1764 { 1765 ACPI_DM_HEST_HEADER, 1766 ACPI_DM_HEST_AER, 1767 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableMask2), "2nd Uncorrectable Mask", 0}, 1768 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableSeverity2), "2nd Uncorrectable Severity", 0}, 1769 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (AdvancedCapabilities2), "2nd Advanced Capabilities", 0}, 1770 ACPI_DMT_TERMINATOR 1771 }; 1772 1773 /* 9: Generic Hardware Error Source */ 1774 1775 ACPI_DMTABLE_INFO AcpiDmTableInfoHest9[] = 1776 { 1777 ACPI_DM_HEST_HEADER, 1778 {ACPI_DMT_UINT16, ACPI_HEST9_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1779 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Reserved), "Reserved", 0}, 1780 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Enabled), "Enabled", 0}, 1781 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1782 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1783 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1784 {ACPI_DMT_GAS, ACPI_HEST9_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1785 {ACPI_DMT_HESTNTFY, ACPI_HEST9_OFFSET (Notify), "Notify", 0}, 1786 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1787 ACPI_DMT_TERMINATOR 1788 }; 1789 1790 /* 10: Generic Hardware Error Source - Version 2 */ 1791 1792 ACPI_DMTABLE_INFO AcpiDmTableInfoHest10[] = 1793 { 1794 ACPI_DM_HEST_HEADER, 1795 {ACPI_DMT_UINT16, ACPI_HEST10_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1796 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Reserved), "Reserved", 0}, 1797 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Enabled), "Enabled", 0}, 1798 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1799 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1800 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1801 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1802 {ACPI_DMT_HESTNTFY, ACPI_HEST10_OFFSET (Notify), "Notify", 0}, 1803 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1804 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ReadAckRegister), "Read Ack Register", 0}, 1805 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckPreserve), "Read Ack Preserve", 0}, 1806 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckWrite), "Read Ack Write", 0}, 1807 ACPI_DMT_TERMINATOR 1808 }; 1809 1810 /* 11: IA32 Deferred Machine Check */ 1811 1812 ACPI_DMTABLE_INFO AcpiDmTableInfoHest11[] = 1813 { 1814 ACPI_DM_HEST_HEADER, 1815 {ACPI_DMT_UINT16, ACPI_HEST11_OFFSET (Reserved1), "Reserved1", 0}, 1816 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1817 {ACPI_DMT_FLAG0, ACPI_HEST11_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1818 {ACPI_DMT_FLAG2, ACPI_HEST11_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1819 1820 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Enabled), "Enabled", 0}, 1821 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1822 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1823 {ACPI_DMT_HESTNTFY, ACPI_HEST11_OFFSET (Notify), "Notify", 0}, 1824 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1825 {ACPI_DMT_UINT24, ACPI_HEST11_OFFSET (Reserved2[0]), "Reserved2", 0}, 1826 ACPI_DMT_TERMINATOR 1827 }; 1828 1829 /* Notification Structure */ 1830 1831 ACPI_DMTABLE_INFO AcpiDmTableInfoHestNotify[] = 1832 { 1833 {ACPI_DMT_HESTNTYP, ACPI_HESTN_OFFSET (Type), "Notify Type", 0}, 1834 {ACPI_DMT_UINT8, ACPI_HESTN_OFFSET (Length), "Notify Length", DT_LENGTH}, 1835 {ACPI_DMT_UINT16, ACPI_HESTN_OFFSET (ConfigWriteEnable), "Configuration Write Enable", 0}, 1836 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollInterval), "PollInterval", 0}, 1837 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (Vector), "Vector", 0}, 1838 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdValue), "Polling Threshold Value", 0}, 1839 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdWindow), "Polling Threshold Window", 0}, 1840 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdValue), "Error Threshold Value", 0}, 1841 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdWindow), "Error Threshold Window", 0}, 1842 ACPI_DMT_TERMINATOR 1843 }; 1844 1845 1846 /* 1847 * IA32 Error Bank(s) - Follows the ACPI_HEST_IA_MACHINE_CHECK and 1848 * ACPI_HEST_IA_CORRECTED structures. 1849 */ 1850 ACPI_DMTABLE_INFO AcpiDmTableInfoHestBank[] = 1851 { 1852 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (BankNumber), "Bank Number", 0}, 1853 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (ClearStatusOnInit), "Clear Status On Init", 0}, 1854 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (StatusFormat), "Status Format", 0}, 1855 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (Reserved), "Reserved", 0}, 1856 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (ControlRegister), "Control Register", 0}, 1857 {ACPI_DMT_UINT64, ACPI_HESTB_OFFSET (ControlData), "Control Data", 0}, 1858 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (StatusRegister), "Status Register", 0}, 1859 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (AddressRegister), "Address Register", 0}, 1860 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (MiscRegister), "Misc Register", 0}, 1861 ACPI_DMT_TERMINATOR 1862 }; 1863 1864 1865 /******************************************************************************* 1866 * 1867 * HMAT - Heterogeneous Memory Attributes Table 1868 * 1869 ******************************************************************************/ 1870 1871 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat[] = 1872 { 1873 {ACPI_DMT_UINT32, ACPI_HMAT_OFFSET (Reserved), "Reserved", 0}, 1874 ACPI_DMT_TERMINATOR 1875 }; 1876 1877 /* Common HMAT structure header (one per Subtable) */ 1878 1879 ACPI_DMTABLE_INFO AcpiDmTableInfoHmatHdr[] = 1880 { 1881 {ACPI_DMT_HMAT, ACPI_HMATH_OFFSET (Type), "Structure Type", 0}, 1882 {ACPI_DMT_UINT16, ACPI_HMATH_OFFSET (Reserved), "Reserved", 0}, 1883 {ACPI_DMT_UINT32, ACPI_HMATH_OFFSET (Length), "Length", 0}, 1884 ACPI_DMT_TERMINATOR 1885 }; 1886 1887 /* HMAT subtables */ 1888 1889 /* 0x00: Memory proximity domain attributes */ 1890 1891 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat0[] = 1892 { 1893 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1894 {ACPI_DMT_FLAG0, ACPI_HMAT0_FLAG_OFFSET (Flags,0), "Processor Proximity Domain Valid", 0}, 1895 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Reserved1), "Reserved1", 0}, 1896 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (InitiatorPD), "Attached Initiator Proximity Domain", 0}, 1897 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1898 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (Reserved2), "Reserved2", 0}, 1899 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved3), "Reserved3", 0}, 1900 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved4), "Reserved4", 0}, 1901 ACPI_DMT_TERMINATOR 1902 }; 1903 1904 /* 0x01: System Locality Latency and Bandwidth Information */ 1905 1906 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1[] = 1907 { 1908 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Flags), "Flags (decoded below)", 0}, 1909 {ACPI_DMT_FLAGS4_0, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Memory Hierarchy", 0}, /* First 4 bits */ 1910 {ACPI_DMT_FLAG4, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Use Minimum Transfer Size", 0}, 1911 {ACPI_DMT_FLAG5, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Non-sequential Transfers", 0}, 1912 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (DataType), "Data Type", 0}, 1913 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (MinTransferSize), "Minimum Transfer Size", 0}, 1914 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Reserved1), "Reserved1", 0}, 1915 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfInitiatorPDs), "Initiator Proximity Domains #", 0}, 1916 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfTargetPDs), "Target Proximity Domains #", 0}, 1917 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (Reserved2), "Reserved2", 0}, 1918 {ACPI_DMT_UINT64, ACPI_HMAT1_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 1919 ACPI_DMT_TERMINATOR 1920 }; 1921 1922 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1a[] = 1923 { 1924 {ACPI_DMT_UINT32, 0, "Initiator Proximity Domain List", DT_OPTIONAL}, 1925 ACPI_DMT_TERMINATOR 1926 }; 1927 1928 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1b[] = 1929 { 1930 {ACPI_DMT_UINT32, 0, "Target Proximity Domain List", DT_OPTIONAL}, 1931 ACPI_DMT_TERMINATOR 1932 }; 1933 1934 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1c[] = 1935 { 1936 {ACPI_DMT_UINT16, 0, "Entry", DT_OPTIONAL}, 1937 ACPI_DMT_TERMINATOR 1938 }; 1939 1940 /* 0x02: Memory Side Cache Information */ 1941 1942 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2[] = 1943 { 1944 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1945 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (Reserved1), "Reserved1", 0}, 1946 {ACPI_DMT_UINT64, ACPI_HMAT2_OFFSET (CacheSize), "Memory Side Cache Size", 0}, 1947 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (CacheAttributes), "Cache Attributes (decoded below)", 0}, 1948 {ACPI_DMT_FLAGS4_0, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Total Cache Levels", 0}, 1949 {ACPI_DMT_FLAGS4_4, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Level", 0}, 1950 {ACPI_DMT_FLAGS4_8, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Associativity", 0}, 1951 {ACPI_DMT_FLAGS4_12, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Write Policy", 0}, 1952 {ACPI_DMT_FLAGS16_16, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Line Size", 0}, 1953 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (AddressMode), "Address Mode", 0}, 1954 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (NumberOfSMBIOSHandles), "SMBIOS Handle #", 0}, 1955 ACPI_DMT_TERMINATOR 1956 }; 1957 1958 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2a[] = 1959 { 1960 {ACPI_DMT_UINT16, 0, "SMBIOS Handle", DT_OPTIONAL}, 1961 ACPI_DMT_TERMINATOR 1962 }; 1963 1964 1965 /******************************************************************************* 1966 * 1967 * HPET - High Precision Event Timer table 1968 * 1969 ******************************************************************************/ 1970 1971 ACPI_DMTABLE_INFO AcpiDmTableInfoHpet[] = 1972 { 1973 {ACPI_DMT_UINT32, ACPI_HPET_OFFSET (Id), "Hardware Block ID", 0}, 1974 {ACPI_DMT_GAS, ACPI_HPET_OFFSET (Address), "Timer Block Register", 0}, 1975 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Sequence), "Sequence Number", 0}, 1976 {ACPI_DMT_UINT16, ACPI_HPET_OFFSET (MinimumTick), "Minimum Clock Ticks", 0}, 1977 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1978 {ACPI_DMT_FLAG0, ACPI_HPET_FLAG_OFFSET (Flags,0), "4K Page Protect", 0}, 1979 {ACPI_DMT_FLAG1, ACPI_HPET_FLAG_OFFSET (Flags,0), "64K Page Protect", 0}, 1980 ACPI_DMT_TERMINATOR 1981 }; 1982 /*! [End] no source code translation !*/ 1983
Indexes created Sun Sep 21 16:09:51 GMT 2025