1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo2 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /* 8 * Copyright (C) 2000 - 2025, Intel Corp. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 */ 43 44 #include "acpi.h" 45 #include "accommon.h" 46 #include "acdisasm.h" 47 #include "actbinfo.h" 48 49 /* This module used for application-level code only */ 50 51 #define _COMPONENT ACPI_CA_DISASSEMBLER 52 ACPI_MODULE_NAME ("dmtbinfo2") 53 54 /* 55 * How to add a new table: 56 * 57 * - Add the C table definition to the actbl1.h or actbl2.h header. 58 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 59 * - Define the table in this file (for the disassembler). If any 60 * new data types are required (ACPI_DMT_*), see below. 61 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 62 * in acdisam.h 63 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 64 * If a simple table (with no subtables), no disassembly code is needed. 65 * Otherwise, create the AcpiDmDump* function for to disassemble the table 66 * and add it to the dmtbdump.c file. 67 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 68 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 69 * - Create a template for the new table 70 * - Add data table compiler support 71 * 72 * How to add a new data type (ACPI_DMT_*): 73 * 74 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 75 * - Add length and implementation cases in dmtable.c (disassembler) 76 * - Add type and length cases in dtutils.c (DT compiler) 77 */ 78 79 /* 80 * Remaining tables are not consumed directly by the ACPICA subsystem 81 */ 82 83 /******************************************************************************* 84 * 85 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface 86 * 87 * Conforms to "ACPI for Arm Components 1.1, Platform Design Document" 88 * ARM DEN0093 v1.1 89 * 90 ******************************************************************************/ 91 92 ACPI_DMTABLE_INFO AcpiDmTableInfoAgdi[] = 93 { 94 {ACPI_DMT_UINT8, ACPI_AGDI_OFFSET (Flags), "Flags (decoded below)", 0}, 95 {ACPI_DMT_FLAG0, ACPI_AGDI_FLAG_OFFSET (Flags, 0), "Signalling mode", 0}, 96 {ACPI_DMT_UINT24, ACPI_AGDI_OFFSET (Reserved[0]), "Reserved", 0}, 97 {ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (SdeiEvent), "SdeiEvent", 0}, 98 {ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (Gsiv), "Gsiv", 0}, 99 ACPI_DMT_TERMINATOR 100 }; 101 102 103 /******************************************************************************* 104 * 105 * APMT - ARM Performance Monitoring Unit Table 106 * 107 * Conforms to: 108 * ARM Performance Monitoring Unit Architecture 1.0 Platform Design Document 109 * ARM DEN0117 v1.0 November 25, 2021 110 * 111 ******************************************************************************/ 112 113 ACPI_DMTABLE_INFO AcpiDmTableInfoApmtNode[] = 114 { 115 {ACPI_DMT_UINT16, ACPI_APMTN_OFFSET (Length), "Length of APMT Node", 0}, 116 {ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Flags), "Node Flags", 0}, 117 {ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Dual Page Extension", 0}, 118 {ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Processor Affinity Type", 0}, 119 {ACPI_DMT_FLAG2, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "64-bit Atomic Support", 0}, 120 {ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Type), "Node Type", 0}, 121 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Id), "Unique Node Identifier", 0}, 122 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (InstPrimary), "Primary Node Instance", 0}, 123 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (InstSecondary), "Secondary Node Instance", 0}, 124 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress0), "Page 0 Base Address", 0}, 125 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress1), "Page 1 Base Address", 0}, 126 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrq), "Overflow Interrupt ID", 0}, 127 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Reserved), "Reserved", 0}, 128 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrqFlags), "Overflow Interrupt Flags", 0}, 129 {ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Mode", 0}, 130 {ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Type", 0}, 131 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ProcAffinity), "Processor Affinity", 0}, 132 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ImplId), "Implementation ID", 0}, 133 ACPI_DMT_TERMINATOR 134 }; 135 136 137 /******************************************************************************* 138 * 139 * IORT - IO Remapping Table 140 * 141 ******************************************************************************/ 142 143 ACPI_DMTABLE_INFO AcpiDmTableInfoIort[] = 144 { 145 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeCount), "Node Count", 0}, 146 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeOffset), "Node Offset", 0}, 147 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (Reserved), "Reserved", 0}, 148 ACPI_DMT_TERMINATOR 149 }; 150 151 /* Optional padding field */ 152 153 ACPI_DMTABLE_INFO AcpiDmTableInfoIortPad[] = 154 { 155 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 156 ACPI_DMT_TERMINATOR 157 }; 158 159 /* Common Subtable header (one per Subtable) */ 160 161 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr[] = 162 { 163 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 164 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 165 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 166 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Reserved", 0}, 167 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 168 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 169 ACPI_DMT_TERMINATOR 170 }; 171 172 /* Common Subtable header (one per Subtable)- Revision 3 */ 173 174 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr3[] = 175 { 176 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 177 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 178 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 179 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Identifier", 0}, 180 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 181 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 182 ACPI_DMT_TERMINATOR 183 }; 184 185 ACPI_DMTABLE_INFO AcpiDmTableInfoIortMap[] = 186 { 187 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (InputBase), "Input base", DT_OPTIONAL}, 188 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (IdCount), "ID Count", 0}, 189 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputBase), "Output Base", 0}, 190 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputReference), "Output Reference", 0}, 191 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (Flags), "Flags (decoded below)", 0}, 192 {ACPI_DMT_FLAG0, ACPI_IORTM_FLAG_OFFSET (Flags, 0), "Single Mapping", 0}, 193 ACPI_DMT_TERMINATOR 194 }; 195 196 ACPI_DMTABLE_INFO AcpiDmTableInfoIortAcc[] = 197 { 198 {ACPI_DMT_UINT32, ACPI_IORTA_OFFSET (CacheCoherency), "Cache Coherency", 0}, 199 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (Hints), "Hints (decoded below)", 0}, 200 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Transient", 0}, 201 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Write Allocate", 0}, 202 {ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Read Allocate", 0}, 203 {ACPI_DMT_FLAG3, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Override", 0}, 204 {ACPI_DMT_UINT16, ACPI_IORTA_OFFSET (Reserved), "Reserved", 0}, 205 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (MemoryFlags), "Memory Flags (decoded below)", 0}, 206 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Coherency", 0}, 207 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Device Attribute", 0}, 208 {ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Ensured Coherency of Accesses", 0}, 209 ACPI_DMT_TERMINATOR 210 }; 211 212 /* IORT subtables */ 213 214 /* 0x00: ITS Group */ 215 216 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0[] = 217 { 218 {ACPI_DMT_UINT32, ACPI_IORT0_OFFSET (ItsCount), "ItsCount", 0}, 219 ACPI_DMT_TERMINATOR 220 }; 221 222 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0a[] = 223 { 224 {ACPI_DMT_UINT32, 0, "Identifiers", DT_OPTIONAL}, 225 ACPI_DMT_TERMINATOR 226 }; 227 228 /* 0x01: Named Component */ 229 230 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1[] = 231 { 232 {ACPI_DMT_UINT32, ACPI_IORT1_OFFSET (NodeFlags), "Node Flags", 0}, 233 {ACPI_DMT_IORTMEM, ACPI_IORT1_OFFSET (MemoryProperties), "Memory Properties", 0}, 234 {ACPI_DMT_UINT8, ACPI_IORT1_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 235 {ACPI_DMT_STRING, ACPI_IORT1_OFFSET (DeviceName[0]), "Device Name", 0}, 236 ACPI_DMT_TERMINATOR 237 }; 238 239 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1a[] = 240 { 241 {ACPI_DMT_RAW_BUFFER, 0, "Padding", DT_OPTIONAL}, 242 ACPI_DMT_TERMINATOR 243 }; 244 245 /* 0x02: PCI Root Complex */ 246 247 ACPI_DMTABLE_INFO AcpiDmTableInfoIort2[] = 248 { 249 {ACPI_DMT_IORTMEM, ACPI_IORT2_OFFSET (MemoryProperties), "Memory Properties", 0}, 250 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (AtsAttribute), "ATS Attribute", 0}, 251 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (PciSegmentNumber), "PCI Segment Number", 0}, 252 {ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 253 {ACPI_DMT_UINT16, ACPI_IORT2_OFFSET (PasidCapabilities), "PASID Capabilities", 0}, 254 {ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (Reserved[0]), "Reserved", 0}, 255 ACPI_DMT_TERMINATOR 256 }; 257 258 /* 0x03: SMMUv1/2 */ 259 260 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3[] = 261 { 262 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (BaseAddress), "Base Address", 0}, 263 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (Span), "Span", 0}, 264 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Model), "Model", 0}, 265 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Flags), "Flags (decoded below)", 0}, 266 {ACPI_DMT_FLAG0, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "DVM Supported", 0}, 267 {ACPI_DMT_FLAG1, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "Coherent Walk", 0}, 268 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (GlobalInterruptOffset), "Global Interrupt Offset", 0}, 269 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptCount), "Context Interrupt Count", 0}, 270 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptOffset), "Context Interrupt Offset", 0}, 271 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptCount), "PMU Interrupt Count", 0}, 272 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptOffset), "PMU Interrupt Offset", 0}, 273 ACPI_DMT_TERMINATOR 274 }; 275 276 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3a[] = 277 { 278 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrpt), "NSgIrpt", 0}, 279 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrptFlags), "NSgIrpt Flags (decoded below)", 0}, 280 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgIrptFlags, 0), "Edge Triggered", 0}, 281 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrpt), "NSgCfgIrpt", 0}, 282 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrptFlags), "NSgCfgIrpt Flags (decoded below)", 0}, 283 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgCfgIrptFlags, 0), "Edge Triggered", 0}, 284 ACPI_DMT_TERMINATOR 285 }; 286 287 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3b[] = 288 { 289 {ACPI_DMT_UINT64, 0, "Context Interrupt", DT_OPTIONAL}, 290 ACPI_DMT_TERMINATOR 291 }; 292 293 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3c[] = 294 { 295 {ACPI_DMT_UINT64, 0, "PMU Interrupt", DT_OPTIONAL}, 296 ACPI_DMT_TERMINATOR 297 }; 298 299 /* 0x04: SMMUv3 */ 300 301 ACPI_DMTABLE_INFO AcpiDmTableInfoIort4[] = 302 { 303 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (BaseAddress), "Base Address", 0}, 304 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Flags), "Flags (decoded below)", 0}, 305 {ACPI_DMT_FLAG0, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "COHACC Override", 0}, 306 {ACPI_DMT_FLAG1, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "HTTU Override", 0}, 307 {ACPI_DMT_FLAG3, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "Proximity Domain Valid", 0}, 308 {ACPI_DMT_FLAG4, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "DeviceID Valid", 0}, 309 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Reserved), "Reserved", 0}, 310 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (VatosAddress), "VATOS Address", 0}, 311 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Model), "Model", 0}, 312 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (EventGsiv), "Event GSIV", 0}, 313 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (PriGsiv), "PRI GSIV", 0}, 314 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (GerrGsiv), "GERR GSIV", 0}, 315 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (SyncGsiv), "Sync GSIV", 0}, 316 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Pxm), "Proximity Domain", 0}, 317 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (IdMappingIndex), "Device ID Mapping Index", 0}, 318 ACPI_DMT_TERMINATOR 319 }; 320 321 /* 0x05: PMCG */ 322 323 ACPI_DMTABLE_INFO AcpiDmTableInfoIort5[] = 324 { 325 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page0BaseAddress), "Page 0 Base Address", 0}, 326 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (OverflowGsiv), "Overflow Interrupt GSIV", 0}, 327 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (NodeReference), "Node Reference", 0}, 328 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page1BaseAddress), "Page 1 Base Address", 0}, 329 ACPI_DMT_TERMINATOR 330 }; 331 332 333 /* 0x06: RMR */ 334 335 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6[] = 336 { 337 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (Flags), "Flags (decoded below)", 0}, 338 {ACPI_DMT_FLAG0, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Remapping Permitted", 0}, 339 {ACPI_DMT_FLAG1, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Privileged", 0}, 340 {ACPI_DMT_FLAGS8_2, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Attributes", 0}, 341 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrCount), "Number of RMR Descriptors", 0}, 342 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrOffset), "RMR Descriptor Offset", 0}, 343 ACPI_DMT_TERMINATOR 344 }; 345 346 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6a[] = 347 { 348 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (BaseAddress), "Base Address of RMR", DT_OPTIONAL}, 349 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (Length), "Length of RMR", 0}, 350 {ACPI_DMT_UINT32, ACPI_IORT6A_OFFSET (Reserved), "Reserved", 0}, 351 ACPI_DMT_TERMINATOR 352 }; 353 354 /* 0x07: IWB */ 355 356 ACPI_DMTABLE_INFO AcpiDmTableInfoIort7[] = 357 { 358 {ACPI_DMT_UINT64, ACPI_IORT7_OFFSET (BaseAddress), "Config Frame base", 0}, 359 {ACPI_DMT_UINT16, ACPI_IORT7_OFFSET (IwbIndex), "IWB Index", 0}, 360 {ACPI_DMT_STRING, ACPI_IORT7_OFFSET (DeviceName[0]), "IWB Device Name", 0}, 361 ACPI_DMT_TERMINATOR 362 }; 363 364 365 /******************************************************************************* 366 * 367 * IOVT - I/O Virtualization Table 368 * 369 ******************************************************************************/ 370 371 ACPI_DMTABLE_INFO AcpiDmTableInfoIovt[] = 372 { 373 {ACPI_DMT_UINT16, ACPI_IOVT_OFFSET (IommuCount), "IOMMU Count", 0}, 374 {ACPI_DMT_UINT16, ACPI_IOVT_OFFSET (IommuOffset), "IOMMU Offset", 0}, 375 {ACPI_DMT_UINT64, ACPI_IOVT_OFFSET (Reserved), "Reserved", 0}, 376 ACPI_DMT_TERMINATOR 377 }; 378 379 /* IOVT Subtables */ 380 381 ACPI_DMTABLE_INFO AcpiDmTableInfoIovt0[] = 382 { 383 {ACPI_DMT_IOVT, ACPI_IOVTH_OFFSET (Type), "Subtable Type", 0}, 384 {ACPI_DMT_UINT16, ACPI_IOVTH_OFFSET (Length), "Length", DT_LENGTH}, 385 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 386 {ACPI_DMT_FLAG0, ACPI_IOVT0_FLAG_OFFSET (Flags,0), "PCI Device", 0}, 387 {ACPI_DMT_FLAG1, ACPI_IOVT0_FLAG_OFFSET (Flags,0), "Proximity Domain Valid", 0}, 388 {ACPI_DMT_FLAG2, ACPI_IOVT0_FLAG_OFFSET (Flags,0), "Manageable Devices Range", 0}, 389 {ACPI_DMT_FLAG3, ACPI_IOVT0_FLAG_OFFSET (Flags,0), "HW Capability Supported", 0}, 390 {ACPI_DMT_FLAG4, ACPI_IOVT0_FLAG_OFFSET (Flags,0), "MSI Interrupt Address", 0}, 391 {ACPI_DMT_UINT16, ACPI_IOVT0_OFFSET (Segment), "PCI Segment Number", 0}, 392 {ACPI_DMT_UINT16, ACPI_IOVT0_OFFSET (PhyWidth), "Physical Address Width", 0}, 393 {ACPI_DMT_UINT16, ACPI_IOVT0_OFFSET (VirtWidth), "Virtual Address Width", 0}, 394 {ACPI_DMT_UINT16, ACPI_IOVT0_OFFSET (MaxPageLevel), "Max Page Level", 0}, 395 {ACPI_DMT_UINT64, ACPI_IOVT0_OFFSET (PageSize), "Page Size Supported", 0}, 396 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (DeviceId), "IOMMU DeviceID", 0}, 397 {ACPI_DMT_UINT64, ACPI_IOVT0_OFFSET (BaseAddress), "IOMMU Base Address", 0}, 398 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (AddressSpaceSize), "IOMMU Register Size", 0}, 399 {ACPI_DMT_UINT8, ACPI_IOVT0_OFFSET (InterruptType), "Interrupt Type", 0}, 400 {ACPI_DMT_UINT24, ACPI_IOVT0_OFFSET (Reserved), "Reserved", 0}, 401 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (GsiNumber), "Global System Interrupt", 0}, 402 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (ProximityDomain), "Proximity Domain", 0}, 403 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (MaxDeviceNum), "Max Device Num", 0}, 404 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (DeviceEntryNum), "Number of Device Entries", 0}, 405 {ACPI_DMT_UINT32, ACPI_IOVT0_OFFSET (DeviceEntryOffset), "Offset of Device Entries", 0}, 406 ACPI_DMT_TERMINATOR 407 }; 408 409 /* device entry */ 410 411 ACPI_DMTABLE_INFO AcpiDmTableInfoIovtdev[] = 412 { 413 {ACPI_DMT_IOVTDEV, ACPI_IOVTDEV_OFFSET (Type), "Subtable Type", 0}, 414 {ACPI_DMT_UINT8, ACPI_IOVTDEV_OFFSET (Length), "Length", 0}, 415 {ACPI_DMT_UINT8, ACPI_IOVTDEV_OFFSET (Flags), "Flags", 0}, 416 {ACPI_DMT_UINT24, ACPI_IOVTDEV_OFFSET (Reserved), "Reserved", 0}, 417 {ACPI_DMT_UINT16, ACPI_IOVTDEV_OFFSET (DeviceId), "DeviceID", 0}, 418 ACPI_DMT_TERMINATOR 419 }; 420 421 422 /******************************************************************************* 423 * 424 * IVRS - I/O Virtualization Reporting Structure 425 * 426 ******************************************************************************/ 427 428 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs[] = 429 { 430 {ACPI_DMT_UINT32, ACPI_IVRS_OFFSET (Info), "Virtualization Info", 0}, 431 {ACPI_DMT_UINT64, ACPI_IVRS_OFFSET (Reserved), "Reserved", 0}, 432 ACPI_DMT_TERMINATOR 433 }; 434 435 /* IVRS subtables */ 436 437 /* 0x10: I/O Virtualization Hardware Definition (IVHD) Block */ 438 439 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware1[] = 440 { 441 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 442 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 443 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 444 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 445 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 446 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 447 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 448 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 449 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 450 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 451 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 452 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 453 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (CapabilityOffset), "Capability Offset", 0}, 454 {ACPI_DMT_UINT64, ACPI_IVRS0_OFFSET (BaseAddress), "Base Address", 0}, 455 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 456 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (Info), "Virtualization Info", 0}, 457 {ACPI_DMT_UINT32, ACPI_IVRS0_OFFSET (FeatureReporting), "Feature Reporting", 0}, 458 ACPI_DMT_TERMINATOR 459 }; 460 461 /* 0x11, 0x40: I/O Virtualization Hardware Definition (IVHD) Block */ 462 463 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware23[] = 464 { 465 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 466 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 467 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 468 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 469 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 470 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 471 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 472 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 473 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 474 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 475 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.Length), "Length", DT_LENGTH}, 476 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.DeviceId), "DeviceId", 0}, 477 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (CapabilityOffset), "Capability Offset", 0}, 478 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (BaseAddress), "Base Address", 0}, 479 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 480 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Info), "Virtualization Info", 0}, 481 {ACPI_DMT_UINT32, ACPI_IVRS01_OFFSET (Attributes), "Attributes", 0}, 482 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (EfrRegisterImage), "EFR Image", 0}, 483 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (Reserved), "Reserved", 0}, 484 ACPI_DMT_TERMINATOR 485 }; 486 487 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition (IVMD) Device Entry Block */ 488 489 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsMemory[] = 490 { 491 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 492 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 493 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Unity", 0}, 494 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Readable", 0}, 495 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Writeable", 0}, 496 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Exclusion Range", 0}, 497 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 498 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 499 {ACPI_DMT_UINT16, ACPI_IVRS1_OFFSET (AuxData), "Auxiliary Data", 0}, 500 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (Reserved), "Reserved", 0}, 501 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (StartAddress), "Start Address", 0}, 502 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (MemoryLength), "Memory Length", 0}, 503 ACPI_DMT_TERMINATOR 504 }; 505 506 /* Device entry header for IVHD block */ 507 508 #define ACPI_DMT_IVRS_DE_HEADER \ 509 {ACPI_DMT_IVRS_DE, ACPI_IVRSD_OFFSET (Type), "Subtable Type", 0}, \ 510 {ACPI_DMT_UINT16, ACPI_IVRSD_OFFSET (Id), "Device ID", 0}, \ 511 {ACPI_DMT_UINT8, ACPI_IVRSD_OFFSET (DataSetting), "Data Setting (decoded below)", 0}, \ 512 {ACPI_DMT_FLAG0, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "INITPass", 0}, \ 513 {ACPI_DMT_FLAG1, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "EIntPass", 0}, \ 514 {ACPI_DMT_FLAG2, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "NMIPass", 0}, \ 515 {ACPI_DMT_FLAG3, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "Reserved", 0}, \ 516 {ACPI_DMT_FLAGS4, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "System MGMT", 0}, \ 517 {ACPI_DMT_FLAG6, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT0 Pass", 0}, \ 518 {ACPI_DMT_FLAG7, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT1 Pass", 0} 519 520 /* 4-byte device entry (Types 1,2,3,4) */ 521 522 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs4[] = 523 { 524 ACPI_DMT_IVRS_DE_HEADER, 525 ACPI_DMT_TERMINATOR 526 }; 527 528 /* 8-byte device entry (Type Alias Select, Alias Start of Range) */ 529 530 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8a[] = 531 { 532 ACPI_DMT_IVRS_DE_HEADER, 533 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved1), "Reserved", 0}, 534 {ACPI_DMT_UINT16, ACPI_IVRS8A_OFFSET (UsedId), "Source Used Device ID", 0}, 535 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved2), "Reserved", 0}, 536 ACPI_DMT_TERMINATOR 537 }; 538 539 /* 8-byte device entry (Type Extended Select, Extended Start of Range) */ 540 541 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8b[] = 542 { 543 ACPI_DMT_IVRS_DE_HEADER, 544 {ACPI_DMT_UINT32, ACPI_IVRS8B_OFFSET (ExtendedData), "Extended Data", 0}, 545 ACPI_DMT_TERMINATOR 546 }; 547 548 /* 8-byte device entry (Type Special Device) */ 549 550 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8c[] = 551 { 552 ACPI_DMT_IVRS_DE_HEADER, 553 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Handle), "Handle", 0}, 554 {ACPI_DMT_UINT16, ACPI_IVRS8C_OFFSET (UsedId), "Source Used Device ID", 0}, 555 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Variety), "Variety", 0}, 556 ACPI_DMT_TERMINATOR 557 }; 558 559 /* Variable-length Device Entry Type 0xF0 */ 560 561 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHid[] = 562 { 563 ACPI_DMT_IVRS_DE_HEADER, 564 ACPI_DMT_TERMINATOR 565 }; 566 567 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidString[] = 568 { 569 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 570 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 571 {ACPI_DMT_IVRS_UNTERMINATED_STRING, 2, "UID", DT_OPTIONAL}, 572 ACPI_DMT_TERMINATOR 573 }; 574 575 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidInteger[] = 576 { 577 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 578 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 579 {ACPI_DMT_UINT64, 2, "UID", DT_OPTIONAL}, 580 ACPI_DMT_TERMINATOR 581 }; 582 583 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidString[] = 584 { 585 {ACPI_DMT_NAME8, 0, "ACPI HID", 0}, 586 ACPI_DMT_TERMINATOR 587 }; 588 589 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidInteger[] = 590 { 591 {ACPI_DMT_UINT64, 0, "ACPI HID", 0}, 592 ACPI_DMT_TERMINATOR 593 }; 594 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidString[] = 595 { 596 {ACPI_DMT_NAME8, 0, "ACPI CID", 0}, 597 ACPI_DMT_TERMINATOR 598 }; 599 600 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidInteger[] = 601 { 602 {ACPI_DMT_UINT64, 0, "ACPI CID", 0}, 603 ACPI_DMT_TERMINATOR 604 }; 605 606 607 /******************************************************************************* 608 * 609 * LPIT - Low Power Idle Table 610 * 611 ******************************************************************************/ 612 613 /* Main table consists only of the standard ACPI table header */ 614 615 /* Common Subtable header (one per Subtable) */ 616 617 ACPI_DMTABLE_INFO AcpiDmTableInfoLpitHdr[] = 618 { 619 {ACPI_DMT_LPIT, ACPI_LPITH_OFFSET (Type), "Subtable Type", 0}, 620 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Length), "Length", DT_LENGTH}, 621 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (UniqueId), "Unique ID", 0}, 622 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (Reserved), "Reserved", 0}, 623 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 624 {ACPI_DMT_FLAG0, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "State Disabled", 0}, 625 {ACPI_DMT_FLAG1, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "No Counter", 0}, 626 ACPI_DMT_TERMINATOR 627 }; 628 629 /* LPIT Subtables */ 630 631 /* 0: Native C-state */ 632 633 ACPI_DMTABLE_INFO AcpiDmTableInfoLpit0[] = 634 { 635 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (EntryTrigger), "Entry Trigger", 0}, 636 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Residency), "Residency", 0}, 637 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Latency), "Latency", 0}, 638 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (ResidencyCounter), "Residency Counter", 0}, 639 {ACPI_DMT_UINT64, ACPI_LPIT0_OFFSET (CounterFrequency), "Counter Frequency", 0}, 640 ACPI_DMT_TERMINATOR 641 }; 642 /******************************************************************************* 643 * 644 * MADT - Multiple APIC Description Table and subtables 645 * 646 ******************************************************************************/ 647 648 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt[] = 649 { 650 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Address), "Local Apic Address", 0}, 651 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 652 {ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility", 0}, 653 ACPI_DMT_TERMINATOR 654 }; 655 656 /* Common Subtable header (one per Subtable) */ 657 658 ACPI_DMTABLE_INFO AcpiDmTableInfoMadtHdr[] = 659 { 660 {ACPI_DMT_MADT, ACPI_MADTH_OFFSET (Type), "Subtable Type", 0}, 661 {ACPI_DMT_UINT8, ACPI_MADTH_OFFSET (Length), "Length", DT_LENGTH}, 662 ACPI_DMT_TERMINATOR 663 }; 664 665 /* MADT Subtables */ 666 667 /* 0: processor APIC */ 668 669 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt0[] = 670 { 671 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (ProcessorId), "Processor ID", 0}, 672 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (Id), "Local Apic ID", 0}, 673 {ACPI_DMT_UINT32, ACPI_MADT0_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 674 {ACPI_DMT_FLAG0, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 675 {ACPI_DMT_FLAG1, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Runtime Online Capable", 0}, 676 ACPI_DMT_TERMINATOR 677 }; 678 679 /* 1: IO APIC */ 680 681 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt1[] = 682 { 683 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Id), "I/O Apic ID", 0}, 684 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Reserved), "Reserved", 0}, 685 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (Address), "Address", 0}, 686 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (GlobalIrqBase), "Interrupt", 0}, 687 ACPI_DMT_TERMINATOR 688 }; 689 690 /* 2: Interrupt Override */ 691 692 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt2[] = 693 { 694 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (Bus), "Bus", 0}, 695 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (SourceIrq), "Source", 0}, 696 {ACPI_DMT_UINT32, ACPI_MADT2_OFFSET (GlobalIrq), "Interrupt", 0}, 697 {ACPI_DMT_UINT16, ACPI_MADT2_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 698 {ACPI_DMT_FLAGS0, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 699 {ACPI_DMT_FLAGS2, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 700 ACPI_DMT_TERMINATOR 701 }; 702 703 /* 3: NMI Sources */ 704 705 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt3[] = 706 { 707 {ACPI_DMT_UINT16, ACPI_MADT3_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 708 {ACPI_DMT_FLAGS0, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 709 {ACPI_DMT_FLAGS2, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 710 {ACPI_DMT_UINT32, ACPI_MADT3_OFFSET (GlobalIrq), "Interrupt", 0}, 711 ACPI_DMT_TERMINATOR 712 }; 713 714 /* 4: Local APIC NMI */ 715 716 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt4[] = 717 { 718 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (ProcessorId), "Processor ID", 0}, 719 {ACPI_DMT_UINT16, ACPI_MADT4_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 720 {ACPI_DMT_FLAGS0, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 721 {ACPI_DMT_FLAGS2, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 722 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (Lint), "Interrupt Input LINT", 0}, 723 ACPI_DMT_TERMINATOR 724 }; 725 726 /* 5: Address Override */ 727 728 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt5[] = 729 { 730 {ACPI_DMT_UINT16, ACPI_MADT5_OFFSET (Reserved), "Reserved", 0}, 731 {ACPI_DMT_UINT64, ACPI_MADT5_OFFSET (Address), "APIC Address", 0}, 732 ACPI_DMT_TERMINATOR 733 }; 734 735 /* 6: I/O Sapic */ 736 737 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt6[] = 738 { 739 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Id), "I/O Sapic ID", 0}, 740 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Reserved), "Reserved", 0}, 741 {ACPI_DMT_UINT32, ACPI_MADT6_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 742 {ACPI_DMT_UINT64, ACPI_MADT6_OFFSET (Address), "Address", 0}, 743 ACPI_DMT_TERMINATOR 744 }; 745 746 /* 7: Local Sapic */ 747 748 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt7[] = 749 { 750 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (ProcessorId), "Processor ID", 0}, 751 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Id), "Local Sapic ID", 0}, 752 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Eid), "Local Sapic EID", 0}, 753 {ACPI_DMT_UINT24, ACPI_MADT7_OFFSET (Reserved[0]), "Reserved", 0}, 754 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 755 {ACPI_DMT_FLAG0, ACPI_MADT7_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 756 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (Uid), "Processor UID", 0}, 757 {ACPI_DMT_STRING, ACPI_MADT7_OFFSET (UidString[0]), "Processor UID String", 0}, 758 ACPI_DMT_TERMINATOR 759 }; 760 761 /* 8: Platform Interrupt Source */ 762 763 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt8[] = 764 { 765 {ACPI_DMT_UINT16, ACPI_MADT8_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 766 {ACPI_DMT_FLAGS0, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 767 {ACPI_DMT_FLAGS2, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 768 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Type), "InterruptType", 0}, 769 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Id), "Processor ID", 0}, 770 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Eid), "Processor EID", 0}, 771 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (IoSapicVector), "I/O Sapic Vector", 0}, 772 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (GlobalIrq), "Interrupt", 0}, 773 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 774 {ACPI_DMT_FLAG0, ACPI_MADT8_OFFSET (Flags), "CPEI Override", 0}, 775 ACPI_DMT_TERMINATOR 776 }; 777 778 /* 9: Processor Local X2_APIC (ACPI 4.0) */ 779 780 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt9[] = 781 { 782 {ACPI_DMT_UINT16, ACPI_MADT9_OFFSET (Reserved), "Reserved", 0}, 783 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LocalApicId), "Processor x2Apic ID", 0}, 784 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 785 {ACPI_DMT_FLAG0, ACPI_MADT9_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 786 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (Uid), "Processor UID", 0}, 787 ACPI_DMT_TERMINATOR 788 }; 789 790 /* 10: Local X2_APIC NMI (ACPI 4.0) */ 791 792 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt10[] = 793 { 794 {ACPI_DMT_UINT16, ACPI_MADT10_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 795 {ACPI_DMT_FLAGS0, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 796 {ACPI_DMT_FLAGS2, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 797 {ACPI_DMT_UINT32, ACPI_MADT10_OFFSET (Uid), "Processor UID", 0}, 798 {ACPI_DMT_UINT8, ACPI_MADT10_OFFSET (Lint), "Interrupt Input LINT", 0}, 799 {ACPI_DMT_UINT24, ACPI_MADT10_OFFSET (Reserved[0]), "Reserved", 0}, 800 ACPI_DMT_TERMINATOR 801 }; 802 803 /* 11: Generic Interrupt Controller (ACPI 5.0) */ 804 805 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11[] = 806 { 807 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 808 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 809 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 810 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 811 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 812 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 813 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 814 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 815 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 816 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 817 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 818 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 819 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 820 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 821 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 822 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 823 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 824 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 825 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 826 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0}, 827 ACPI_DMT_TERMINATOR 828 }; 829 830 /* 11: Generic Interrupt Controller (ACPI 5.0) - MADT revision 6 */ 831 832 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11a[] = 833 { 834 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 835 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 836 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 837 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 838 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 839 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 840 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 841 {ACPI_DMT_FLAG3, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Online Capable", 0}, 842 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 843 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 844 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 845 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 846 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 847 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 848 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 849 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 850 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 851 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 852 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 853 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 854 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0}, 855 ACPI_DMT_TERMINATOR 856 }; 857 858 /* 11: Generic Interrupt Controller (ACPI 5.0) - MADT revision 7 */ 859 860 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11b[] = 861 { 862 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 863 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 864 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 865 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 866 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 867 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 868 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 869 {ACPI_DMT_FLAG3, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Online Capable", 0}, 870 {ACPI_DMT_FLAG4, ACPI_MADT11_FLAG_OFFSET (Flags,0), "GICR non-coherent", 0}, 871 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 872 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 873 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 874 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 875 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 876 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 877 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 878 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 879 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 880 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 881 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 882 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 883 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0}, 884 ACPI_DMT_TERMINATOR 885 }; 886 887 /* 12: Generic Interrupt Distributor (ACPI 5.0) */ 888 889 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt12[] = 890 { 891 {ACPI_DMT_UINT16, ACPI_MADT12_OFFSET (Reserved), "Reserved", 0}, 892 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GicId), "Local GIC Hardware ID", 0}, 893 {ACPI_DMT_UINT64, ACPI_MADT12_OFFSET (BaseAddress), "Base Address", 0}, 894 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 895 {ACPI_DMT_UINT8, ACPI_MADT12_OFFSET (Version), "Version", 0}, 896 {ACPI_DMT_UINT24, ACPI_MADT12_OFFSET (Reserved2[0]), "Reserved", 0}, 897 ACPI_DMT_TERMINATOR 898 }; 899 900 /* 13: Generic MSI Frame (ACPI 5.1) */ 901 902 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt13[] = 903 { 904 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (Reserved), "Reserved", 0}, 905 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (MsiFrameId), "MSI Frame ID", 0}, 906 {ACPI_DMT_UINT64, ACPI_MADT13_OFFSET (BaseAddress), "Base Address", 0}, 907 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 908 {ACPI_DMT_FLAG0, ACPI_MADT13_FLAG_OFFSET (Flags,0), "Select SPI", 0}, 909 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiCount), "SPI Count", 0}, 910 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiBase), "SPI Base", 0}, 911 ACPI_DMT_TERMINATOR 912 }; 913 914 /* 14: Generic Redistributor (ACPI 5.1) */ 915 916 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14[] = 917 { 918 {ACPI_DMT_UINT16, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0}, 919 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0}, 920 {ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0}, 921 ACPI_DMT_TERMINATOR 922 }; 923 924 /* 14: Generic Redistributor (ACPI 5.1) */ 925 926 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14a[] = 927 { 928 {ACPI_DMT_UINT8, ACPI_MADT14_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 929 {ACPI_DMT_FLAG0, ACPI_MADT14_FLAG_OFFSET (Flags,0), "GICR non-coherent", 0}, 930 {ACPI_DMT_UINT8, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0}, 931 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0}, 932 {ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0}, 933 ACPI_DMT_TERMINATOR 934 }; 935 936 /* 15: Generic Translator (ACPI 6.0) */ 937 938 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15[] = 939 { 940 {ACPI_DMT_UINT16, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0}, 941 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0}, 942 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0}, 943 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0}, 944 ACPI_DMT_TERMINATOR 945 }; 946 947 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15a[] = 948 { 949 {ACPI_DMT_UINT8, ACPI_MADT15_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 950 {ACPI_DMT_FLAG0, ACPI_MADT15_FLAG_OFFSET (Flags,0), "GIC ITS non-coherent", 0}, 951 {ACPI_DMT_UINT8, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0}, 952 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0}, 953 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0}, 954 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0}, 955 ACPI_DMT_TERMINATOR 956 }; 957 958 /* 16: Multiprocessor wakeup structure (ACPI 6.6) */ 959 960 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt16[] = 961 { 962 {ACPI_DMT_UINT16, ACPI_MADT16_OFFSET (MailboxVersion), "Mailbox Version", 0}, 963 {ACPI_DMT_UINT32, ACPI_MADT16_OFFSET (Reserved), "Reserved", 0}, 964 {ACPI_DMT_UINT64, ACPI_MADT16_OFFSET (BaseAddress), "Mailbox Address", 0}, 965 {ACPI_DMT_UINT64, ACPI_MADT16_OFFSET (ResetVector), "ResetVector", 0}, 966 ACPI_DMT_TERMINATOR 967 }; 968 969 /* 17: core interrupt controller */ 970 971 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt17[] = 972 { 973 {ACPI_DMT_UINT8, ACPI_MADT17_OFFSET (Version), "Version", 0}, 974 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (ProcessorId), "ProcessorId", 0}, 975 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (CoreId), "CoreId", 0}, 976 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (Flags), "Flags", 0}, 977 ACPI_DMT_TERMINATOR 978 }; 979 980 /* 18: Legacy I/O interrupt controller */ 981 982 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt18[] = 983 { 984 {ACPI_DMT_UINT8, ACPI_MADT18_OFFSET (Version), "Version", 0}, 985 {ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (Address), "Address", 0}, 986 {ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Size), "Size", 0}, 987 {ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Cascade), "Cascade", 0}, 988 {ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (CascadeMap), "CascadeMap", 0}, 989 ACPI_DMT_TERMINATOR 990 }; 991 992 /* 19: HT interrupt controller */ 993 994 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt19[] = 995 { 996 {ACPI_DMT_UINT8, ACPI_MADT19_OFFSET (Version), "Version", 0}, 997 {ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Address), "Address", 0}, 998 {ACPI_DMT_UINT16, ACPI_MADT19_OFFSET (Size), "Size", 0}, 999 {ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Cascade), "Cascade", 0}, 1000 ACPI_DMT_TERMINATOR 1001 }; 1002 1003 /* 20: Extend I/O interrupt controller */ 1004 1005 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt20[] = 1006 { 1007 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Version), "Version", 0}, 1008 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Cascade), "Cascade", 0}, 1009 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Node), "Node", 0}, 1010 {ACPI_DMT_UINT64, ACPI_MADT20_OFFSET (NodeMap), "NodeMap", 0}, 1011 ACPI_DMT_TERMINATOR 1012 }; 1013 1014 /* 21: MSI controller */ 1015 1016 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt21[] = 1017 { 1018 {ACPI_DMT_UINT8, ACPI_MADT21_OFFSET (Version), "Version", 0}, 1019 {ACPI_DMT_UINT64, ACPI_MADT21_OFFSET (MsgAddress), "MsgAddress", 0}, 1020 {ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Start), "Start", 0}, 1021 {ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Count), "Count", 0}, 1022 ACPI_DMT_TERMINATOR 1023 }; 1024 1025 /* 22: BIO interrupt controller */ 1026 1027 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt22[] = 1028 { 1029 {ACPI_DMT_UINT8, ACPI_MADT22_OFFSET (Version), "Version", 0}, 1030 {ACPI_DMT_UINT64, ACPI_MADT22_OFFSET (Address), "Address", 0}, 1031 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Size), "Size", 0}, 1032 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Id), "Id", 0}, 1033 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (GsiBase), "GsiBase", 0}, 1034 ACPI_DMT_TERMINATOR 1035 }; 1036 1037 /* 23: LPC interrupt controller */ 1038 1039 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt23[] = 1040 { 1041 {ACPI_DMT_UINT8, ACPI_MADT23_OFFSET (Version), "Version", 0}, 1042 {ACPI_DMT_UINT64, ACPI_MADT23_OFFSET (Address), "Address", 0}, 1043 {ACPI_DMT_UINT16, ACPI_MADT23_OFFSET (Size), "Size", 0}, 1044 {ACPI_DMT_UINT8, ACPI_MADT23_OFFSET (Cascade), "Cascade", 0}, 1045 ACPI_DMT_TERMINATOR 1046 }; 1047 1048 /* 24: RINTC interrupt controller */ 1049 1050 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt24[] = 1051 { 1052 {ACPI_DMT_UINT8, ACPI_MADT24_OFFSET (Version), "Version", 0}, 1053 {ACPI_DMT_UINT8, ACPI_MADT24_OFFSET (Reserved), "Reserved", 0}, 1054 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (Flags), "Flags", 0}, 1055 {ACPI_DMT_UINT64, ACPI_MADT24_OFFSET (HartId), "HartId", 0}, 1056 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (Uid), "Uid", 0}, 1057 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (ExtIntcId), "ExtIntcId", 0}, 1058 {ACPI_DMT_UINT64, ACPI_MADT24_OFFSET (ImsicAddr), "ImsicAddr", 0}, 1059 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (ImsicSize), "ImsicSize", 0}, 1060 ACPI_DMT_TERMINATOR 1061 }; 1062 1063 /* 25: RISC-V IMSIC interrupt controller */ 1064 1065 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt25[] = 1066 { 1067 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (Version), "Version", 0}, 1068 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (Reserved), "Reserved", 0}, 1069 {ACPI_DMT_UINT32, ACPI_MADT25_OFFSET (Flags), "Flags", 0}, 1070 {ACPI_DMT_UINT16, ACPI_MADT25_OFFSET (NumIds), "NumIds", 0}, 1071 {ACPI_DMT_UINT16, ACPI_MADT25_OFFSET (NumGuestIds), "NumGuestIds", 0}, 1072 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GuestIndexBits), "GuestIndexBits", 0}, 1073 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (HartIndexBits), "HartIndexBits", 0}, 1074 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GroupIndexBits), "GroupIndexBits", 0}, 1075 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GroupIndexShift), "GroupIndexShift", 0}, 1076 ACPI_DMT_TERMINATOR 1077 }; 1078 1079 /* 26: RISC-V APLIC interrupt controller */ 1080 1081 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt26[] = 1082 { 1083 {ACPI_DMT_UINT8, ACPI_MADT26_OFFSET (Version), "Version", 0}, 1084 {ACPI_DMT_UINT8, ACPI_MADT26_OFFSET (Id), "Id", 0}, 1085 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (Flags), "Flags", 0}, 1086 {ACPI_DMT_UINT64, ACPI_MADT26_OFFSET (HwId), "HwId", 0}, 1087 {ACPI_DMT_UINT16, ACPI_MADT26_OFFSET (NumIdcs), "NumIdcs", 0}, 1088 {ACPI_DMT_UINT16, ACPI_MADT26_OFFSET (NumSources), "NumSources", 0}, 1089 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (GsiBase), "GsiBase", 0}, 1090 {ACPI_DMT_UINT64, ACPI_MADT26_OFFSET (BaseAddr), "BaseAddr", 0}, 1091 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (Size), "Size", 0}, 1092 ACPI_DMT_TERMINATOR 1093 }; 1094 1095 /* 27: RISC-V PLIC interrupt controller */ 1096 1097 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt27[] = 1098 { 1099 {ACPI_DMT_UINT8, ACPI_MADT27_OFFSET (Version), "Version", 0}, 1100 {ACPI_DMT_UINT8, ACPI_MADT27_OFFSET (Id), "Id", 0}, 1101 {ACPI_DMT_UINT64, ACPI_MADT27_OFFSET (HwId), "HwId", 0}, 1102 {ACPI_DMT_UINT16, ACPI_MADT27_OFFSET (NumIrqs), "NumIrqs", 0}, 1103 {ACPI_DMT_UINT16, ACPI_MADT27_OFFSET (MaxPrio), "MaxPrio", 0}, 1104 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (Flags), "Flags", 0}, 1105 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (Size), "Size", 0}, 1106 {ACPI_DMT_UINT64, ACPI_MADT27_OFFSET (BaseAddr), "BaseAddr", 0}, 1107 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (GsiBase), "GsiBase", 0}, 1108 ACPI_DMT_TERMINATOR 1109 }; 1110 1111 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt28[] = 1112 { 1113 {ACPI_DMT_UINT8, ACPI_MADT28_OFFSET (Version), "Gic version", 0}, 1114 {ACPI_DMT_UINT8, ACPI_MADT28_OFFSET (Reserved), "Reserved", 0}, 1115 {ACPI_DMT_UINT32, ACPI_MADT28_OFFSET (IrsId), "Irs Id", 0}, 1116 {ACPI_DMT_UINT32, ACPI_MADT28_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1117 {ACPI_DMT_FLAG0, ACPI_MADT28_FLAG_OFFSET (Flags,0), "GICV5 IRS non-coherent", 0}, 1118 {ACPI_DMT_UINT32, ACPI_MADT28_OFFSET (Reserved2), "Reserved", 0}, 1119 {ACPI_DMT_UINT64, ACPI_MADT28_OFFSET (ConfigBaseAddress), "Irs Config Frame Physical Base Address", 0}, 1120 {ACPI_DMT_UINT64, ACPI_MADT28_OFFSET (SetlpiBaseAddress), "Irs Setlpi Frame Physical Base Address", 0}, 1121 ACPI_DMT_TERMINATOR 1122 }; 1123 1124 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt29[] = 1125 { 1126 {ACPI_DMT_UINT8, ACPI_MADT29_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1127 {ACPI_DMT_FLAG0, ACPI_MADT29_FLAG_OFFSET (Flags,0), "GICV5 ITS non-coherent", 0}, 1128 {ACPI_DMT_UINT8, ACPI_MADT29_OFFSET (Reserved), "Reserved", 0}, 1129 {ACPI_DMT_UINT32, ACPI_MADT29_OFFSET (TranslatorId), "Gic Its Id", 0}, 1130 {ACPI_DMT_UINT64, ACPI_MADT29_OFFSET (BaseAddress), "Physical Base Address", 0}, 1131 ACPI_DMT_TERMINATOR 1132 }; 1133 1134 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt30[] = 1135 { 1136 {ACPI_DMT_UINT16, ACPI_MADT30_OFFSET (Reserved), "Reserved", 0}, 1137 {ACPI_DMT_UINT32, ACPI_MADT30_OFFSET (LinkedTranslatorId), "Linked Its Id", 0}, 1138 {ACPI_DMT_UINT32, ACPI_MADT30_OFFSET (TranslateFrameId), "Its Transalte Id", 0}, 1139 {ACPI_DMT_UINT32, ACPI_MADT30_OFFSET (Reserved2), "Reserved", 0}, 1140 {ACPI_DMT_UINT64, ACPI_MADT30_OFFSET (BaseAddress), "Its Translate Frame Physical Base Address", 0}, 1141 ACPI_DMT_TERMINATOR 1142 }; 1143 1144 /* 128: OEM data structure */ 1145 1146 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt128[] = 1147 { 1148 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", 0}, 1149 ACPI_DMT_TERMINATOR 1150 }; 1151 1152 /******************************************************************************* 1153 * 1154 * MCFG - PCI Memory Mapped Configuration table and Subtable 1155 * 1156 ******************************************************************************/ 1157 1158 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg[] = 1159 { 1160 {ACPI_DMT_UINT64, ACPI_MCFG_OFFSET (Reserved[0]), "Reserved", 0}, 1161 ACPI_DMT_TERMINATOR 1162 }; 1163 1164 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg0[] = 1165 { 1166 {ACPI_DMT_UINT64, ACPI_MCFG0_OFFSET (Address), "Base Address", 0}, 1167 {ACPI_DMT_UINT16, ACPI_MCFG0_OFFSET (PciSegment), "Segment Group Number", 0}, 1168 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (StartBusNumber), "Start Bus Number", 0}, 1169 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (EndBusNumber), "End Bus Number", 0}, 1170 {ACPI_DMT_UINT32, ACPI_MCFG0_OFFSET (Reserved), "Reserved", 0}, 1171 ACPI_DMT_TERMINATOR 1172 }; 1173 1174 1175 /******************************************************************************* 1176 * 1177 * MCHI - Management Controller Host Interface table 1178 * 1179 ******************************************************************************/ 1180 1181 ACPI_DMTABLE_INFO AcpiDmTableInfoMchi[] = 1182 { 1183 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterfaceType), "Interface Type", 0}, 1184 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Protocol), "Protocol", 0}, 1185 {ACPI_DMT_UINT64, ACPI_MCHI_OFFSET (ProtocolData), "Protocol Data", 0}, 1186 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterruptType), "Interrupt Type", 0}, 1187 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Gpe), "Gpe", 0}, 1188 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDeviceFlag), "Pci Device Flag", 0}, 1189 {ACPI_DMT_UINT32, ACPI_MCHI_OFFSET (GlobalInterrupt), "Global Interrupt", 0}, 1190 {ACPI_DMT_GAS, ACPI_MCHI_OFFSET (ControlRegister), "Control Register", 0}, 1191 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciSegment), "Pci Segment", 0}, 1192 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciBus), "Pci Bus", 0}, 1193 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDevice), "Pci Device", 0}, 1194 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciFunction), "Pci Function", 0}, 1195 ACPI_DMT_TERMINATOR 1196 }; 1197 1198 /******************************************************************************* 1199 * 1200 * MPAM - Memory System Resource Partitioning and Monitoring Tables 1201 * Arm's DEN0065 MPAM ACPI 2.0. December 2022. 1202 ******************************************************************************/ 1203 1204 /* MPAM subtables */ 1205 1206 /* 0: MPAM Resource Node Structure - A root MSC table. 1207 * Arm's DEN0065 MPAM ACPI 2.0. Table 4: MPAM MSC node body. 1208 */ 1209 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam0[] = 1210 { 1211 {ACPI_DMT_UINT16, ACPI_MPAM0_OFFSET (Length), "Length", 0}, 1212 {ACPI_DMT_UINT8, ACPI_MPAM0_OFFSET (InterfaceType), "Interface type", 0}, 1213 {ACPI_DMT_UINT8, ACPI_MPAM0_OFFSET (Reserved), "Reserved", 0}, 1214 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Identifier), "Identifier", 0}, 1215 {ACPI_DMT_UINT64, ACPI_MPAM0_OFFSET (BaseAddress), "Base address", 0}, 1216 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (MMIOSize), "MMIO size", 0}, 1217 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterrupt), "Overflow interrupt", 0}, 1218 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterruptFlags), "Overflow interrupt flags", 0}, 1219 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Reserved1), "Reserved1", 0}, 1220 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterruptAffinity), "Overflow interrupt affinity", 0}, 1221 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterrupt), "Error interrupt", 0}, 1222 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterruptFlags), "Error interrupt flags", 0}, 1223 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Reserved2), "Reserved2", 0}, 1224 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterruptAffinity), "Error interrupt affinity", 0}, 1225 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (MaxNrdyUsec), "MAX_NRDY_USEC", 0}, 1226 {ACPI_DMT_NAME8, ACPI_MPAM0_OFFSET (HardwareIdLinkedDevice), "Hardware ID of linked device", 0}, 1227 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (InstanceIdLinkedDevice), "Instance ID of linked device", 0}, 1228 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (NumResourceNodes), "Number of resource nodes", 0}, 1229 1230 ACPI_DMT_TERMINATOR 1231 }; 1232 1233 /* 1: MPAM Resource (RIS) Node Structure - A subtable of MSC Nodes. 1234 * Arm's DEN0065 MPAM ACPI 2.0. Table 9: Resource node. 1235 */ 1236 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1[] = 1237 { 1238 {ACPI_DMT_UINT32, ACPI_MPAM1_OFFSET (Identifier), "Identifier", 0}, 1239 {ACPI_DMT_UINT8, ACPI_MPAM1_OFFSET (RISIndex), "RIS Index", 0}, 1240 {ACPI_DMT_UINT16, ACPI_MPAM1_OFFSET (Reserved1), "Reserved1", 0}, 1241 {ACPI_DMT_MPAM_LOCATOR, ACPI_MPAM1_OFFSET (LocatorType), "Locator type", 0}, 1242 ACPI_DMT_TERMINATOR 1243 }; 1244 1245 /* An RIS field part of the RIS subtable */ 1246 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1Deps[] = 1247 { 1248 {ACPI_DMT_UINT32, 0, "Number of functional dependencies", 0}, 1249 ACPI_DMT_TERMINATOR 1250 }; 1251 1252 /* 1A: MPAM Processor cache locator descriptor. A subtable of RIS. 1253 * Arm's DEN0065 MPAM ACPI 2.0. Table 13. 1254 */ 1255 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1A[] = 1256 { 1257 {ACPI_DMT_UINT64, ACPI_MPAM1A_OFFSET (CacheReference), "Cache reference", 0}, 1258 {ACPI_DMT_UINT32, ACPI_MPAM1A_OFFSET (Reserved), "Reserved", 0}, 1259 ACPI_DMT_TERMINATOR 1260 }; 1261 1262 /* 1B: MPAM Memory locator descriptor. A subtable of RIS. 1263 * Arm's DEN0065 MPAM ACPI 2.0. Table 14. 1264 */ 1265 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1B[] = 1266 { 1267 {ACPI_DMT_UINT64, ACPI_MPAM1B_OFFSET (ProximityDomain), "Proximity domain", 0}, 1268 {ACPI_DMT_UINT32, ACPI_MPAM1B_OFFSET (Reserved), "Reserved", 0}, 1269 ACPI_DMT_TERMINATOR 1270 }; 1271 1272 /* 1C: MPAM SMMU locator descriptor. A subtable of RIS. 1273 * Arm's DEN0065 MPAM ACPI 2.0. Table 15. 1274 */ 1275 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1C[] = 1276 { 1277 {ACPI_DMT_UINT64, ACPI_MPAM1C_OFFSET (SmmuInterface), "SMMU Interface", 0}, 1278 {ACPI_DMT_UINT32, ACPI_MPAM1C_OFFSET (Reserved), "Reserved", 0}, 1279 ACPI_DMT_TERMINATOR 1280 }; 1281 1282 /* 1D: MPAM Memory-side cache locator descriptor. A subtable of RIS. 1283 * Arm's DEN0065 MPAM ACPI 2.0. Table 16. 1284 */ 1285 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1D[] = 1286 { 1287 {ACPI_DMT_UINT56, ACPI_MPAM1D_OFFSET (Reserved), "Reserved", 0}, 1288 {ACPI_DMT_UINT8, ACPI_MPAM1D_OFFSET (Level), "Level", 0}, 1289 {ACPI_DMT_UINT32, ACPI_MPAM1D_OFFSET (Reference), "Reference", 0}, 1290 ACPI_DMT_TERMINATOR 1291 }; 1292 1293 /* 1E: MPAM ACPI device locator descriptor. A subtable of RIS. 1294 * Arm's DEN0065 MPAM ACPI 2.0. Table 17. 1295 */ 1296 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1E[] = 1297 { 1298 {ACPI_DMT_UINT64, ACPI_MPAM1E_OFFSET (AcpiHwId), "ACPI Hardware ID", 0}, 1299 {ACPI_DMT_UINT32, ACPI_MPAM1E_OFFSET (AcpiUniqueId), "ACPI Unique ID", 0}, 1300 ACPI_DMT_TERMINATOR 1301 }; 1302 1303 /* 1F: MPAM Interconnect locator descriptor. A subtable of RIS. 1304 * Arm's DEN0065 MPAM ACPI 2.0. Table 18. 1305 */ 1306 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1F[] = 1307 { 1308 {ACPI_DMT_UINT64, ACPI_MPAM1F_OFFSET (InterConnectDescTblOff), "Interconnect descriptor table offset", 0}, 1309 {ACPI_DMT_UINT32, ACPI_MPAM1F_OFFSET (Reserved), "Reserved", 0}, 1310 ACPI_DMT_TERMINATOR 1311 }; 1312 1313 /* 1G: MPAM Locator structure. 1314 * Arm's DEN0065 MPAM ACPI 2.0. Table 12. 1315 */ 1316 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1G[] = 1317 { 1318 {ACPI_DMT_UINT64, ACPI_MPAM1G_OFFSET (Descriptor1), "Descriptor1", 0}, 1319 {ACPI_DMT_UINT32, ACPI_MPAM1G_OFFSET (Descriptor2), "Descriptor2", 0}, 1320 ACPI_DMT_TERMINATOR 1321 }; 1322 1323 /* 2: MPAM Functional dependency descriptor. 1324 * Arm's DEN0065 MPAM ACPI 2.0. Table 10. 1325 */ 1326 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam2[] = 1327 { 1328 {ACPI_DMT_UINT32, ACPI_MPAM2_OFFSET (Producer), "Producer", 0}, 1329 {ACPI_DMT_UINT32, ACPI_MPAM2_OFFSET (Reserved), "Reserved", 0}, 1330 ACPI_DMT_TERMINATOR 1331 }; 1332 1333 1334 /******************************************************************************* 1335 * 1336 * MPST - Memory Power State Table 1337 * 1338 ******************************************************************************/ 1339 1340 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst[] = 1341 { 1342 {ACPI_DMT_UINT8, ACPI_MPST_OFFSET (ChannelId), "Channel ID", 0}, 1343 {ACPI_DMT_UINT24, ACPI_MPST_OFFSET (Reserved1[0]), "Reserved", 0}, 1344 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (PowerNodeCount), "Power Node Count", 0}, 1345 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (Reserved2), "Reserved", 0}, 1346 ACPI_DMT_TERMINATOR 1347 }; 1348 1349 /* MPST subtables */ 1350 1351 /* 0: Memory Power Node Structure */ 1352 1353 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0[] = 1354 { 1355 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1356 {ACPI_DMT_FLAG0, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Node Enabled", 0}, 1357 {ACPI_DMT_FLAG1, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Power Managed", 0}, 1358 {ACPI_DMT_FLAG2, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Hot Plug Capable", 0}, 1359 1360 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Reserved1), "Reserved", 0}, 1361 {ACPI_DMT_UINT16, ACPI_MPST0_OFFSET (NodeId), "Node ID", 0}, 1362 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (Length), "Length", 0}, 1363 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeAddress), "Range Address", 0}, 1364 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeLength), "Range Length", 0}, 1365 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPowerStates), "Num Power States", 0}, 1366 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPhysicalComponents), "Num Physical Components", 0}, 1367 ACPI_DMT_TERMINATOR 1368 }; 1369 1370 /* 0A: Sub-subtable - Memory Power State Structure (follows Memory Power Node above) */ 1371 1372 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0A[] = 1373 { 1374 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (PowerState), "Power State", 0}, 1375 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (InfoIndex), "InfoIndex", 0}, 1376 ACPI_DMT_TERMINATOR 1377 }; 1378 1379 /* 0B: Sub-subtable - Physical Component ID Structure (follows Memory Power State(s) above) */ 1380 1381 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0B[] = 1382 { 1383 {ACPI_DMT_UINT16, ACPI_MPST0B_OFFSET (ComponentId), "Component Id", 0}, 1384 ACPI_DMT_TERMINATOR 1385 }; 1386 1387 /* 01: Power Characteristics Count (follows all Power Node(s) above) */ 1388 1389 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst1[] = 1390 { 1391 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (CharacteristicsCount), "Characteristics Count", 0}, 1392 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (Reserved), "Reserved", 0}, 1393 ACPI_DMT_TERMINATOR 1394 }; 1395 1396 /* 02: Memory Power State Characteristics Structure */ 1397 1398 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst2[] = 1399 { 1400 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (StructureId), "Structure ID", 0}, 1401 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1402 {ACPI_DMT_FLAG0, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Memory Preserved", 0}, 1403 {ACPI_DMT_FLAG1, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Entry", 0}, 1404 {ACPI_DMT_FLAG2, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Exit", 0}, 1405 1406 {ACPI_DMT_UINT16, ACPI_MPST2_OFFSET (Reserved1), "Reserved", 0}, 1407 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (AveragePower), "Average Power", 0}, 1408 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (PowerSaving), "Power Saving", 0}, 1409 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (ExitLatency), "Exit Latency", 0}, 1410 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (Reserved2), "Reserved", 0}, 1411 ACPI_DMT_TERMINATOR 1412 }; 1413 1414 1415 /******************************************************************************* 1416 * 1417 * MRRM - Memory Range and Region Mapping Table 1418 * 1419 ******************************************************************************/ 1420 1421 ACPI_DMTABLE_INFO AcpiDmTableInfoMrrm[] = 1422 { 1423 {ACPI_DMT_UINT8, ACPI_MRRM_OFFSET (MaxMemRegion), "Max Memory Regions", 0}, 1424 {ACPI_DMT_UINT8, ACPI_MRRM_OFFSET (Flags), "Region Assignment Type", 0}, 1425 {ACPI_DMT_BUF26, ACPI_MRRM_OFFSET (Reserved), "Reserved", 0}, 1426 ACPI_DMT_TERMINATOR 1427 }; 1428 1429 /* MRRM Subtable */ 1430 1431 /* 0: Memory Range entry */ 1432 1433 ACPI_DMTABLE_INFO AcpiDmTableInfoMrrm0[] = 1434 { 1435 {ACPI_DMT_UINT16, ACPI_MRRM0_OFFSET (Header.Type), "Memory Range", 0}, 1436 {ACPI_DMT_UINT16, ACPI_MRRM0_OFFSET (Header.Length), "Length", DT_LENGTH}, 1437 {ACPI_DMT_UINT32, ACPI_MRRM0_OFFSET (Reserved0), "Reserved", 0}, 1438 {ACPI_DMT_UINT64, ACPI_MRRM0_OFFSET (AddrBase), "System Address Base", 0}, 1439 {ACPI_DMT_UINT64, ACPI_MRRM0_OFFSET (AddrLen), "System Address Length", 0}, 1440 {ACPI_DMT_UINT16, ACPI_MRRM0_OFFSET (RegionIdFlags), "Region Valid Flags", 0}, 1441 {ACPI_DMT_UINT8, ACPI_MRRM0_OFFSET (LocalRegionId), "Static Local Region ID", 0}, 1442 {ACPI_DMT_UINT8, ACPI_MRRM0_OFFSET (RemoteRegionId), "Static Remote Region ID", 0}, 1443 {ACPI_DMT_UINT32, ACPI_MRRM0_OFFSET (Reserved1), "Reserved", 0}, 1444 ACPI_DMT_TERMINATOR 1445 }; 1446 1447 1448 /******************************************************************************* 1449 * 1450 * MSCT - Maximum System Characteristics Table (ACPI 4.0) 1451 * 1452 ******************************************************************************/ 1453 1454 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct[] = 1455 { 1456 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (ProximityOffset), "Proximity Offset", 0}, 1457 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxProximityDomains), "Max Proximity Domains", 0}, 1458 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxClockDomains), "Max Clock Domains", 0}, 1459 {ACPI_DMT_UINT64, ACPI_MSCT_OFFSET (MaxAddress), "Max Physical Address", 0}, 1460 ACPI_DMT_TERMINATOR 1461 }; 1462 1463 /* Subtable - Maximum Proximity Domain Information. Version 1 */ 1464 1465 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct0[] = 1466 { 1467 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Revision), "Revision", 0}, 1468 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Length), "Length", DT_LENGTH}, 1469 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeStart), "Domain Range Start", 0}, 1470 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeEnd), "Domain Range End", 0}, 1471 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (ProcessorCapacity), "Processor Capacity", 0}, 1472 {ACPI_DMT_UINT64, ACPI_MSCT0_OFFSET (MemoryCapacity), "Memory Capacity", 0}, 1473 ACPI_DMT_TERMINATOR 1474 }; 1475 1476 1477 /******************************************************************************* 1478 * 1479 * NFIT - NVDIMM Firmware Interface Table and Subtables - (ACPI 6.0) 1480 * 1481 ******************************************************************************/ 1482 1483 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit[] = 1484 { 1485 {ACPI_DMT_UINT32, ACPI_NFIT_OFFSET (Reserved), "Reserved", 0}, 1486 ACPI_DMT_TERMINATOR 1487 }; 1488 1489 /* Common Subtable header */ 1490 1491 ACPI_DMTABLE_INFO AcpiDmTableInfoNfitHdr[] = 1492 { 1493 {ACPI_DMT_NFIT, ACPI_NFITH_OFFSET (Type), "Subtable Type", 0}, 1494 {ACPI_DMT_UINT16, ACPI_NFITH_OFFSET (Length), "Length", DT_LENGTH}, 1495 ACPI_DMT_TERMINATOR 1496 }; 1497 1498 /* 0: System Physical Address Range Structure */ 1499 1500 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit0[] = 1501 { 1502 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (RangeIndex), "Range Index", 0}, 1503 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1504 {ACPI_DMT_FLAG0, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Add/Online Operation Only", 0}, 1505 {ACPI_DMT_FLAG1, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Proximity Domain Valid", 0}, 1506 {ACPI_DMT_FLAG2, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Location Cookie Valid", 0}, 1507 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (Reserved), "Reserved", 0}, 1508 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (ProximityDomain), "Proximity Domain", 0}, 1509 {ACPI_DMT_UUID, ACPI_NFIT0_OFFSET (RangeGuid[0]), "Region Type GUID", 0}, 1510 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Address), "Address Range Base", 0}, 1511 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Length), "Address Range Length", 0}, 1512 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (MemoryMapping), "Memory Map Attribute", 0}, 1513 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (LocationCookie), "Location Cookie", 0}, /* ACPI 6.4 */ 1514 ACPI_DMT_TERMINATOR 1515 }; 1516 1517 /* 1: Memory Device to System Address Range Map Structure */ 1518 1519 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit1[] = 1520 { 1521 {ACPI_DMT_UINT32, ACPI_NFIT1_OFFSET (DeviceHandle), "Device Handle", 0}, 1522 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (PhysicalId), "Physical Id", 0}, 1523 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionId), "Region Id", 0}, 1524 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RangeIndex), "Range Index", 0}, 1525 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionIndex), "Control Region Index", 0}, 1526 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionSize), "Region Size", 0}, 1527 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionOffset), "Region Offset", 0}, 1528 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (Address), "Address Region Base", 0}, 1529 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveIndex), "Interleave Index", 0}, 1530 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveWays), "Interleave Ways", 0}, 1531 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Flags), "Flags", DT_FLAG}, 1532 {ACPI_DMT_FLAG0, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Save to device failed", 0}, 1533 {ACPI_DMT_FLAG1, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Restore from device failed", 0}, 1534 {ACPI_DMT_FLAG2, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Platform flush failed", 0}, 1535 {ACPI_DMT_FLAG3, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Device not armed", 0}, 1536 {ACPI_DMT_FLAG4, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events observed", 0}, 1537 {ACPI_DMT_FLAG5, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events enabled", 0}, 1538 {ACPI_DMT_FLAG6, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Mapping failed", 0}, 1539 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Reserved), "Reserved", 0}, 1540 ACPI_DMT_TERMINATOR 1541 }; 1542 1543 /* 2: Interleave Structure */ 1544 1545 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2[] = 1546 { 1547 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (InterleaveIndex), "Interleave Index", 0}, 1548 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (Reserved), "Reserved", 0}, 1549 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineCount), "Line Count", 0}, 1550 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineSize), "Line Size", 0}, 1551 ACPI_DMT_TERMINATOR 1552 }; 1553 1554 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2a[] = 1555 { 1556 {ACPI_DMT_UINT32, 0, "Line Offset", DT_OPTIONAL}, 1557 ACPI_DMT_TERMINATOR 1558 }; 1559 1560 /* 3: SMBIOS Management Information Structure */ 1561 1562 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3[] = 1563 { 1564 {ACPI_DMT_UINT32, ACPI_NFIT3_OFFSET (Reserved), "Reserved", 0}, 1565 ACPI_DMT_TERMINATOR 1566 }; 1567 1568 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3a[] = 1569 { 1570 {ACPI_DMT_RAW_BUFFER, 0, "SMBIOS Table Entries", DT_OPTIONAL}, 1571 ACPI_DMT_TERMINATOR 1572 }; 1573 1574 /* 4: NVDIMM Control Region Structure */ 1575 1576 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit4[] = 1577 { 1578 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RegionIndex), "Region Index", 0}, 1579 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (VendorId), "Vendor Id", 0}, 1580 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (DeviceId), "Device Id", 0}, 1581 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RevisionId), "Revision Id", 0}, 1582 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemVendorId), "Subsystem Vendor Id", 0}, 1583 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemDeviceId), "Subsystem Device Id", 0}, 1584 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemRevisionId), "Subsystem Revision Id", 0}, 1585 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ValidFields), "Valid Fields", 0}, 1586 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ManufacturingLocation), "Manufacturing Location", 0}, 1587 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (ManufacturingDate), "Manufacturing Date", 0}, 1588 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Reserved[0]), "Reserved", 0}, 1589 {ACPI_DMT_UINT32, ACPI_NFIT4_OFFSET (SerialNumber), "Serial Number", 0}, 1590 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Code), "Code", 0}, 1591 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Windows), "Window Count", 0}, 1592 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (WindowSize), "Window Size", 0}, 1593 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandOffset), "Command Offset", 0}, 1594 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandSize), "Command Size", 0}, 1595 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusOffset), "Status Offset", 0}, 1596 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusSize), "Status Size", 0}, 1597 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Flags), "Flags", DT_FLAG}, 1598 {ACPI_DMT_FLAG0, ACPI_NFIT4_FLAG_OFFSET (Flags,0), "Windows buffered", 0}, 1599 {ACPI_DMT_UINT48, ACPI_NFIT4_OFFSET (Reserved1[0]), "Reserved1", 0}, 1600 ACPI_DMT_TERMINATOR 1601 }; 1602 1603 /* 5: NVDIMM Block Data Window Region Structure */ 1604 1605 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit5[] = 1606 { 1607 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (RegionIndex), "Region Index", 0}, 1608 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (Windows), "Window Count", 0}, 1609 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Offset), "Offset", 0}, 1610 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Size), "Size", 0}, 1611 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Capacity), "Capacity", 0}, 1612 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (StartAddress), "Start Address", 0}, 1613 ACPI_DMT_TERMINATOR 1614 }; 1615 1616 /* 6: Flush Hint Address Structure */ 1617 1618 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6[] = 1619 { 1620 {ACPI_DMT_UINT32, ACPI_NFIT6_OFFSET (DeviceHandle), "Device Handle", 0}, 1621 {ACPI_DMT_UINT16, ACPI_NFIT6_OFFSET (HintCount), "Hint Count", 0}, 1622 {ACPI_DMT_UINT48, ACPI_NFIT6_OFFSET (Reserved[0]), "Reserved", 0}, 1623 ACPI_DMT_TERMINATOR 1624 }; 1625 1626 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6a[] = 1627 { 1628 {ACPI_DMT_UINT64, 0, "Hint Address", DT_OPTIONAL}, 1629 ACPI_DMT_TERMINATOR 1630 }; 1631 1632 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit7[] = 1633 { 1634 {ACPI_DMT_UINT8, ACPI_NFIT7_OFFSET (HighestCapability), "Highest Capability", 0}, 1635 {ACPI_DMT_UINT24, ACPI_NFIT7_OFFSET (Reserved[0]), "Reserved", 0}, 1636 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Capabilities), "Capabilities (decoded below)", DT_FLAG}, 1637 {ACPI_DMT_FLAG0, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Cache Flush to NVDIMM", 0}, 1638 {ACPI_DMT_FLAG1, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Flush to NVDIMM", 0}, 1639 {ACPI_DMT_FLAG2, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Mirroring", 0}, 1640 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Reserved2), "Reserved", 0}, 1641 ACPI_DMT_TERMINATOR 1642 }; 1643 1644 1645 /******************************************************************************* 1646 * 1647 * PCCT - Platform Communications Channel Table (ACPI 5.0) 1648 * 1649 ******************************************************************************/ 1650 1651 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct[] = 1652 { 1653 {ACPI_DMT_UINT32, ACPI_PCCT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1654 {ACPI_DMT_FLAG0, ACPI_PCCT_FLAG_OFFSET (Flags,0), "Platform", 0}, 1655 {ACPI_DMT_UINT64, ACPI_PCCT_OFFSET (Reserved), "Reserved", 0}, 1656 ACPI_DMT_TERMINATOR 1657 }; 1658 1659 /* PCCT subtables */ 1660 1661 ACPI_DMTABLE_INFO AcpiDmTableInfoPcctHdr[] = 1662 { 1663 {ACPI_DMT_PCCT, ACPI_PCCT0_OFFSET (Header.Type), "Subtable Type", 0}, 1664 {ACPI_DMT_UINT8, ACPI_PCCT0_OFFSET (Header.Length), "Length", DT_LENGTH}, 1665 ACPI_DMT_TERMINATOR 1666 }; 1667 1668 /* 0: Generic Communications Subspace */ 1669 1670 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct0[] = 1671 { 1672 {ACPI_DMT_UINT48, ACPI_PCCT0_OFFSET (Reserved[0]), "Reserved", 0}, 1673 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (BaseAddress), "Base Address", 0}, 1674 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (Length), "Address Length", 0}, 1675 {ACPI_DMT_GAS, ACPI_PCCT0_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1676 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (PreserveMask), "Preserve Mask", 0}, 1677 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (WriteMask), "Write Mask", 0}, 1678 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (Latency), "Command Latency", 0}, 1679 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1680 {ACPI_DMT_UINT16, ACPI_PCCT0_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1681 ACPI_DMT_TERMINATOR 1682 }; 1683 1684 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */ 1685 1686 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct1[] = 1687 { 1688 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1689 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1690 {ACPI_DMT_FLAG0, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1691 {ACPI_DMT_FLAG1, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Mode", 0}, 1692 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Reserved), "Reserved", 0}, 1693 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (BaseAddress), "Base Address", 0}, 1694 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (Length), "Address Length", 0}, 1695 {ACPI_DMT_GAS, ACPI_PCCT1_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1696 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (PreserveMask), "Preserve Mask", 0}, 1697 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (WriteMask), "Write Mask", 0}, 1698 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (Latency), "Command Latency", 0}, 1699 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1700 {ACPI_DMT_UINT16, ACPI_PCCT1_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1701 ACPI_DMT_TERMINATOR 1702 }; 1703 1704 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */ 1705 1706 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct2[] = 1707 { 1708 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1709 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1710 {ACPI_DMT_FLAG0, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1711 {ACPI_DMT_FLAG1, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Mode", 0}, 1712 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Reserved), "Reserved", 0}, 1713 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (BaseAddress), "Base Address", 0}, 1714 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (Length), "Address Length", 0}, 1715 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1716 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (PreserveMask), "Preserve Mask", 0}, 1717 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (WriteMask), "Write Mask", 0}, 1718 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (Latency), "Command Latency", 0}, 1719 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1720 {ACPI_DMT_UINT16, ACPI_PCCT2_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1721 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1722 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1723 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckWriteMask), "ACK Write Mask", 0}, 1724 ACPI_DMT_TERMINATOR 1725 }; 1726 1727 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */ 1728 1729 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct3[] = 1730 { 1731 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1732 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1733 {ACPI_DMT_FLAG0, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1734 {ACPI_DMT_FLAG1, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Mode", 0}, 1735 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Reserved1), "Reserved", 0}, 1736 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (BaseAddress), "Base Address", 0}, 1737 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Length), "Address Length", 0}, 1738 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1739 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (PreserveMask), "Preserve Mask", 0}, 1740 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (WriteMask), "Write Mask", 0}, 1741 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Latency), "Command Latency", 0}, 1742 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1743 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1744 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1745 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1746 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1747 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (Reserved2), "Reserved", 0}, 1748 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1749 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1750 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1751 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1752 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1753 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1754 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1755 ACPI_DMT_TERMINATOR 1756 }; 1757 1758 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */ 1759 1760 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct4[] = 1761 { 1762 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1763 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1764 {ACPI_DMT_FLAG0, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1765 {ACPI_DMT_FLAG1, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Mode", 0}, 1766 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Reserved1), "Reserved", 0}, 1767 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (BaseAddress), "Base Address", 0}, 1768 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Length), "Address Length", 0}, 1769 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1770 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (PreserveMask), "Preserve Mask", 0}, 1771 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (WriteMask), "Write Mask", 0}, 1772 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Latency), "Command Latency", 0}, 1773 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1774 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1775 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1776 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1777 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1778 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (Reserved2), "Reserved", 0}, 1779 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1780 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1781 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1782 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1783 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1784 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1785 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1786 ACPI_DMT_TERMINATOR 1787 }; 1788 1789 /* 5: HW Registers based Communications Subspace */ 1790 1791 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct5[] = 1792 { 1793 {ACPI_DMT_UINT16, ACPI_PCCT5_OFFSET (Version), "Version", 0}, 1794 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (BaseAddress), "Base Address", 0}, 1795 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (Length), "Length", 0}, 1796 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1797 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellPreserve), "Preserve Mask", 0}, 1798 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellWrite), "Write Mask", 0}, 1799 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1800 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1801 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1802 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1803 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (NominalLatency), "Nominal Latency", 0}, 1804 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1805 ACPI_DMT_TERMINATOR 1806 }; 1807 1808 1809 /******************************************************************************* 1810 * 1811 * PDTT - Platform Debug Trigger Table (ACPI 6.2) 1812 * 1813 ******************************************************************************/ 1814 1815 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt[] = 1816 { 1817 {ACPI_DMT_UINT8, ACPI_PDTT_OFFSET (TriggerCount), "Trigger Count", 0}, 1818 {ACPI_DMT_UINT24, ACPI_PDTT_OFFSET (Reserved), "Reserved", 0}, 1819 {ACPI_DMT_UINT32, ACPI_PDTT_OFFSET (ArrayOffset), "Array Offset", 0}, 1820 ACPI_DMT_TERMINATOR 1821 }; 1822 1823 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt0[] = 1824 { 1825 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (SubchannelId), "Subchannel Id", 0}, 1826 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1827 {ACPI_DMT_FLAG0, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Runtime Trigger", 0}, 1828 {ACPI_DMT_FLAG1, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Wait for Completion", 0}, 1829 {ACPI_DMT_FLAG2, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Trigger Order", 0}, 1830 ACPI_DMT_TERMINATOR 1831 }; 1832 1833 1834 /******************************************************************************* 1835 * 1836 * PHAT - Platform Health Assessment Table (ACPI 6.4) 1837 * 1838 ******************************************************************************/ 1839 1840 /* Common subtable header */ 1841 1842 ACPI_DMTABLE_INFO AcpiDmTableInfoPhatHdr[] = 1843 { 1844 {ACPI_DMT_PHAT, ACPI_PHATH_OFFSET (Type), "Subtable Type", 0}, 1845 {ACPI_DMT_UINT16, ACPI_PHATH_OFFSET (Length), "Length", DT_LENGTH}, 1846 {ACPI_DMT_UINT8, ACPI_PHATH_OFFSET (Revision), "Revision", 0}, 1847 ACPI_DMT_TERMINATOR 1848 }; 1849 1850 /* 0: Firmware version table */ 1851 1852 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0[] = 1853 { 1854 {ACPI_DMT_UINT24, ACPI_PHAT0_OFFSET (Reserved), "Reserved", 0}, 1855 {ACPI_DMT_UINT32, ACPI_PHAT0_OFFSET (ElementCount), "Element Count", 0}, 1856 ACPI_DMT_TERMINATOR 1857 }; 1858 1859 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0a[] = 1860 { 1861 {ACPI_DMT_UUID, ACPI_PHAT0A_OFFSET (Guid), "GUID", 0}, 1862 {ACPI_DMT_UINT64, ACPI_PHAT0A_OFFSET (VersionValue), "Version Value", 0}, 1863 {ACPI_DMT_UINT32, ACPI_PHAT0A_OFFSET (ProducerId), "Producer ID", 0}, 1864 ACPI_DMT_TERMINATOR 1865 }; 1866 1867 /* 1: Firmware Health Data Record */ 1868 1869 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1[] = 1870 { 1871 {ACPI_DMT_UINT16, ACPI_PHAT1_OFFSET (Reserved), "Reserved", 0}, 1872 {ACPI_DMT_UINT8, ACPI_PHAT1_OFFSET (Health), "Health", 0}, 1873 {ACPI_DMT_UUID, ACPI_PHAT1_OFFSET (DeviceGuid), "Device GUID", 0}, 1874 {ACPI_DMT_UINT32, ACPI_PHAT1_OFFSET (DeviceSpecificOffset), "Device-Specific Offset", 0}, 1875 ACPI_DMT_TERMINATOR 1876 }; 1877 1878 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1a[] = 1879 { 1880 {ACPI_DMT_UNICODE, 0, "Device Path", 0}, 1881 ACPI_DMT_TERMINATOR 1882 }; 1883 1884 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1b[] = 1885 { 1886 {ACPI_DMT_RAW_BUFFER, 0, "Device-Specific Data", DT_OPTIONAL}, 1887 ACPI_DMT_TERMINATOR 1888 }; 1889 1890 1891 /******************************************************************************* 1892 * 1893 * PMTT - Platform Memory Topology Table 1894 * 1895 ******************************************************************************/ 1896 1897 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt[] = 1898 { 1899 {ACPI_DMT_UINT32, ACPI_PMTT_OFFSET (MemoryDeviceCount), "Memory Device Count", 0}, 1900 ACPI_DMT_TERMINATOR 1901 }; 1902 1903 /* Common Subtable header (one per Subtable) */ 1904 1905 #define ACPI_DM_PMTT_HEADER \ 1906 {ACPI_DMT_PMTT, ACPI_PMTTH_OFFSET (Type), "Subtable Type", 0}, \ 1907 {ACPI_DMT_UINT8, ACPI_PMTTH_OFFSET (Reserved1), "Reserved", 0}, \ 1908 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Length), "Length", DT_LENGTH}, \ 1909 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, \ 1910 {ACPI_DMT_FLAG0, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Top-level Device", 0}, \ 1911 {ACPI_DMT_FLAG1, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Physical Element", 0}, \ 1912 {ACPI_DMT_FLAGS2, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Memory Type", 0}, \ 1913 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Reserved2), "Reserved", 0}, \ 1914 {ACPI_DMT_UINT32, ACPI_PMTTH_OFFSET (MemoryDeviceCount), "Memory Device Count", 0} 1915 1916 /* PMTT Subtables */ 1917 1918 /* 0: Socket */ 1919 1920 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt0[] = 1921 { 1922 ACPI_DM_PMTT_HEADER, 1923 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (SocketId), "Socket ID", 0}, 1924 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (Reserved), "Reserved", 0}, 1925 ACPI_DMT_TERMINATOR 1926 }; 1927 1928 /* 1: Memory Controller */ 1929 1930 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt1[] = 1931 { 1932 ACPI_DM_PMTT_HEADER, 1933 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (ControllerId), "Controller ID", 0}, 1934 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (Reserved), "Reserved", 0}, 1935 ACPI_DMT_TERMINATOR 1936 }; 1937 1938 /* 2: Physical Component */ 1939 1940 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt2[] = 1941 { 1942 ACPI_DM_PMTT_HEADER, 1943 {ACPI_DMT_UINT32, ACPI_PMTT2_OFFSET (BiosHandle), "Bios Handle", 0}, 1944 ACPI_DMT_TERMINATOR 1945 }; 1946 1947 /* 0xFF: Vendor Specific */ 1948 1949 ACPI_DMTABLE_INFO AcpiDmTableInfoPmttVendor[] = 1950 { 1951 ACPI_DM_PMTT_HEADER, 1952 {ACPI_DMT_UUID, ACPI_PMTT_VENDOR_OFFSET (TypeUuid), "Type Uuid", 0}, 1953 {ACPI_DMT_PMTT_VENDOR, ACPI_PMTT_VENDOR_OFFSET (Specific), "Vendor Data", 0}, 1954 ACPI_DMT_TERMINATOR 1955 }; 1956 1957 1958 /******************************************************************************* 1959 * 1960 * PPTT - Processor Properties Topology Table (ACPI 6.2) 1961 * 1962 ******************************************************************************/ 1963 1964 /* Main table consists of only the standard ACPI header - subtables follow */ 1965 1966 /* Common Subtable header (one per Subtable) */ 1967 1968 ACPI_DMTABLE_INFO AcpiDmTableInfoPpttHdr[] = 1969 { 1970 {ACPI_DMT_PPTT, ACPI_PPTTH_OFFSET (Type), "Subtable Type", 0}, 1971 {ACPI_DMT_UINT8, ACPI_PPTTH_OFFSET (Length), "Length", 0}, 1972 ACPI_DMT_TERMINATOR 1973 }; 1974 1975 /* 0: Processor hierarchy node */ 1976 1977 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0[] = 1978 { 1979 {ACPI_DMT_UINT16, ACPI_PPTT0_OFFSET (Reserved), "Reserved", 0}, 1980 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1981 {ACPI_DMT_FLAG0, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Physical package", 0}, 1982 {ACPI_DMT_FLAG1, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "ACPI Processor ID valid", 0}, 1983 {ACPI_DMT_FLAG2, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Processor is a thread", 0}, 1984 {ACPI_DMT_FLAG3, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Node is a leaf", 0}, 1985 {ACPI_DMT_FLAG4, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Identical Implementation", 0}, 1986 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Parent), "Parent", 0}, 1987 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (AcpiProcessorId), "ACPI Processor ID", 0}, 1988 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (NumberOfPrivResources), "Private Resource Number", 0}, 1989 ACPI_DMT_TERMINATOR 1990 }; 1991 1992 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0a[] = 1993 { 1994 {ACPI_DMT_UINT32, 0, "Private Resource", DT_OPTIONAL}, 1995 ACPI_DMT_TERMINATOR 1996 }; 1997 1998 /* 1: Cache type */ 1999 2000 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1[] = 2001 { 2002 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (Reserved), "Reserved", 0}, 2003 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Flags), "Flags (decoded below)", 0}, 2004 {ACPI_DMT_FLAG0, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Size valid", 0}, 2005 {ACPI_DMT_FLAG1, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Number of Sets valid", 0}, 2006 {ACPI_DMT_FLAG2, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Associativity valid", 0}, 2007 {ACPI_DMT_FLAG3, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Allocation Type valid", 0}, 2008 {ACPI_DMT_FLAG4, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache Type valid", 0}, 2009 {ACPI_DMT_FLAG5, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Write Policy valid", 0}, 2010 {ACPI_DMT_FLAG6, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Line Size valid", 0}, 2011 {ACPI_DMT_FLAG7, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache ID valid", 0}, 2012 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NextLevelOfCache), "Next Level of Cache", 0}, 2013 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Size), "Size", 0}, 2014 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NumberOfSets), "Number of Sets", 0}, 2015 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Associativity), "Associativity", 0}, 2016 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Attributes), "Attributes", 0}, 2017 {ACPI_DMT_FLAGS0, ACPI_PPTT1_OFFSET (Attributes), "Allocation Type", 0}, 2018 {ACPI_DMT_FLAGS2, ACPI_PPTT1_OFFSET (Attributes), "Cache Type", 0}, 2019 {ACPI_DMT_FLAG4, ACPI_PPTT1_OFFSET (Attributes), "Write Policy", 0}, 2020 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (LineSize), "Line Size", 0}, 2021 ACPI_DMT_TERMINATOR 2022 }; 2023 2024 /* 1: cache type v1 */ 2025 2026 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1a[] = 2027 { 2028 {ACPI_DMT_UINT16, ACPI_PPTT1A_OFFSET (Reserved), "Reserved", 0}, 2029 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (Flags), "Flags (decoded below)", 0}, 2030 {ACPI_DMT_FLAG0, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Size valid", 0}, 2031 {ACPI_DMT_FLAG1, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Number of Sets valid", 0}, 2032 {ACPI_DMT_FLAG2, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Associativity valid", 0}, 2033 {ACPI_DMT_FLAG3, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Allocation Type valid", 0}, 2034 {ACPI_DMT_FLAG4, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Cache Type valid", 0}, 2035 {ACPI_DMT_FLAG5, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Write Policy valid", 0}, 2036 {ACPI_DMT_FLAG6, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Line Size valid", 0}, 2037 {ACPI_DMT_FLAG7, ACPI_PPTT1A_FLAG_OFFSET (Flags,0), "Cache ID valid", 0}, 2038 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (NextLevelOfCache), "Next Level of Cache", 0}, 2039 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (Size), "Size", 0}, 2040 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (NumberOfSets), "Number of Sets", 0}, 2041 {ACPI_DMT_UINT8, ACPI_PPTT1A_OFFSET (Associativity), "Associativity", 0}, 2042 {ACPI_DMT_UINT8, ACPI_PPTT1A_OFFSET (Attributes), "Attributes", 0}, 2043 {ACPI_DMT_FLAGS0, ACPI_PPTT1A_OFFSET (Attributes), "Allocation Type", 0}, 2044 {ACPI_DMT_FLAGS2, ACPI_PPTT1A_OFFSET (Attributes), "Cache Type", 0}, 2045 {ACPI_DMT_FLAG4, ACPI_PPTT1A_OFFSET (Attributes), "Write Policy", 0}, 2046 {ACPI_DMT_UINT16, ACPI_PPTT1A_OFFSET (LineSize), "Line Size", 0}, 2047 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (CacheId), "Cache ID", 0}, 2048 ACPI_DMT_TERMINATOR 2049 }; 2050 2051 /* 2: ID */ 2052 2053 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt2[] = 2054 { 2055 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (Reserved), "Reserved", 0}, 2056 {ACPI_DMT_UINT32, ACPI_PPTT2_OFFSET (VendorId), "Vendor ID", 0}, 2057 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level1Id), "Level1 ID", 0}, 2058 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level2Id), "Level2 ID", 0}, 2059 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MajorRev), "Major revision", 0}, 2060 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MinorRev), "Minor revision", 0}, 2061 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (SpinRev), "Spin revision", 0}, 2062 ACPI_DMT_TERMINATOR 2063 }; 2064 2065 2066 /******************************************************************************* 2067 * 2068 * PRMT - Platform Runtime Mechanism Table 2069 * Version 1 2070 * 2071 ******************************************************************************/ 2072 2073 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHdr[] = 2074 { 2075 {ACPI_DMT_UUID, ACPI_PRMTH_OFFSET (PlatformGuid[0]), "Platform GUID", 0}, 2076 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoOffset), "Module info offset", 0}, 2077 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoCount), "Module info count", 0}, 2078 ACPI_DMT_NEW_LINE, 2079 ACPI_DMT_TERMINATOR 2080 2081 }; 2082 2083 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtModule[] = 2084 { 2085 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Revision), "Revision", 0}, 2086 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Length), "Length", 0}, 2087 {ACPI_DMT_UUID, ACPI_PRMT0_OFFSET (ModuleGuid[0]), "Module GUID", 0}, 2088 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MajorRev), "Major Revision", 0}, 2089 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MinorRev), "Minor Revision", 0}, 2090 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (HandlerInfoCount), "Handler Info Count", 0}, 2091 {ACPI_DMT_UINT32, ACPI_PRMT0_OFFSET (HandlerInfoOffset), "Handler Info Offset", 0}, 2092 {ACPI_DMT_UINT64, ACPI_PRMT0_OFFSET (MmioListPointer), "Mmio List pointer", 0}, 2093 ACPI_DMT_NEW_LINE, 2094 ACPI_DMT_TERMINATOR 2095 2096 }; 2097 2098 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHandler[] = 2099 { 2100 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Revision), "Revision", 0}, 2101 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Length), "Length", 0}, 2102 {ACPI_DMT_UUID, ACPI_PRMT1_OFFSET (HandlerGuid[0]), "Handler GUID", 0}, 2103 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (HandlerAddress), "Handler address", 0}, 2104 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (StaticDataBufferAddress),"Static Data Address", 0}, 2105 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (AcpiParamBufferAddress), "ACPI Parameter Address", 0}, 2106 ACPI_DMT_NEW_LINE, 2107 ACPI_DMT_TERMINATOR 2108 2109 }; 2110 2111 2112 /******************************************************************************* 2113 * 2114 * RASF - RAS Feature table 2115 * 2116 ******************************************************************************/ 2117 2118 ACPI_DMTABLE_INFO AcpiDmTableInfoRasf[] = 2119 { 2120 {ACPI_DMT_BUF12, ACPI_RASF_OFFSET (ChannelId[0]), "Channel ID", 0}, 2121 ACPI_DMT_TERMINATOR 2122 }; 2123 2124 2125 /******************************************************************************* 2126 * 2127 * RAS2 - RAS2 Feature table (ACPI 6.5) 2128 * 2129 ******************************************************************************/ 2130 2131 ACPI_DMTABLE_INFO AcpiDmTableInfoRas2[] = 2132 { 2133 {ACPI_DMT_UINT16, ACPI_RAS2_OFFSET (Reserved), "Reserved", 0}, 2134 {ACPI_DMT_UINT16, ACPI_RAS2_OFFSET (NumPccDescs), "Number of PCC Descriptors", 0}, 2135 ACPI_DMT_TERMINATOR 2136 }; 2137 2138 /* RAS2 PCC Descriptor */ 2139 2140 ACPI_DMTABLE_INFO AcpiDmTableInfoRas2PccDesc[] = 2141 { 2142 {ACPI_DMT_UINT8, ACPI_RAS2_PCC_DESC_OFFSET (ChannelId), "Channel ID", 0}, 2143 {ACPI_DMT_UINT16, ACPI_RAS2_PCC_DESC_OFFSET (Reserved), "Reserved", 0}, 2144 {ACPI_DMT_UINT8, ACPI_RAS2_PCC_DESC_OFFSET (FeatureType), "Feature Type", 0}, 2145 {ACPI_DMT_UINT32, ACPI_RAS2_PCC_DESC_OFFSET (Instance), "Instance", 0}, 2146 ACPI_DMT_TERMINATOR 2147 }; 2148 2149 2150 /******************************************************************************* 2151 * 2152 * RGRT - Regulatory Graphics Resource Table 2153 * 2154 ******************************************************************************/ 2155 2156 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt[] = 2157 { 2158 {ACPI_DMT_UINT16, ACPI_RGRT_OFFSET (Version), "Version", 0}, 2159 {ACPI_DMT_RGRT, ACPI_RGRT_OFFSET (ImageType), "Image Type", 0}, 2160 {ACPI_DMT_UINT8, ACPI_RGRT_OFFSET (Reserved), "Reserved", 0}, 2161 ACPI_DMT_TERMINATOR 2162 }; 2163 2164 /* 2165 * We treat the binary image field as its own subtable (to make 2166 * ACPI_DMT_RAW_BUFFER work properly). 2167 */ 2168 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt0[] = 2169 { 2170 {ACPI_DMT_RAW_BUFFER, 0, "Image", 0}, 2171 ACPI_DMT_TERMINATOR 2172 }; 2173 2174 2175 /******************************************************************************* 2176 * 2177 * RHCT - RISC-V Hart Capabilities Table 2178 * 2179 ******************************************************************************/ 2180 2181 ACPI_DMTABLE_INFO AcpiDmTableInfoRhct[] = 2182 { 2183 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (Flags), "Flags", 0}, 2184 {ACPI_DMT_UINT64, ACPI_RHCT_OFFSET (TimeBaseFreq), "Timer Base Frequency", 0}, 2185 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (NodeCount), "Number of nodes", 0}, 2186 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (NodeOffset), "Offset to the node array", 0}, 2187 ACPI_DMT_TERMINATOR 2188 }; 2189 2190 2191 /* Common Subtable header (one per Subtable) */ 2192 2193 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctNodeHdr[] = 2194 { 2195 {ACPI_DMT_RHCT, ACPI_RHCTH_OFFSET (Type), "Subtable Type", 0}, 2196 {ACPI_DMT_UINT16, ACPI_RHCTH_OFFSET (Length), "Length", DT_LENGTH}, 2197 {ACPI_DMT_UINT16, ACPI_RHCTH_OFFSET (Revision), "Revision", 0}, 2198 ACPI_DMT_TERMINATOR 2199 }; 2200 2201 /* 0: ISA string type */ 2202 2203 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctIsa1[] = 2204 { 2205 {ACPI_DMT_UINT16, ACPI_RHCT0_OFFSET (IsaLength), "ISA string length", 0}, 2206 {ACPI_DMT_STRING, ACPI_RHCT0_OFFSET (Isa[0]), "ISA string", 0}, 2207 ACPI_DMT_TERMINATOR 2208 }; 2209 2210 2211 /* Optional padding field */ 2212 2213 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctIsaPad[] = 2214 { 2215 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 2216 ACPI_DMT_TERMINATOR 2217 }; 2218 2219 /* 1: CMO node type */ 2220 2221 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctCmo1[] = 2222 { 2223 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (Reserved), "Reserved", 0}, 2224 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbomSize), "CBOM Block Size", 0}, 2225 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbopSize), "CBOP Block Size", 0}, 2226 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbozSize), "CBOZ Block Size", 0}, 2227 ACPI_DMT_TERMINATOR 2228 }; 2229 2230 /* 2: MMU node type */ 2231 2232 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctMmu1[] = 2233 { 2234 {ACPI_DMT_UINT8, ACPI_RHCT2_OFFSET (Reserved), "Reserved", 0}, 2235 {ACPI_DMT_UINT8, ACPI_RHCT2_OFFSET (MmuType), "MMU Type", 0}, 2236 ACPI_DMT_TERMINATOR 2237 }; 2238 2239 /* 0xFFFF: Hart Info type */ 2240 2241 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctHartInfo1[] = 2242 { 2243 {ACPI_DMT_UINT16, ACPI_RHCTFFFF_OFFSET (NumOffsets), "Number of offsets", 0}, 2244 {ACPI_DMT_UINT32, ACPI_RHCTFFFF_OFFSET (Uid), "Processor UID", 0}, 2245 ACPI_DMT_TERMINATOR 2246 }; 2247 2248 2249 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctHartInfo2[] = 2250 { 2251 {ACPI_DMT_UINT32, 0, "Nodes", DT_OPTIONAL}, 2252 ACPI_DMT_TERMINATOR 2253 }; 2254 2255 2256 /******************************************************************************* 2257 * 2258 * RIMT - RISC-V IO Mapping Table 2259 * 2260 * https://github.com/riscv-non-isa/riscv-acpi-rimt 2261 * 2262 ******************************************************************************/ 2263 2264 ACPI_DMTABLE_INFO AcpiDmTableInfoRimt[] = 2265 { 2266 {ACPI_DMT_UINT32, ACPI_RIMT_OFFSET (NumNodes), "Number of RIMT Nodes", 0}, 2267 {ACPI_DMT_UINT32, ACPI_RIMT_OFFSET (NodeOffset), "Offset to RIMT Node Array", 0}, 2268 {ACPI_DMT_UINT32, ACPI_RIMT_OFFSET (Reserved), "Reserved", 0}, 2269 ACPI_DMT_TERMINATOR 2270 }; 2271 2272 2273 /* Common Subtable header (one per Subtable) */ 2274 2275 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtNodeHdr[] = 2276 { 2277 {ACPI_DMT_UINT8, ACPI_RIMTH_OFFSET (Type), "Type", 0}, 2278 {ACPI_DMT_UINT8, ACPI_RIMTH_OFFSET (Revision), "Revision", 0}, 2279 {ACPI_DMT_UINT16, ACPI_RIMTH_OFFSET (Length), "Length", 0}, 2280 {ACPI_DMT_UINT16, ACPI_RIMTH_OFFSET (Reserved), "Reserved", 0}, 2281 {ACPI_DMT_UINT16, ACPI_RIMTH_OFFSET (Id), "ID", 0}, 2282 ACPI_DMT_TERMINATOR 2283 }; 2284 2285 /* 0: IOMMU Node type */ 2286 2287 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtIommu[] = 2288 { 2289 {ACPI_DMT_NAME8, ACPI_RIMTI_OFFSET (HardwareId), "Hardware ID", 0}, 2290 {ACPI_DMT_UINT64, ACPI_RIMTI_OFFSET (BaseAddress), "Base Address", 0}, 2291 {ACPI_DMT_UINT32, ACPI_RIMTI_OFFSET (Flags), "Flags", 0}, 2292 {ACPI_DMT_UINT32, ACPI_RIMTI_OFFSET (ProximityDomain), "Proximity Domain", 0}, 2293 {ACPI_DMT_UINT16, ACPI_RIMTI_OFFSET (PcieSegmentNumber), "PCIe Segment number", 0}, 2294 {ACPI_DMT_UINT16, ACPI_RIMTI_OFFSET (PcieBdf), "PCIe B/D/F", 0}, 2295 {ACPI_DMT_UINT16, ACPI_RIMTI_OFFSET (NumInterruptWires), "Number of interrupt wires", 0}, 2296 {ACPI_DMT_UINT16, ACPI_RIMTI_OFFSET (InterruptWireOffset), "Interrupt wire array offset", 0}, 2297 ACPI_DMT_TERMINATOR 2298 }; 2299 2300 2301 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtIommuWire[] = 2302 { 2303 {ACPI_DMT_UINT32, ACPI_RIMTW_OFFSET (IrqNum), "Interrupt Number", 0}, 2304 {ACPI_DMT_UINT32, ACPI_RIMTW_OFFSET (Flags), "Flags", 0}, 2305 ACPI_DMT_TERMINATOR 2306 }; 2307 2308 /* 1: PCIE Root Complex Node type */ 2309 2310 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtPcieRc[] = 2311 { 2312 {ACPI_DMT_UINT32, ACPI_RIMTP_OFFSET (Flags), "Flags", 0}, 2313 {ACPI_DMT_UINT16, ACPI_RIMTP_OFFSET (Reserved), "Reserved", 0}, 2314 {ACPI_DMT_UINT16, ACPI_RIMTP_OFFSET (PcieSegmentNumber), "PCIe Segment number", 0}, 2315 {ACPI_DMT_UINT16, ACPI_RIMTP_OFFSET (IdMappingOffset), "ID mapping array offset", 0}, 2316 {ACPI_DMT_UINT16, ACPI_RIMTP_OFFSET (NumIdMappings), "Number of ID mappings", 0}, 2317 ACPI_DMT_TERMINATOR 2318 }; 2319 2320 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtIdMapping[] = 2321 { 2322 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (SourceIdBase), "Source ID Base", 0}, 2323 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (NumIds), "Number of IDs", 0}, 2324 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (DestIdBase), "Destination Device ID Base", 0}, 2325 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (DestOffset), "Destination IOMMU Offset", 0}, 2326 {ACPI_DMT_UINT32, ACPI_RIMTM_OFFSET (Flags), "Flags", 0}, 2327 ACPI_DMT_TERMINATOR 2328 }; 2329 2330 /* 2: Platform Device Node type */ 2331 2332 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtPlatDev[] = 2333 { 2334 {ACPI_DMT_UINT16, ACPI_RIMTN_OFFSET (IdMappingOffset), "ID mapping array offset", 0}, 2335 {ACPI_DMT_UINT16, ACPI_RIMTN_OFFSET (NumIdMappings), "Number of ID mappings", 0}, 2336 {ACPI_DMT_STRING, ACPI_RIMTN_OFFSET (DeviceName[0]), "Device Object Name", 0}, 2337 ACPI_DMT_TERMINATOR 2338 }; 2339 2340 ACPI_DMTABLE_INFO AcpiDmTableInfoRimtPlatDevPad[] = 2341 { 2342 {ACPI_DMT_RAW_BUFFER, 0, "Padding", DT_OPTIONAL}, 2343 ACPI_DMT_TERMINATOR 2344 }; 2345 2346 2347 /******************************************************************************* 2348 * 2349 * S3PT - S3 Performance Table 2350 * 2351 ******************************************************************************/ 2352 2353 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt[] = 2354 { 2355 {ACPI_DMT_SIG, ACPI_S3PT_OFFSET (Signature[0]), "Signature", 0}, 2356 {ACPI_DMT_UINT32, ACPI_S3PT_OFFSET (Length), "Length", DT_LENGTH}, 2357 ACPI_DMT_TERMINATOR 2358 }; 2359 2360 /* S3PT subtable header */ 2361 2362 ACPI_DMTABLE_INFO AcpiDmTableInfoS3ptHdr[] = 2363 { 2364 {ACPI_DMT_UINT16, ACPI_S3PTH_OFFSET (Type), "Type", 0}, 2365 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Length), "Length", DT_LENGTH}, 2366 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Revision), "Revision", 0}, 2367 ACPI_DMT_TERMINATOR 2368 }; 2369 2370 /* 0: Basic S3 Resume Performance Record */ 2371 2372 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt0[] = 2373 { 2374 {ACPI_DMT_UINT32, ACPI_S3PT0_OFFSET (ResumeCount), "Resume Count", 0}, 2375 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (FullResume), "Full Resume", 0}, 2376 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (AverageResume), "Average Resume", 0}, 2377 ACPI_DMT_TERMINATOR 2378 }; 2379 2380 /* 1: Basic S3 Suspend Performance Record */ 2381 2382 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt1[] = 2383 { 2384 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendStart), "Suspend Start", 0}, 2385 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendEnd), "Suspend End", 0}, 2386 ACPI_DMT_TERMINATOR 2387 }; 2388 2389 2390 /******************************************************************************* 2391 * 2392 * SBST - Smart Battery Specification Table 2393 * 2394 ******************************************************************************/ 2395 2396 ACPI_DMTABLE_INFO AcpiDmTableInfoSbst[] = 2397 { 2398 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (WarningLevel), "Warning Level", 0}, 2399 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (LowLevel), "Low Level", 0}, 2400 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (CriticalLevel), "Critical Level", 0}, 2401 ACPI_DMT_TERMINATOR 2402 }; 2403 2404 2405 /******************************************************************************* 2406 * 2407 * SDEI - Software Delegated Exception Interface Descriptor Table 2408 * 2409 ******************************************************************************/ 2410 2411 ACPI_DMTABLE_INFO AcpiDmTableInfoSdei[] = 2412 { 2413 ACPI_DMT_TERMINATOR 2414 }; 2415 2416 2417 /******************************************************************************* 2418 * 2419 * SDEV - Secure Devices Table (ACPI 6.2) 2420 * 2421 ******************************************************************************/ 2422 2423 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev[] = 2424 { 2425 ACPI_DMT_TERMINATOR 2426 }; 2427 2428 /* Common Subtable header (one per Subtable) */ 2429 2430 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevHdr[] = 2431 { 2432 {ACPI_DMT_SDEV, ACPI_SDEVH_OFFSET (Type), "Subtable Type", 0}, 2433 {ACPI_DMT_UINT8, ACPI_SDEVH_OFFSET (Flags), "Flags (decoded below)", 0}, 2434 {ACPI_DMT_FLAG0, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Allow handoff to unsecure OS", 0}, 2435 {ACPI_DMT_FLAG1, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Secure access components present", 0}, 2436 {ACPI_DMT_UINT16, ACPI_SDEVH_OFFSET (Length), "Length", DT_LENGTH}, 2437 ACPI_DMT_TERMINATOR 2438 }; 2439 2440 /* SDEV Subtables */ 2441 2442 /* 0: Namespace Device Based Secure Device Structure */ 2443 2444 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0[] = 2445 { 2446 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdOffset), "Device ID Offset", 0}, 2447 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdLength), "Device ID Length", 0}, 2448 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2449 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2450 ACPI_DMT_TERMINATOR 2451 }; 2452 2453 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0a[] = 2454 { 2455 {ACPI_DMT_STRING, 0, "Namepath", 0}, 2456 ACPI_DMT_TERMINATOR 2457 }; 2458 2459 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0b[] = 2460 { 2461 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentOffset), "Secure Access Components Offset", 0}, 2462 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentLength), "Secure Access Components Length", 0}, 2463 ACPI_DMT_TERMINATOR 2464 }; 2465 2466 /* Secure access components */ 2467 2468 /* Common secure access components header secure access component */ 2469 2470 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompHdr[] = 2471 { 2472 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Type), "Secure Component Type", 0}, 2473 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Flags), "Flags (decoded below)", 0}, 2474 {ACPI_DMT_UINT16, ACPI_SDEVCH_OFFSET (Length), "Length", 0}, 2475 ACPI_DMT_TERMINATOR 2476 }; 2477 2478 /* 0: Identification Based Secure Access Component */ 2479 2480 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompId[] = 2481 { 2482 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdOffset), "Hardware ID Offset", 0}, 2483 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdLength), "Hardware ID Length", 0}, 2484 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdOffset), "Subsystem ID Offset", 0}, 2485 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdLength), "Subsystem ID Length", 0}, 2486 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareRevision), "Hardware Revision", 0}, 2487 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (HardwareRevPresent), "Hardware Rev Present", 0}, 2488 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (ClassCodePresent), "Class Code Present", 0}, 2489 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciBaseClass), "PCI Base Class", 0}, 2490 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciSubClass), "PCI SubClass", 0}, 2491 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciProgrammingXface), "PCI Programming Xface", 0}, 2492 ACPI_DMT_TERMINATOR 2493 }; 2494 2495 /* 1: Memory Based Secure Access Component */ 2496 2497 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompMem[] = 2498 { 2499 {ACPI_DMT_UINT32, ACPI_SDEVC1_OFFSET (Reserved), "Reserved", 0}, 2500 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryBaseAddress), "Memory Base Address", 0}, 2501 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryLength), "Memory Length", 0}, 2502 ACPI_DMT_TERMINATOR 2503 }; 2504 2505 2506 /* 1: PCIe Endpoint Device Based Device Structure */ 2507 2508 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1[] = 2509 { 2510 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (Segment), "Segment", 0}, 2511 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (StartBus), "Start Bus", 0}, 2512 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathOffset), "Path Offset", 0}, 2513 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathLength), "Path Length", 0}, 2514 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2515 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2516 ACPI_DMT_TERMINATOR 2517 }; 2518 2519 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1a[] = 2520 { 2521 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Device), "Device", 0}, 2522 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Function), "Function", 0}, 2523 ACPI_DMT_TERMINATOR 2524 }; 2525 2526 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1b[] = 2527 { 2528 {ACPI_DMT_RAW_BUFFER, 0, "Vendor Data", 0}, /*, DT_OPTIONAL}, */ 2529 ACPI_DMT_TERMINATOR 2530 }; 2531 2532 /*! [End] no source code translation !*/ 2533
Indexes created Sat Feb 21 16:20:20 UTC 2026