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    Searched defs:AddSubOpc (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerCombiner.cpp 170 unsigned ShiftAmt, AddSubOpc;
184 AddSubOpc = TargetOpcode::G_ADD;
187 AddSubOpc = TargetOpcode::G_SUB;
197 AddSubOpc = TargetOpcode::G_SUB;
201 AddSubOpc = TargetOpcode::G_ADD;
216 auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS});
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MLxExpansionPass.cpp 68 unsigned MulOpc, unsigned AddSubOpc,
270 unsigned MulOpc, unsigned AddSubOpc,
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
354 unsigned MulOpc, AddSubOpc;
357 MulOpc, AddSubOpc, NegAcc, HasLane) ||
361 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane);
ARMBaseInstrInfo.cpp 85 uint16_t AddSubOpc; // Expanded add / sub opcode
91 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
119 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
4890 unsigned &AddSubOpc,
4898 AddSubOpc = Entry.AddSubOpc;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 12251 unsigned ShiftAmt, AddSubOpc;
12265 AddSubOpc = ISD::ADD;
12268 AddSubOpc = ISD::SUB;
12278 AddSubOpc = ISD::SUB;
12282 AddSubOpc = ISD::ADD;
12295 SDValue Res = DAG.getNode(AddSubOpc, DL, VT, AddSubN0, AddSubN1);

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