| /src/external/apache2/llvm/dist/clang/lib/AST/ |
| ScanfFormatString.cpp | 132 const OptionalAmount &Amt = clang::analyze_format_string::ParseAmount(I, E);
133 if (Amt.getHowSpecified() != OptionalAmount::NotSpecified) {
134 assert(Amt.getHowSpecified() == OptionalAmount::Constant);
135 FS.setFieldWidth(Amt);
|
| FormatString.cpp | 82 const OptionalAmount &Amt = ParseAmount(I, E);
84 if (Amt.getHowSpecified() == OptionalAmount::NotSpecified) {
95 assert(Amt.getHowSpecified() == OptionalAmount::Constant);
101 if (Amt.getConstantAmount() == 0) {
109 return OptionalAmount(OptionalAmount::Arg, Amt.getConstantAmount() - 1,
132 const OptionalAmount Amt =
136 if (Amt.isInvalid())
138 CS.setFieldWidth(Amt);
151 const OptionalAmount &Amt = ParseAmount(I, E);
159 if (Amt.getHowSpecified() == OptionalAmount::Constant && *(I++) == '$')
714 os << amt; local
[all...] |
| PrintfFormatString.cpp | 44 const OptionalAmount Amt = ParsePositionAmount(H, Start, Beg, E,
46 if (Amt.isInvalid())
48 FS.setPrecision(Amt);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCFrameLowering.cpp | 474 unsigned Amt = Old.getOperand(0).getImm();
477 if (Amt > AFI->MaxCallStackReq && Old.getOpcode() == ARC::ADJCALLSTACKDOWN)
478 AFI->MaxCallStackReq = Amt;
480 if (Amt != 0) {
485 emitRegUpdate(MBB, I, dl, ARC::SP, Amt, IsAdd, TII);
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 1048 Constant *Amt = ConstantInt::get(VarX->getType(), ShlAmt - ShrAmt);
1049 New = BinaryOperator::CreateShl(VarX, Amt);
1054 Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt);
1055 New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
1056 BinaryOperator::CreateAShr(VarX, Amt);
|
| InstCombineCasts.cpp | 51 // This is a value scaled by '1 << the shift amt'.
145 Value *Amt = nullptr;
147 Amt = NumElements;
149 Amt = ConstantInt::get(AI.getArraySize()->getType(), Scale);
151 Amt = Builder.CreateMul(Amt, NumElements);
157 Amt = Builder.CreateAdd(Amt, Off);
160 AllocaInst *New = Builder.CreateAlloca(CastElTy, Amt);
1125 const APInt *Amt;
[all...] |
| InstCombineCompares.cpp | 2172 unsigned Amt = ShiftAmt->getLimitedValue(TypeBits - 1);
2173 if (Shl->hasOneUse() && Amt != 0 && C.countTrailingZeros() >= Amt &&
2174 DL.isLegalInteger(TypeBits - Amt)) {
2175 Type *TruncTy = IntegerType::get(Cmp.getContext(), TypeBits - Amt);
2179 ConstantInt::get(TruncTy, C.ashr(*ShiftAmt).trunc(TypeBits - Amt));
3573 // 'trunc' or the shift amt in the non-truncated shift should be one-use.
|
| InstructionCombining.cpp | 1409 int32_t Amt = cast<ConstantInt>(BO->getOperand(1))->
1411 // Op = LHS << Amt.
1413 if (Amt == logScale) {
1419 if (Amt < logScale || !Op->hasOneUse())
1425 Op = ConstantInt::get(BO->getType(), Amt - logScale);
|
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| ConstantFold.cpp | 270 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1));
271 if (!Amt)
273 APInt ShAmt = Amt->getValue();
293 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1));
294 if (!Amt)
296 APInt ShAmt = Amt->getValue();
|
| AutoUpgrade.cpp | 1282 Value *Amt = CI.getArgOperand(1);
1287 if (Amt->getType() != Ty) {
1289 Amt = Builder.CreateIntCast(Amt, Ty->getScalarType(), false);
1290 Amt = Builder.CreateVectorSplat(NumElts, Amt);
1295 Value *Res = Builder.CreateCall(Intrin, {Src, Src, Amt});
1349 Value *Amt = CI.getArgOperand(2);
1357 if (Amt->getType() != Ty) {
1359 Amt = Builder.CreateIntCast(Amt, Ty->getScalarType(), false)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 293 SDValue Amt = N->getOperand(1);
294 EVT AmtVT = Amt.getValueType();
295 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
297 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
300 SDValue Amt = N->getOperand(1);
301 EVT AmtVT = Amt.getValueType();
302 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
304 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstCombineIntrinsic.cpp | 201 auto Amt = II.getArgOperand(1);
204 auto AmtVT = Amt->getType();
214 llvm::computeKnownBits(Amt, II.getModule()->getDataLayout());
216 Amt = Builder.CreateZExtOrTrunc(Amt, SVT);
217 Amt = Builder.CreateVectorSplat(VWidth, Amt);
218 return (LogicalShift ? (ShiftLeft ? Builder.CreateShl(Vec, Amt)
219 : Builder.CreateLShr(Vec, Amt))
220 : Builder.CreateAShr(Vec, Amt));
[all...] |
| X86InstrInfo.cpp | 2038 unsigned Amt = MI.getOperand(3).getImm();
2041 WorkingMI.getOperand(3).setImm(Size - Amt);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 2221 const ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
2222 if (!Amt)
2227 Amt->getZExtValue(), Width));
|
| AMDGPURegisterBankInfo.cpp | 2385 int Amt = MI.getOperand(2).getImm();
2386 if (Amt <= 32) {
2387 if (Amt == 32) {
2392 B.buildSExtInReg(DstRegs[0], SrcRegs[0], Amt);
2399 B.buildSExtInReg(DstRegs[1], DstRegs[0], Amt - 32);
|
| AMDGPUISelLowering.cpp | 3255 SDValue Amt = Src.getOperand(1);
3256 KnownBits Known = DAG.computeKnownBits(Amt);
3269 if (Amt.getValueType() != NewShiftVT) {
3270 Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT);
3271 DCI.AddToWorklist(Amt.getNode());
3275 Trunc, Amt);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 219 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
221 if (ARM_AM::getSOImmVal(Amt) == -1)
228 .addImm(Amt)
231 } else if (Amt != 0) {
233 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
253 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
259 .addImm(Amt)
|
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| CGExprScalar.cpp | 2483 llvm::Value *amt = CGF.EmitToMemory( local
2486 Builder.CreateAtomicRMW(aop, LV.getPointer(CGF), amt,
2488 return isPre ? Builder.CreateBinOp(op, old, amt) : old;
2552 Value *amt = llvm::ConstantInt::get(value->getType(), amount, true); local
2553 value = Builder.CreateAdd(value, amt, isInc ? "inc" : "dec");
2569 llvm::Value *amt = llvm::ConstantInt::get(value->getType(), amount, true); local
2570 value = Builder.CreateAdd(value, amt, isInc ? "inc" : "dec");
2591 llvm::Value *amt = Builder.getInt32(amount); local
2595 value = Builder.CreateGEP(value, amt, "incdec.funcptr");
2597 value = CGF.EmitCheckedInBoundsGEP(value, amt, /*SignedIndices=*/false
2604 llvm::Value *amt = Builder.getInt32(amount); local
2616 llvm::Value *amt = llvm::ConstantInt::get(value->getType(), amount); local
2629 llvm::Value *amt; local
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 2249 /// and the shift amount is a constant 'Amt'. Expand the operation.
2250 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
2257 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
2259 if (!Amt) {
2271 if (Amt.ugt(VTBits)) {
2273 } else if (Amt.ugt(NVTBits)) {
2276 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2277 } else if (Amt == NVTBits) {
2281 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
2284 DAG.getConstant(Amt, DL, ShTy))
[all...] |
| TargetLowering.cpp | 1686 unsigned Amt = SA->getAPIntValue().urem(BitWidth);
1690 if (Amt == 0) {
1697 // fshl: (Op0 << Amt) | (Op1 >> (BW - Amt))
1698 // fshr: (Op0 << (BW - Amt)) | (Op1 >> Amt)
1699 APInt Demanded0 = DemandedBits.lshr(IsFSHL ? Amt : (BitWidth - Amt));
1700 APInt Demanded1 = DemandedBits << (IsFSHL ? (BitWidth - Amt) : Amt);
[all...] |
| SelectionDAGBuilder.cpp | 3949 unsigned Amt = ElementMul.logBase2();
3952 DAG.getConstant(Amt, dl, IdxN.getValueType()));
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| LegalizerHelper.cpp | 4349 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
4356 if (Amt.isNullValue()) {
4368 if (Amt.ugt(VTBits)) {
4370 } else if (Amt.ugt(NVTBits)) {
4373 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
4374 } else if (Amt == NVTBits) {
4378 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
4380 MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
4382 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
4386 if (Amt.ugt(VTBits))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 4128 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
10128 unsigned Amt = Inst.getOperand(2).getImm();
10129 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
10131 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
10132 Amt = 0;
10133 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
|
| /src/external/apache2/llvm/dist/clang/lib/Sema/ |
| SemaChecking.cpp | 8188 bool HandleAmount(const analyze_format_string::OptionalAmount &Amt, unsigned k,
8191 const analyze_printf::OptionalAmount &Amt,
8236 const analyze_format_string::OptionalAmount &Amt,
8239 if (Amt.hasDataArgument()) {
8241 unsigned argIndex = Amt.getArgIndex();
8245 getLocationOfByte(Amt.getStart()),
8264 const analyze_printf::ArgType &AT = Amt.getArgType(S.Context);
8271 getLocationOfByte(Amt.getStart()),
8285 const analyze_printf::OptionalAmount &Amt,
8293 Amt.getHowSpecified() == analyze_printf::OptionalAmount::Constan
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 8731 SDValue Amt = Op.getOperand(2);
8732 EVT AmtVT = Amt.getValueType();
8735 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
8736 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
8739 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
8743 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
8760 SDValue Amt = Op.getOperand(2);
8761 EVT AmtVT = Amt.getValueType();
8764 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
8765 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
[all...] |
