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    Searched defs:ArgLocs (Results 1 - 25 of 29) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CallLowering.cpp 518 SmallVector<CCValAssign, 16> ArgLocs;
520 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext());
524 return handleAssignments(Handler, Args, CCInfo, ArgLocs, MIRBuilder,
610 SmallVectorImpl<CCValAssign> &ArgLocs,
621 assert(j < ArgLocs.size() && "Skipped too many arg locs");
622 CCValAssign &VA = ArgLocs[j];
627 Handler.assignCustomValue(Args[i], makeArrayRef(ArgLocs).slice(j));
644 // There should be Regs.size() ArgLocs per argument.
663 assert((j + (NumParts - 1)) < ArgLocs.size() &&
675 // There should be Regs.size() ArgLocs per argument
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64CallLowering.cpp 482 SmallVector<CCValAssign, 16> ArgLocs;
483 CCState CCInfo(F.getCallingConv(), /*IsVarArg=*/true, MF, ArgLocs,
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCISelLowering.cpp 237 SmallVector<CCValAssign, 16> ArgLocs;
238 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
261 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
262 CCValAssign &VA = ArgLocs[i];
455 SmallVector<CCValAssign, 16> ArgLocs;
456 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
478 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
479 CCValAssign &VA = ArgLocs[i];
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelLowering.cpp 315 SmallVector<CCValAssign, 16> ArgLocs;
316 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
319 for (auto &VA : ArgLocs) {
393 SmallVector<CCValAssign, 16> ArgLocs;
394 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
418 e = std::min(static_cast<unsigned>(ArgLocs.size()), MaxArgs);
420 CCValAssign &VA = ArgLocs[i];
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsCallLowering.cpp 40 ArrayRef<CCValAssign> ArgLocs,
44 if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT))
56 ArrayRef<CCValAssign> ArgLocs, ArrayRef<CallLowering::ArgInfo> Args) {
78 if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0],
82 if (!assign(Args[ArgsIndex].Regs[0], ArgLocs[ArgLocsIndex], VT))
106 ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
203 ArrayRef<CCValAssign> ArgLocs,
206 if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
230 ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
314 ArrayRef<CCValAssign> ArgLocs,
    [all...]
MipsFastISel.cpp 1140 SmallVector<CCValAssign, 16> ArgLocs;
1141 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1152 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1153 CCValAssign &VA = ArgLocs[i];
MipsISelLowering.cpp 3159 SmallVector<CCValAssign, 16> ArgLocs;
3161 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
3252 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3254 CCValAssign &VA = ArgLocs[i];
3619 SmallVector<CCValAssign, 16> ArgLocs;
3620 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3637 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3638 CCValAssign &VA = ArgLocs[i];
3725 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 273 SmallVector<CCValAssign, 16> ArgLocs;
275 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
500 SmallVector<CCValAssign, 16> ArgLocs;
501 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
590 SmallVector<CCValAssign, 16> ArgLocs;
591 CCState CCInfo(CC, F.isVarArg(), MF, ArgLocs, F.getContext());
718 if (!handleAssignments(Handler, SplitArgs, CCInfo, ArgLocs, B))
1181 SmallVector<CCValAssign, 16> ArgLocs;
1182 CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext());
1203 if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder)
    [all...]
R600ISelLowering.cpp 1493 SmallVector<CCValAssign, 16> ArgLocs;
1494 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1506 CCValAssign &VA = ArgLocs[i];
SIISelLowering.cpp 2276 SmallVector<CCValAssign, 16> ArgLocs;
2278 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2370 CCValAssign &VA = ArgLocs[ArgIdx++];
2906 SmallVector<CCValAssign, 16> ArgLocs;
2907 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
2919 return parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals);
3010 SmallVector<CCValAssign, 16> ArgLocs;
3011 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
3059 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3060 CCValAssign &VA = ArgLocs[i]
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 447 SmallVector<CCValAssign, 16> ArgLocs;
448 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
456 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
457 CCValAssign &VA = ArgLocs[i];
603 SmallVector<CCValAssign, 16> ArgLocs;
604 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
657 for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
658 CCValAssign &VA = ArgLocs[I];
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 456 SmallVectorImpl<CCValAssign> &ArgLocs,
627 SmallVector<CCValAssign, 16> ArgLocs;
628 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
630 AnalyzeArguments(CCInfo, ArgLocs, Ins);
638 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
639 CCValAssign &VA = ArgLocs[i];
706 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
810 SmallVector<CCValAssign, 16> ArgLocs;
811 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
813 AnalyzeArguments(CCInfo, ArgLocs, Outs)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 1013 SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) {
1133 SmallVector<CCValAssign, 16> ArgLocs;
1134 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1141 analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo);
1145 for (CCValAssign &VA : ArgLocs) {
1242 SmallVector<CCValAssign, 16> ArgLocs;
1243 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1266 analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo);
1279 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1280 CCValAssign &VA = ArgLocs[AI]
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 1380 SmallVector<CCValAssign, 16> ArgLocs;
1381 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1390 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1391 CCValAssign &VA = ArgLocs[I];
1428 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1429 CCValAssign &VA = ArgLocs[I];
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 966 SmallVector<CCValAssign, 16> ArgLocs;
967 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
982 CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(),
1000 assert(ArgLocs[ValNo].getValNo() == ValNo &&
1001 "ArgLocs should remain in order and only hold varargs args");
1002 unsigned Offset = ArgLocs[ValNo++].getLocMemOffset();
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 1114 SmallVector<CCValAssign, 16> ArgLocs;
1115 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1141 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1142 CCValAssign &VA = ArgLocs[i];
1269 SmallVector<CCValAssign, 16> ArgLocs;
1270 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1294 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1296 CCValAssign &VA = ArgLocs[i];
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 2995 SmallVector<CCValAssign, 16> ArgLocs;
2996 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
3008 for (CCValAssign &VA : ArgLocs) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFastISel.cpp 1879 SmallVector<CCValAssign, 16> ArgLocs;
1880 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1886 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1887 CCValAssign &VA = ArgLocs[i];
1901 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1936 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1937 CCValAssign &VA = ArgLocs[i];
1984 // FIXME: ArgLocs[++i] may extend beyond ArgLocs.size()
1985 CCValAssign &NextVA = ArgLocs[++i]
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 426 SmallVector<CCValAssign, 16> ArgLocs;
427 HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs, *DAG.getContext(),
442 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
443 CCValAssign &VA = ArgLocs[i];
465 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
466 CCValAssign &VA = ArgLocs[i];
788 SmallVector<CCValAssign, 16> ArgLocs;
789 HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs,
825 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
826 CCValAssign &VA = ArgLocs[i]
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 521 SmallVector<CCValAssign, 16> ArgLocs;
524 M68kCCState CCInfo(*CalleeFunc, CallConv, IsVarArg, MF, ArgLocs,
560 if (!ArgLocs.back().isMemLoc())
563 if (ArgLocs.back().getLocMemOffset() != 0)
584 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
591 CCValAssign &VA = ArgLocs[i];
669 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
670 CCValAssign &VA = ArgLocs[i];
878 SmallVector<CCValAssign, 16> ArgLocs;
879 M68kCCState CCInfo(MF.getFunction(), CCID, IsVarArg, MF, ArgLocs,
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 390 SmallVector<CCValAssign, 16> ArgLocs;
391 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
399 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
400 CCValAssign &VA = ArgLocs[i];
423 CCValAssign &NextVA = ArgLocs[++i];
583 SmallVector<CCValAssign, 16> ArgLocs;
584 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
591 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
592 CCValAssign &VA = ArgLocs[i];
732 SmallVector<CCValAssign, 16> ArgLocs;
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 404 SmallVector<CCValAssign, 16> ArgLocs;
405 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
413 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
414 CCValAssign &VA = ArgLocs[i];
498 unsigned ArgOffset = ArgLocs.size() * 8;
548 SmallVector<CCValAssign, 16> ArgLocs;
549 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
637 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
638 CCValAssign &VA = ArgLocs[i];
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FastISel.cpp 3284 SmallVector<CCValAssign, 16> ArgLocs;
3285 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, CLI.RetTy->getContext());
3303 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3304 CCValAssign const &VA = ArgLocs[i];
  /src/external/apache2/llvm/dist/clang/lib/Sema/
SemaTemplateInstantiateDecl.cpp 3500 SmallVector<TemplateArgumentLoc, 4> ArgLocs;
3502 ArgLocs.push_back(Loc.getArgLoc(I));
3503 if (SemaRef.Subst(ArgLocs.data(), ArgLocs.size(),
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 1389 SmallVector<CCValAssign, 16> ArgLocs;
1390 SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1395 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1397 CCValAssign &VA = ArgLocs[I];
1463 CCValAssign &PartVA = ArgLocs[I + 1];
1518 SmallVectorImpl<CCValAssign> &ArgLocs,
1523 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1524 CCValAssign &VA = ArgLocs[I];
1562 SmallVector<CCValAssign, 16> ArgLocs;
1563 SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, Ctx)
    [all...]

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