| /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| AssumeBundleQueries.h | 96 /// ArgValue is optionally an argument of the attribute.
100 /// - ArgValue will be 4.
103 unsigned ArgValue = 0;
107 ArgValue == Other.ArgValue;
111 /// only differ in ArgValue.
117 return ArgValue < Other.ArgValue;
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| AssumeBundleBuilder.cpp | 80 RK.ArgValue =
81 MinAlign(RK.ArgValue, GEP->getMaxPreservedAlignment(DL).value());
93 RK.ArgValue = RK.ArgValue + Offset;
126 if (RKOther.ArgValue >= RK.ArgValue) {
139 ConstantInt::get(Type::getInt64Ty(M->getContext()), RK.ArgValue));
156 Arg->getAttribute(RK.AttrKind).getValueAsInt() >= RK.ArgValue))
182 AssumedKnowledgeMap[Key] = RK.ArgValue;
185 assert(((Lookup->second == 0 && RK.ArgValue == 0) |
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/ASTMatchers/Dynamic/ |
| Parser.cpp | 501 ParserValue ArgValue;
517 ArgValue.Text = NodeMatcherToken.Text;
518 ArgValue.Range = NodeMatcherToken.Range;
521 S->lookupMatcherCtor(ArgValue.Text);
539 ArgValue.Value = NK;
542 Args.push_back(ArgValue);
669 ParserValue ArgValue;
671 ArgValue.Text = Tokenizer->peekNextToken().Text;
672 ArgValue.Range = Tokenizer->peekNextToken().Range;
673 if (!parseExpressionImpl(&ArgValue.Value))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 335 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
340 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
343 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
347 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
349 InVals.push_back(ArgValue);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
478 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
480 InVals.push_back(ArgValue);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 655 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
661 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
664 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
668 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
670 InVals.push_back(ArgValue);
|
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| CGExprAgg.cpp | 1280 Address ArgValue = Address::invalid();
1281 Address ArgPtr = CGF.EmitVAArg(VE, ArgValue);
|
| CGExprComplex.cpp | 1099 Address ArgValue = Address::invalid();
1100 Address ArgPtr = CGF.EmitVAArg(E, ArgValue);
|
| CGExprCXX.cpp | 1401 RValueTy ArgValue;
1475 DeleteArgs.add(Traits::get(CGF, Arg.ArgValue), Arg.ArgType);
|
| CGExprScalar.cpp | 4652 Address ArgValue = Address::invalid();
4653 Address ArgPtr = CGF.EmitVAArg(VE, ArgValue);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 1144 SDValue ArgValue;
1160 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1174 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1177 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1179 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1182 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 885 SDValue ArgValue;
901 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
907 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
910 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
913 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
917 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 3671 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3673 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3680 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3687 std::swap(ArgValue, ArgValue2);
3688 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3689 ArgValue, ArgValue2);
3692 InVals.push_back(ArgValue);
3714 SDValue ArgValue = DAG.getLoad
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 1396 SDValue ArgValue;
1434 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
1449 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
1456 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
1465 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
1472 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
1503 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
1504 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
1584 SDValue ArgValue = OutVals[I]
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/Sema/ |
| SemaDeclAttr.cpp | 645 llvm::APInt ArgValue = IL->getValue();
646 uint64_t ParamIdxFromOne = ArgValue.getZExtValue();
648 if (!ArgValue.isStrictlyPositive() || ParamIdxFromOne > NumParams) {
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 10201 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT,
10210 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 1732 SDValue ArgValue;
1755 ArgValue = DAG.getExtLoad(
1759 return ArgValue;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 7260 SDValue ArgValue;
7264 ArgValue = unpackF64OnRV32DSoftABI(DAG, Chain, VA, DL);
7266 ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL, *this);
7268 ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
7276 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
7284 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
7292 InVals.push_back(ArgValue);
7337 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);
7340 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
7513 SDValue ArgValue = OutVals[i]
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 4044 SDValue ArgValue;
4055 ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo,
4059 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
4062 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
4065 InVals.push_back(ArgValue);
6767 SelectionDAG &DAG, SDValue ArgValue,
6773 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
6776 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 4881 SDValue ArgValue;
4909 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
4924 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
4931 ArgValue = DAG.getNode(ISD::SRL, DL, RegVT, ArgValue,
4933 ArgValue = DAG.getZExtOrTrunc(ArgValue, DL, VA.getValVT());
4980 ArgValue = DAG.getExtLoad(
5000 SDValue Ptr = ArgValue;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 4109 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4126 std::swap (ArgValue, ArgValue2);
4127 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4264 SDValue ArgValue;
4336 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4337 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4339 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4342 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl)
[all...] |
