1 /* Definition of RISC-V target for GNU compiler. 2 Copyright (C) 2011-2024 Free Software Foundation, Inc. 3 Contributed by Andrew Waterman (andrew (at) sifive.com). 4 Based on MIPS target for GNU compiler. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #ifndef GCC_RISCV_H 23 #define GCC_RISCV_H 24 25 #include <stdbool.h> 26 #include "config/riscv/riscv-opts.h" 27 28 #define SWITCHABLE_TARGET 1 29 30 /* Target CPU builtins. */ 31 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile) 32 33 #ifdef TARGET_BIG_ENDIAN_DEFAULT 34 #define DEFAULT_ENDIAN_SPEC "b" 35 #else 36 #define DEFAULT_ENDIAN_SPEC "l" 37 #endif 38 39 /* Default target_flags if no switches are specified */ 40 41 #ifndef TARGET_DEFAULT 42 #define TARGET_DEFAULT 0 43 #endif 44 45 #ifndef RISCV_TUNE_STRING_DEFAULT 46 #define RISCV_TUNE_STRING_DEFAULT "rocket" 47 #endif 48 49 extern const char *riscv_expand_arch (int argc, const char **argv); 50 extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv); 51 extern const char *riscv_default_mtune (int argc, const char **argv); 52 extern const char *riscv_multi_lib_check (int argc, const char **argv); 53 extern const char *riscv_arch_help (int argc, const char **argv); 54 55 # define EXTRA_SPEC_FUNCTIONS \ 56 { "riscv_expand_arch", riscv_expand_arch }, \ 57 { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, \ 58 { "riscv_default_mtune", riscv_default_mtune }, \ 59 { "riscv_multi_lib_check", riscv_multi_lib_check }, \ 60 { "riscv_arch_help", riscv_arch_help }, 61 62 /* Support for a compile-time default CPU, et cetera. The rules are: 63 --with-arch is ignored if -march or -mcpu is specified. 64 --with-abi is ignored if -mabi is specified. 65 --with-tune is ignored if -mtune or -mcpu is specified. 66 --with-isa-spec is ignored if -misa-spec is specified. 67 --with-tls is ignored if -mtls-dialect is specified. 68 69 But using default -march/-mtune value if -mcpu don't have valid option. */ 70 #define OPTION_DEFAULT_SPECS \ 71 {"tune", "%{!mtune=*:" \ 72 " %{!mcpu=*:-mtune=%(VALUE)}" \ 73 " %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" }, \ 74 {"arch", "%{!march=*:" \ 75 " %{!mcpu=*:-march=%(VALUE)}" \ 76 " %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" }, \ 77 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ 78 {"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \ 79 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, \ 80 81 #ifdef IN_LIBGCC2 82 #undef TARGET_64BIT 83 /* Make this compile time constant for libgcc2 */ 84 #define TARGET_64BIT (__riscv_xlen == 64) 85 #endif /* IN_LIBGCC2 */ 86 87 #ifdef HAVE_AS_MISA_SPEC 88 #define ASM_MISA_SPEC "%{misa-spec=*}" 89 #else 90 #define ASM_MISA_SPEC "" 91 #endif 92 93 /* Reference: 94 https://gcc.gnu.org/onlinedocs/cpp/Stringizing.html#Stringizing */ 95 #define STRINGIZING(s) __STRINGIZING(s) 96 #define __STRINGIZING(s) #s 97 98 #define MULTILIB_DEFAULTS \ 99 {"march=" STRINGIZING (TARGET_RISCV_DEFAULT_ARCH), \ 100 "mabi=" STRINGIZING (TARGET_RISCV_DEFAULT_ABI) } 101 102 #undef ASM_SPEC 103 #define ASM_SPEC "\ 104 %(subtarget_asm_debugging_spec) \ 105 %{" FPIE_OR_FPIC_SPEC ":-fpic} \ 106 %{march=*} \ 107 %{mabi=*} \ 108 %{mno-relax} \ 109 %{mbig-endian} \ 110 %{mlittle-endian} \ 111 %(subtarget_asm_spec)" \ 112 ASM_MISA_SPEC 113 114 #undef DRIVER_SELF_SPECS 115 #define DRIVER_SELF_SPECS \ 116 "%{march=help:%:riscv_arch_help()} " \ 117 "%{print-supported-extensions:%:riscv_arch_help()} " \ 118 "%{-print-supported-extensions:%:riscv_arch_help()} " \ 119 "%{march=*:%:riscv_expand_arch(%*)} " \ 120 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} " 121 122 #define TARGET_DEFAULT_CMODEL CM_MEDLOW 123 124 #define LOCAL_LABEL_PREFIX "." 125 #define USER_LABEL_PREFIX "" 126 127 /* Offsets recorded in opcodes are a multiple of this alignment factor. 128 The default for this in 64-bit mode is 8, which causes problems with 129 SFmode register saves. */ 130 #define DWARF_CIE_DATA_ALIGNMENT -4 131 132 /* The mapping from gcc register number to DWARF 2 CFA column number. */ 133 #define DWARF_FRAME_REGNUM(REGNO) \ 134 (FRM_REG_P (REGNO) ? RISCV_DWARF_FRM \ 135 : VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM \ 136 : VL_REG_P (REGNO) ? RISCV_DWARF_VL \ 137 : VTYPE_REG_P (REGNO) \ 138 ? RISCV_DWARF_VTYPE \ 139 : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO) \ 140 ? REGNO \ 141 : INVALID_REGNUM)) 142 143 /* The DWARF 2 CFA column which tracks the return address. */ 144 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM 145 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM) 146 147 /* Describe how we implement __builtin_eh_return. */ 148 #define EH_RETURN_DATA_REGNO(N) \ 149 ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 150 151 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4) 152 153 /* Target machine storage layout */ 154 155 #define BITS_BIG_ENDIAN 0 156 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 157 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 158 159 #define MAX_BITS_PER_WORD 64 160 161 /* Width of a word, in units (bytes). */ 162 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 163 #define BITS_PER_WORD (BITS_PER_UNIT * UNITS_PER_WORD) 164 #ifndef IN_LIBGCC2 165 #define MIN_UNITS_PER_WORD 4 166 #endif 167 168 /* Allows SImode op in builtin overflow pattern, see internal-fn.cc. */ 169 #undef TARGET_MIN_ARITHMETIC_PRECISION 170 #define TARGET_MIN_ARITHMETIC_PRECISION riscv_min_arithmetic_precision 171 172 /* The `Q' extension is not yet supported. */ 173 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) 174 /* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */ 175 #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk) 176 177 /* The largest type that can be passed in floating-point registers. */ 178 #define UNITS_PER_FP_ARG \ 179 ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E \ 180 || riscv_abi == ABI_LP64 || riscv_abi == ABI_LP64E) \ 181 ? 0 \ 182 : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8)) 183 184 /* Set the sizes of the core types. */ 185 #define SHORT_TYPE_SIZE 16 186 #define INT_TYPE_SIZE 32 187 #define LONG_LONG_TYPE_SIZE 64 188 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32) 189 #define LONG_TYPE_SIZE POINTER_SIZE 190 191 #define FLOAT_TYPE_SIZE 32 192 #define DOUBLE_TYPE_SIZE 64 193 #define LONG_DOUBLE_TYPE_SIZE 128 194 195 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 196 #define PARM_BOUNDARY BITS_PER_WORD 197 198 /* Allocation boundary (in *bits*) for the code of a function. */ 199 #define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32) 200 201 /* The smallest supported stack boundary the calling convention supports. */ 202 #define STACK_BOUNDARY \ 203 (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \ 204 ? BITS_PER_WORD \ 205 : 2 * BITS_PER_WORD) 206 207 /* The ABI stack alignment. */ 208 #define ABI_STACK_BOUNDARY \ 209 (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \ 210 ? BITS_PER_WORD \ 211 : 128) 212 213 /* There is no point aligning anything to a rounder boundary than this. */ 214 #define BIGGEST_ALIGNMENT 128 215 216 /* The user-level ISA permits unaligned accesses, but they are not required 217 of the privileged architecture. */ 218 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 219 220 /* Define this if you wish to imitate the way many other C compilers 221 handle alignment of bitfields and the structures that contain 222 them. 223 224 The behavior is that the type written for a bit-field (`int', 225 `short', or other integer type) imposes an alignment for the 226 entire structure, as if the structure really did contain an 227 ordinary field of that type. In addition, the bit-field is placed 228 within the structure so that it would fit within such a field, 229 not crossing a boundary for it. 230 231 Thus, on most machines, a bit-field whose type is written as `int' 232 would not cross a four-byte boundary, and would force four-byte 233 alignment for the whole structure. (The alignment used may not 234 be four bytes; it is controlled by the other alignment 235 parameters.) 236 237 If the macro is defined, its definition should be a C expression; 238 a nonzero value for the expression enables this behavior. */ 239 240 #define PCC_BITFIELD_TYPE_MATTERS 1 241 242 /* An integer expression for the size in bits of the largest integer machine 243 mode that should actually be used. We allow pairs of registers. */ 244 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 245 246 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition. */ 247 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN) \ 248 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 249 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 250 || TREE_CODE (TYPE) == UNION_TYPE \ 251 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 252 253 /* If defined, a C expression to compute the alignment for a static 254 variable. TYPE is the data type, and ALIGN is the alignment that 255 the object would ordinarily have. The value of this macro is used 256 instead of that alignment to align the object. 257 258 If this macro is not defined, then ALIGN is used. 259 260 One use of this macro is to increase alignment of medium-size 261 data to make it all fit in fewer cache lines. Another is to 262 cause character arrays to be word-aligned so that `strcpy' calls 263 that copy constants to character arrays can be done inline. */ 264 265 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 266 RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen, \ 267 TYPE, ALIGN) 268 269 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause 270 character arrays to be word-aligned so that `strcpy' calls that copy 271 constants to character arrays can be done inline, and 'strcmp' can be 272 optimised to use word loads. */ 273 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 274 RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN) 275 276 /* Define if operations between registers always perform the operation 277 on the full register even if a narrower mode is specified. */ 278 #define WORD_REGISTER_OPERATIONS 1 279 280 /* When in 64-bit mode, move insns will sign extend SImode and CCmode 281 moves. All other references are zero extended. */ 282 #define LOAD_EXTEND_OP(MODE) \ 283 (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) 284 285 /* Define this macro if it is advisable to hold scalars in registers 286 in a wider mode than that declared by the program. In such cases, 287 the value is constrained to be within the bounds of the declared 288 type, but kept valid in the wider mode. The signedness of the 289 extension may differ from that of the type. */ 290 291 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 292 if (GET_MODE_CLASS (MODE) == MODE_INT \ 293 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 294 { \ 295 if ((MODE) == SImode) \ 296 (UNSIGNEDP) = 0; \ 297 (MODE) = word_mode; \ 298 } 299 300 /* Pmode is always the same as ptr_mode, but not always the same as word_mode. 301 Extensions of pointers to word_mode must be signed. */ 302 #define POINTERS_EXTEND_UNSIGNED false 303 304 /* Define if loading short immediate values into registers sign extends. */ 305 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 306 307 /* Standard register usage. */ 308 309 /* Number of hardware registers. We have: 310 311 - 32 integer registers 312 - 32 floating point registers 313 - 2 fake registers: 314 - ARG_POINTER_REGNUM 315 - FRAME_POINTER_REGNUM 316 - 1 vl register 317 - 1 vtype register 318 - 30 unused registers for future expansion 319 - 32 vector registers */ 320 321 #define FIRST_PSEUDO_REGISTER 128 322 323 /* x0, sp, gp, and tp are fixed. */ 324 325 #define FIXED_REGISTERS \ 326 { /* General registers. */ \ 327 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 328 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 329 /* Floating-point registers. */ \ 330 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 331 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 332 /* Others. */ \ 333 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 334 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 335 /* Vector registers. */ \ 336 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 337 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ 338 } 339 340 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls. 341 The call RTLs themselves clobber ra. */ 342 343 #define CALL_USED_REGISTERS \ 344 { /* General registers. */ \ 345 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \ 346 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ 347 /* Floating-point registers. */ \ 348 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \ 349 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ 350 /* Others. */ \ 351 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 352 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 353 /* Vector registers. */ \ 354 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 355 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ 356 } 357 358 /* Select a register mode required for caller save of hard regno REGNO. 359 Contrary to what is documented, the default is not the smallest suitable 360 mode but the largest suitable mode for the given (REGNO, NREGS) pair and 361 it quickly creates paradoxical subregs that can be problematic. */ 362 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 363 ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE)) 364 365 /* Internal macros to classify an ISA register's type. */ 366 367 #define GP_REG_FIRST 0 368 #define GP_REG_LAST (TARGET_RVE ? 15 : 31) 369 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 370 371 #define FP_REG_FIRST 32 372 #define FP_REG_LAST 63 373 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 374 375 #define V_REG_FIRST 96 376 #define V_REG_LAST 127 377 #define V_REG_NUM (V_REG_LAST - V_REG_FIRST + 1) 378 379 /* The DWARF 2 CFA column which tracks the return address from a 380 signal handler context. This means that to maintain backwards 381 compatibility, no hard register can be assigned this column if it 382 would need to be handled by the DWARF unwinder. */ 383 #define DWARF_ALT_FRAME_RETURN_COLUMN 64 384 385 #define GP_REG_P(REGNO) \ 386 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 387 #define FP_REG_P(REGNO) \ 388 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) 389 #define HARDFP_REG_P(REGNO) \ 390 ((REGNO) >= FP_REG_FIRST && (REGNO) <= FP_REG_LAST) 391 #define V_REG_P(REGNO) \ 392 ((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM) 393 #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM) 394 #define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM) 395 #define VXRM_REG_P(REGNO) ((REGNO) == VXRM_REGNUM) 396 #define FRM_REG_P(REGNO) ((REGNO) == FRM_REGNUM) 397 398 /* True when REGNO is in SIBCALL_REGS set. */ 399 #define SIBCALL_REG_P(REGNO) \ 400 TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO) 401 402 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) 403 404 /* Use s0 as the frame pointer if it is so requested. */ 405 #define HARD_FRAME_POINTER_REGNUM 8 406 #define STACK_POINTER_REGNUM 2 407 #define THREAD_POINTER_REGNUM 4 408 409 /* These two registers don't really exist: they get eliminated to either 410 the stack or hard frame pointer. */ 411 #define ARG_POINTER_REGNUM 64 412 #define FRAME_POINTER_REGNUM 65 413 414 /* Define Dwarf for RVV. */ 415 #define RISCV_DWARF_FRM (4096 + 0x003) 416 #define RISCV_DWARF_VXRM (4096 + 0x00a) 417 #define RISCV_DWARF_VL (4096 + 0xc20) 418 #define RISCV_DWARF_VTYPE (4096 + 0xc21) 419 #define RISCV_DWARF_VLENB (4096 + 0xc22) 420 421 /* Register in which static-chain is passed to a function. */ 422 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2) 423 424 /* Registers used as temporaries in prologue/epilogue code. 425 426 The prologue registers mustn't conflict with any 427 incoming arguments, the static chain pointer, or the frame pointer. 428 The epilogue temporary mustn't conflict with the return registers, 429 the frame pointer, the EH stack adjustment, or the EH data registers. */ 430 431 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST) 432 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM) 433 #define RISCV_PROLOGUE_TEMP2_REGNUM (GP_TEMP_FIRST + 1) 434 #define RISCV_PROLOGUE_TEMP2(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP2_REGNUM) 435 436 #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1) 437 #define RISCV_CALL_ADDRESS_TEMP(MODE) \ 438 gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM) 439 440 #define RETURN_ADDR_MASK (1 << RETURN_ADDR_REGNUM) 441 #define S0_MASK (1 << S0_REGNUM) 442 #define S1_MASK (1 << S1_REGNUM) 443 #define S2_MASK (1 << S2_REGNUM) 444 #define S3_MASK (1 << S3_REGNUM) 445 #define S4_MASK (1 << S4_REGNUM) 446 #define S5_MASK (1 << S5_REGNUM) 447 #define S6_MASK (1 << S6_REGNUM) 448 #define S7_MASK (1 << S7_REGNUM) 449 #define S8_MASK (1 << S8_REGNUM) 450 #define S9_MASK (1 << S9_REGNUM) 451 #define S10_MASK (1 << S10_REGNUM) 452 #define S11_MASK (1 << S11_REGNUM) 453 454 #define MULTI_PUSH_GPR_MASK \ 455 (RETURN_ADDR_MASK | S0_MASK | S1_MASK | S2_MASK | S3_MASK | S4_MASK \ 456 | S5_MASK | S6_MASK | S7_MASK | S8_MASK | S9_MASK | S10_MASK | S11_MASK) 457 #define ZCMP_MAX_SPIMM 3 458 #define ZCMP_SP_INC_STEP 16 459 #define ZCMP_INVALID_S0S10_SREGS_COUNTS 11 460 #define ZCMP_S0S11_SREGS_COUNTS 12 461 #define ZCMP_MAX_GRP_SLOTS 13 462 463 #define MCOUNT_NAME "_mcount" 464 465 #define NO_PROFILE_COUNTERS 1 466 467 /* Emit rtl for profiling. Output assembler code to FILE 468 to call "_mcount" for profiling a function entry. */ 469 #define PROFILE_HOOK(LABEL) \ 470 { \ 471 rtx fun, ra; \ 472 ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \ 473 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 474 emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \ 475 } 476 477 /* All the work done in PROFILE_HOOK, but still required. */ 478 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 479 480 /* Define this macro if it is as good or better to call a constant 481 function address than to call an address kept in a register. */ 482 #define NO_FUNCTION_CSE 1 483 484 /* Define the classes of registers for register constraints in the 485 machine description. Also define ranges of constants. 486 487 One of the classes must always be named ALL_REGS and include all hard regs. 488 If there is more than one class, another class must be named NO_REGS 489 and contain no registers. 490 491 The name GENERAL_REGS must be the name of a class (or an alias for 492 another name such as ALL_REGS). This is the class of registers 493 that is allowed by "g" or "r" in a register constraint. 494 Also, registers outside this class are allocated only when 495 instructions express preferences for them. 496 497 The classes must be numbered in nondecreasing order; that is, 498 a larger-numbered class must never be contained completely 499 in a smaller-numbered class. 500 501 For any two classes, it is very desirable that there be another 502 class that represents their union. */ 503 504 enum reg_class 505 { 506 NO_REGS, /* no registers in set */ 507 SIBCALL_REGS, /* registers used by indirect sibcalls */ 508 JALR_REGS, /* registers used by indirect calls */ 509 GR_REGS, /* integer registers */ 510 FP_REGS, /* floating-point registers */ 511 FRAME_REGS, /* arg pointer and frame pointer */ 512 VM_REGS, /* v0.t registers */ 513 VD_REGS, /* vector registers except v0.t */ 514 V_REGS, /* vector registers */ 515 ALL_REGS, /* all registers */ 516 LIM_REG_CLASSES /* max value + 1 */ 517 }; 518 519 #define N_REG_CLASSES (int) LIM_REG_CLASSES 520 521 #define GENERAL_REGS GR_REGS 522 523 /* An initializer containing the names of the register classes as C 524 string constants. These names are used in writing some of the 525 debugging dumps. */ 526 527 #define REG_CLASS_NAMES \ 528 { \ 529 "NO_REGS", \ 530 "SIBCALL_REGS", \ 531 "JALR_REGS", \ 532 "GR_REGS", \ 533 "FP_REGS", \ 534 "FRAME_REGS", \ 535 "VM_REGS", \ 536 "VD_REGS", \ 537 "V_REGS", \ 538 "ALL_REGS" \ 539 } 540 541 /* An initializer containing the contents of the register classes, 542 as integers which are bit masks. The Nth integer specifies the 543 contents of class N. The way the integer MASK is interpreted is 544 that register R is in the class if `MASK & (1 << R)' is 1. 545 546 When the machine has more than 32 registers, an integer does not 547 suffice. Then the integers are replaced by sub-initializers, 548 braced groupings containing several integers. Each 549 sub-initializer must be suitable as an initializer for the type 550 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ 551 552 #define REG_CLASS_CONTENTS \ 553 { \ 554 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 555 { 0xf003fcc0, 0x00000000, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ 556 { 0xffffffc0, 0x00000000, 0x00000000, 0x00000000 }, /* JALR_REGS */ \ 557 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ 558 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FP_REGS */ \ 559 { 0x00000000, 0x00000000, 0x00000003, 0x00000000 }, /* FRAME_REGS */ \ 560 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, /* V0_REGS */ \ 561 { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe }, /* VNoV0_REGS */ \ 562 { 0x00000000, 0x00000000, 0x00000000, 0xffffffff }, /* V_REGS */ \ 563 { 0xffffffff, 0xffffffff, 0x00000003, 0xffffffff } /* ALL_REGS */ \ 564 } 565 566 /* A C expression whose value is a register class containing hard 567 register REGNO. In general there is more that one such class; 568 choose a class which is "minimal", meaning that no smaller class 569 also contains the register. */ 570 571 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ] 572 573 /* A macro whose definition is the name of the class to which a 574 valid base register must belong. A base register is one used in 575 an address which is the register value plus a displacement. */ 576 577 #define BASE_REG_CLASS GR_REGS 578 579 /* A macro whose definition is the name of the class to which a 580 valid index register must belong. An index register is one used 581 in an address where its value is either multiplied by a scale 582 factor or added to another register (as well as added to a 583 displacement). */ 584 585 #define INDEX_REG_CLASS riscv_index_reg_class() 586 587 /* We generally want to put call-clobbered registers ahead of 588 call-saved ones. (IRA expects this.) */ 589 590 #define REG_ALLOC_ORDER \ 591 { \ 592 /* Call-clobbered GPRs. */ \ 593 15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1, \ 594 /* Call-saved GPRs. */ \ 595 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \ 596 /* GPRs that can never be exposed to the register allocator. */ \ 597 0, 2, 3, 4, \ 598 /* Call-clobbered FPRs. */ \ 599 47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49, \ 600 60, 61, 62, 63, \ 601 /* Call-saved FPRs. */ \ 602 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ 603 /* v1 ~ v31 vector registers. */ \ 604 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, \ 605 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \ 606 124, 125, 126, 127, \ 607 /* The vector mask register. */ \ 608 96, \ 609 /* None of the remaining classes have defined call-saved \ 610 registers. */ \ 611 64, 65, 66, 67 \ 612 } 613 614 /* True if VALUE is a signed 12-bit number. */ 615 616 #define SMALL_OPERAND(VALUE) \ 617 ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH) 618 619 #define POLY_SMALL_OPERAND_P(POLY_VALUE) \ 620 (POLY_VALUE.is_constant () ? \ 621 SMALL_OPERAND (POLY_VALUE.to_constant ()) : false) 622 623 /* True if VALUE can be loaded into a register using LUI. */ 624 625 #define LUI_OPERAND(VALUE) \ 626 (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \ 627 || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0) 628 629 /* If this is a single bit mask, then we can load it with bseti. Special 630 handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */ 631 #define SINGLE_BIT_MASK_OPERAND(VALUE) \ 632 (pow2p_hwi (TARGET_64BIT \ 633 ? (VALUE) \ 634 : ((VALUE) & ((HOST_WIDE_INT_1U << 32)-1)))) 635 636 /* True if VALUE can be represented as an immediate with 1 extra bit 637 set: we check that it is not a SMALL_OPERAND (as this would be true 638 for all small operands) unmodified and turns into a small operand 639 once we clear the top bit. */ 640 #define UIMM_EXTRA_BIT_OPERAND(VALUE) \ 641 (!SMALL_OPERAND (VALUE) \ 642 && SMALL_OPERAND (VALUE & ~(HOST_WIDE_INT_1U << floor_log2 (VALUE)))) 643 644 /* True if bit BIT is set in VALUE. */ 645 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0) 646 647 /* Stack layout; function entry, exit and calling. */ 648 649 #define STACK_GROWS_DOWNWARD 1 650 651 #define FRAME_GROWS_DOWNWARD 1 652 653 #define RETURN_ADDR_RTX riscv_return_addr 654 655 #define ELIMINABLE_REGS \ 656 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 657 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 658 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 659 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 660 661 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 662 (OFFSET) = riscv_initial_elimination_offset (FROM, TO) 663 664 /* Allocate stack space for arguments at the beginning of each function. */ 665 #define ACCUMULATE_OUTGOING_ARGS 1 666 667 /* The argument pointer always points to the first argument. */ 668 #define FIRST_PARM_OFFSET(FNDECL) 0 669 670 #define REG_PARM_STACK_SPACE(FNDECL) 0 671 672 /* Define this if it is the responsibility of the caller to 673 allocate the area reserved for arguments passed in registers. 674 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 675 of this macro is to determine whether the space is included in 676 `crtl->outgoing_args_size'. */ 677 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 678 679 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary 680 681 /* Symbolic macros for the registers used to return integer and floating 682 point values. */ 683 684 #define GP_RETURN GP_ARG_FIRST 685 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST) 686 #define V_RETURN V_REG_FIRST 687 688 #define GP_RETURN_FIRST GP_ARG_FIRST 689 #define GP_RETURN_LAST GP_ARG_FIRST + 1 690 #define FP_RETURN_FIRST FP_RETURN 691 #define FP_RETURN_LAST FP_RETURN + 1 692 693 #define MAX_ARGS_IN_REGISTERS \ 694 (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \ 695 ? 6 \ 696 : 8) 697 698 #define MAX_ARGS_IN_VECTOR_REGISTERS (16) 699 #define MAX_ARGS_IN_MASK_REGISTERS (1) 700 701 /* Symbolic macros for the first/last argument registers. */ 702 703 #define GP_ARG_FIRST (GP_REG_FIRST + 10) 704 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 705 #define GP_TEMP_FIRST (GP_REG_FIRST + 5) 706 #define FP_ARG_FIRST (FP_REG_FIRST + 10) 707 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 708 #define V_ARG_FIRST (V_REG_FIRST + 8) 709 #define V_ARG_LAST (V_ARG_FIRST + MAX_ARGS_IN_VECTOR_REGISTERS - 1) 710 711 #define CALLEE_SAVED_REG_NUMBER(REGNO) \ 712 ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 : \ 713 (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1) 714 715 #define CALLEE_SAVED_FREG_NUMBER(REGNO) CALLEE_SAVED_REG_NUMBER (REGNO - 32) 716 717 #define LIBCALL_VALUE(MODE) \ 718 riscv_function_value (NULL_TREE, NULL_TREE, MODE) 719 720 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 721 riscv_function_value (VALTYPE, FUNC, VOIDmode) 722 723 /* 1 if N is a possible register number for function argument passing. 724 We have no FP argument registers when soft-float. */ 725 726 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */ 727 #define FUNCTION_ARG_REGNO_P(N) \ 728 (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \ 729 || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST))) 730 731 /* Define the standard RISC-V calling convention and variants. */ 732 733 enum riscv_cc 734 { 735 RISCV_CC_BASE = 0, /* Base standard RISC-V ABI. */ 736 RISCV_CC_V, /* For functions that pass or return values in V registers. */ 737 RISCV_CC_UNKNOWN 738 }; 739 740 typedef struct { 741 /* The calling convention that current function used. */ 742 enum riscv_cc variant_cc; 743 744 /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */ 745 unsigned int num_gprs; 746 747 /* Number of floating-point registers used so far, likewise. */ 748 unsigned int num_fprs; 749 750 /* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS. */ 751 unsigned int num_mrs; 752 753 /* The used state of args in vector registers, true for used by prev arg, 754 initial to false. */ 755 bool used_vrs[MAX_ARGS_IN_VECTOR_REGISTERS]; 756 } CUMULATIVE_ARGS; 757 758 /* Return riscv calling convention of call_insn. */ 759 extern enum riscv_cc get_riscv_cc (const rtx use); 760 761 /* Initialize a variable CUM of type CUMULATIVE_ARGS 762 for a call to a function whose data type is FNTYPE. 763 For a library call, FNTYPE is 0. */ 764 765 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 766 riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT), \ 767 (N_NAMED_ARGS) != -1) 768 769 #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO) 770 771 /* Align based on stack boundary, which might have been set by the user. */ 772 #define RISCV_STACK_ALIGN(LOC) \ 773 (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8)) 774 775 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 776 the stack pointer does not matter. The value is tested only in 777 functions that have frame pointers. 778 No definition is equivalent to always zero. */ 779 780 #define EXIT_IGNORE_STACK 1 781 782 783 /* Trampolines are a block of code followed by two pointers. */ 784 785 #define TRAMPOLINE_CODE_SIZE 16 786 #define TRAMPOLINE_SIZE \ 787 ((Pmode == SImode) \ 788 ? TRAMPOLINE_CODE_SIZE \ 789 : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2)) 790 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE 791 792 /* Addressing modes, and classification of registers for them. */ 793 794 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 795 riscv_regno_ok_for_index_p (REGNO) 796 797 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 798 riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1) 799 800 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 801 and check its validity for a certain class. 802 We have two alternate definitions for each of them. 803 The usual definition accepts all pseudo regs; the other rejects them all. 804 The symbol REG_OK_STRICT causes the latter definition to be used. 805 806 Most source files want to accept pseudo regs in the hope that 807 they will get allocated to the class that the insn wants them to be in. 808 Some source files that are used after register allocation 809 need to be strict. */ 810 811 #ifndef REG_OK_STRICT 812 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 813 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0) 814 #else 815 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 816 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1) 817 #endif 818 819 #define REG_OK_FOR_INDEX_P(X) 0 820 821 /* Maximum number of registers that can appear in a valid memory address. */ 822 823 #define MAX_REGS_PER_ADDRESS 1 824 825 #define CONSTANT_ADDRESS_P(X) \ 826 (CONSTANT_P (X) && memory_address_p (SImode, X)) 827 828 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means 829 'the start of the function that this code is output in'. */ 830 831 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 832 do { \ 833 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ 834 asm_fprintf ((FILE), "%U%s", \ 835 XSTR (XEXP (DECL_RTL (current_function_decl), \ 836 0), 0)); \ 837 else \ 838 asm_fprintf ((FILE), "%U%s", (NAME)); \ 839 } while (0) 840 841 #undef ASM_OUTPUT_OPCODE 842 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 843 (PTR) = riscv_asm_output_opcode(STREAM, PTR) 844 845 #define JUMP_TABLES_IN_TEXT_SECTION (riscv_cmodel == CM_LARGE) 846 #define CASE_VECTOR_MODE SImode 847 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW) 848 849 #define LOCAL_SYM_P(sym) \ 850 ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym)) \ 851 || ((GET_CODE (sym) == CONST) \ 852 && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0)) \ 853 && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0)))) 854 855 /* The load-address macro is used for PC-relative addressing of symbols 856 that bind locally. Don't use it for symbols that should be addressed 857 via the GOT. Also, avoid it for CM_MEDLOW, where LUI addressing 858 currently results in more opportunities for linker relaxation. */ 859 #define USE_LOAD_ADDRESS_MACRO(sym) \ 860 (!TARGET_EXPLICIT_RELOCS && \ 861 ((flag_pic && LOCAL_SYM_P (sym)) || riscv_cmodel == CM_MEDANY)) 862 863 /* Define this as 1 if `char' should by default be signed; else as 0. */ 864 #define DEFAULT_SIGNED_CHAR 0 865 866 #define MOVE_MAX UNITS_PER_WORD 867 #define MAX_MOVE_MAX 8 868 869 /* The SPARC port says: 870 Nonzero if access to memory by bytes is slow and undesirable. 871 For RISC chips, it means that access to memory by bytes is no 872 better than access by words when possible, so grab a whole word 873 and maybe make use of that. */ 874 #define SLOW_BYTE_ACCESS 1 875 876 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns 877 in the md file instead. */ 878 #define SHIFT_COUNT_TRUNCATED 0 879 880 /* Specify the machine mode that pointers have. 881 After generation of rtl, the compiler makes no further distinction 882 between pointers and any other objects of this machine mode. */ 883 884 #define Pmode word_mode 885 886 /* Specify the machine mode that registers have. */ 887 888 #define Xmode (TARGET_64BIT ? DImode : SImode) 889 890 /* Give call MEMs SImode since it is the "most permissive" mode 891 for both 32-bit and 64-bit targets. */ 892 893 #define FUNCTION_MODE SImode 894 895 /* A C expression for the cost of a branch instruction. A value of 2 896 seems to minimize code size. */ 897 898 #define BRANCH_COST(speed_p, predictable_p) \ 899 ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost) 900 901 /* True if the target optimizes short forward branches around integer 902 arithmetic instructions into predicated operations, e.g., for 903 conditional-move operations. The macro assumes that all branch 904 instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ) 905 support this feature. The macro further assumes that any integer 906 arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I], 907 SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed 908 counterparts, including C.MV and C.LI) can be in the branch shadow. */ 909 910 #define TARGET_SFB_ALU \ 911 ((riscv_microarchitecture == sifive_7) \ 912 || (riscv_microarchitecture == sifive_p400) \ 913 || (riscv_microarchitecture == sifive_p600)) 914 915 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 916 917 /* Control the assembler format that we output. */ 918 919 /* Output to assembler file text saying following lines 920 may contain character constants, extra white space, comments, etc. */ 921 922 #ifndef ASM_APP_ON 923 #define ASM_APP_ON " #APP\n" 924 #endif 925 926 /* Output to assembler file text saying following lines 927 no longer contain unusual constructs. */ 928 929 #ifndef ASM_APP_OFF 930 #define ASM_APP_OFF " #NO_APP\n" 931 #endif 932 933 #define REGISTER_NAMES \ 934 { "zero","ra", "sp", "gp", "tp", "t0", "t1", "t2", \ 935 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", \ 936 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", \ 937 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", \ 938 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", \ 939 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", \ 940 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", \ 941 "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11", \ 942 "arg", "frame", "vl", "vtype", "vxrm", "frm", "vxsat", "N/A", \ 943 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \ 944 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \ 945 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \ 946 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ 947 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ 948 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ 949 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",} 950 951 #define ADDITIONAL_REGISTER_NAMES \ 952 { \ 953 { "x0", 0 + GP_REG_FIRST }, \ 954 { "x1", 1 + GP_REG_FIRST }, \ 955 { "x2", 2 + GP_REG_FIRST }, \ 956 { "x3", 3 + GP_REG_FIRST }, \ 957 { "x4", 4 + GP_REG_FIRST }, \ 958 { "x5", 5 + GP_REG_FIRST }, \ 959 { "x6", 6 + GP_REG_FIRST }, \ 960 { "x7", 7 + GP_REG_FIRST }, \ 961 { "x8", 8 + GP_REG_FIRST }, \ 962 { "x9", 9 + GP_REG_FIRST }, \ 963 { "x10", 10 + GP_REG_FIRST }, \ 964 { "x11", 11 + GP_REG_FIRST }, \ 965 { "x12", 12 + GP_REG_FIRST }, \ 966 { "x13", 13 + GP_REG_FIRST }, \ 967 { "x14", 14 + GP_REG_FIRST }, \ 968 { "x15", 15 + GP_REG_FIRST }, \ 969 { "x16", 16 + GP_REG_FIRST }, \ 970 { "x17", 17 + GP_REG_FIRST }, \ 971 { "x18", 18 + GP_REG_FIRST }, \ 972 { "x19", 19 + GP_REG_FIRST }, \ 973 { "x20", 20 + GP_REG_FIRST }, \ 974 { "x21", 21 + GP_REG_FIRST }, \ 975 { "x22", 22 + GP_REG_FIRST }, \ 976 { "x23", 23 + GP_REG_FIRST }, \ 977 { "x24", 24 + GP_REG_FIRST }, \ 978 { "x25", 25 + GP_REG_FIRST }, \ 979 { "x26", 26 + GP_REG_FIRST }, \ 980 { "x27", 27 + GP_REG_FIRST }, \ 981 { "x28", 28 + GP_REG_FIRST }, \ 982 { "x29", 29 + GP_REG_FIRST }, \ 983 { "x30", 30 + GP_REG_FIRST }, \ 984 { "x31", 31 + GP_REG_FIRST }, \ 985 { "f0", 0 + FP_REG_FIRST }, \ 986 { "f1", 1 + FP_REG_FIRST }, \ 987 { "f2", 2 + FP_REG_FIRST }, \ 988 { "f3", 3 + FP_REG_FIRST }, \ 989 { "f4", 4 + FP_REG_FIRST }, \ 990 { "f5", 5 + FP_REG_FIRST }, \ 991 { "f6", 6 + FP_REG_FIRST }, \ 992 { "f7", 7 + FP_REG_FIRST }, \ 993 { "f8", 8 + FP_REG_FIRST }, \ 994 { "f9", 9 + FP_REG_FIRST }, \ 995 { "f10", 10 + FP_REG_FIRST }, \ 996 { "f11", 11 + FP_REG_FIRST }, \ 997 { "f12", 12 + FP_REG_FIRST }, \ 998 { "f13", 13 + FP_REG_FIRST }, \ 999 { "f14", 14 + FP_REG_FIRST }, \ 1000 { "f15", 15 + FP_REG_FIRST }, \ 1001 { "f16", 16 + FP_REG_FIRST }, \ 1002 { "f17", 17 + FP_REG_FIRST }, \ 1003 { "f18", 18 + FP_REG_FIRST }, \ 1004 { "f19", 19 + FP_REG_FIRST }, \ 1005 { "f20", 20 + FP_REG_FIRST }, \ 1006 { "f21", 21 + FP_REG_FIRST }, \ 1007 { "f22", 22 + FP_REG_FIRST }, \ 1008 { "f23", 23 + FP_REG_FIRST }, \ 1009 { "f24", 24 + FP_REG_FIRST }, \ 1010 { "f25", 25 + FP_REG_FIRST }, \ 1011 { "f26", 26 + FP_REG_FIRST }, \ 1012 { "f27", 27 + FP_REG_FIRST }, \ 1013 { "f28", 28 + FP_REG_FIRST }, \ 1014 { "f29", 29 + FP_REG_FIRST }, \ 1015 { "f30", 30 + FP_REG_FIRST }, \ 1016 { "f31", 31 + FP_REG_FIRST }, \ 1017 } 1018 1019 /* Globalizing directive for a label. */ 1020 #define GLOBAL_ASM_OP "\t.globl\t" 1021 1022 /* This is how to store into the string LABEL 1023 the symbol_ref name of an internal numbered label where 1024 PREFIX is the class of label and NUM is the number within the class. 1025 This is suitable for output with `assemble_name'. */ 1026 1027 #undef ASM_GENERATE_INTERNAL_LABEL 1028 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1029 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) 1030 1031 /* This is how to output an element of a case-vector that is absolute. */ 1032 1033 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 1034 fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE) 1035 1036 /* This is how to output an element of a PIC case-vector. */ 1037 1038 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 1039 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \ 1040 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL) 1041 1042 /* This is how to output an assembler line 1043 that says to advance the location counter 1044 to a multiple of 2**LOG bytes. */ 1045 1046 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 1047 fprintf (STREAM, "\t.align\t%d\n", (LOG)) 1048 1049 /* Define the strings to put out for each section in the object file. */ 1050 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ 1051 #define DATA_SECTION_ASM_OP "\t.data" /* large data */ 1052 #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata" 1053 #define BSS_SECTION_ASM_OP "\t.bss" 1054 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss,\"aw\",@nobits" 1055 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata,\"aw\",@progbits" 1056 1057 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 1058 do \ 1059 { \ 1060 fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ 1061 reg_names[STACK_POINTER_REGNUM], \ 1062 reg_names[STACK_POINTER_REGNUM], \ 1063 TARGET_64BIT ? "sd" : "sw", \ 1064 reg_names[REGNO], \ 1065 reg_names[STACK_POINTER_REGNUM]); \ 1066 } \ 1067 while (0) 1068 1069 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 1070 do \ 1071 { \ 1072 fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n", \ 1073 TARGET_64BIT ? "ld" : "lw", \ 1074 reg_names[REGNO], \ 1075 reg_names[STACK_POINTER_REGNUM], \ 1076 reg_names[STACK_POINTER_REGNUM], \ 1077 reg_names[STACK_POINTER_REGNUM]); \ 1078 } \ 1079 while (0) 1080 1081 #define ASM_COMMENT_START "#" 1082 1083 /* Add output .variant_cc directive for specific function definition. */ 1084 #undef ASM_DECLARE_FUNCTION_NAME 1085 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ 1086 riscv_declare_function_name (STR, NAME, DECL) 1087 1088 #undef ASM_DECLARE_FUNCTION_SIZE 1089 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ 1090 riscv_declare_function_size (FILE, FNAME, DECL) 1091 1092 /* Add output .variant_cc directive for specific alias definition. */ 1093 #undef ASM_OUTPUT_DEF_FROM_DECLS 1094 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \ 1095 riscv_asm_output_alias (STR, DECL, TARGET) 1096 1097 /* Add output .variant_cc directive for specific extern function. */ 1098 #undef ASM_OUTPUT_EXTERNAL 1099 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \ 1100 riscv_asm_output_external (STR, DECL, NAME) 1101 1102 #undef SIZE_TYPE 1103 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") 1104 1105 #undef PTRDIFF_TYPE 1106 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") 1107 1108 /* The maximum number of bytes copied by one iteration of a cpymemsi loop. */ 1109 1110 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4) 1111 1112 /* The maximum number of bytes that can be copied by a straight-line 1113 cpymemsi implementation. */ 1114 1115 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3) 1116 1117 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1118 move-instruction pairs, we will do a cpymem or libcall instead. 1119 Do not use move_by_pieces at all when strict alignment is not 1120 in effect but the target has slow unaligned accesses; in this 1121 case, cpymem or libcall is more efficient. */ 1122 1123 #define MOVE_RATIO(speed) \ 1124 (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 : \ 1125 (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD : \ 1126 CLEAR_RATIO (speed) / 2) 1127 1128 /* For CLEAR_RATIO, when optimizing for size, give a better estimate 1129 of the length of a memset call, but use the default otherwise. */ 1130 1131 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6) 1132 1133 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when 1134 optimizing for size adjust the ratio to account for the overhead of 1135 loading the constant and replicating it across the word. */ 1136 1137 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2)) 1138 1139 #ifndef USED_FOR_TARGET 1140 extern const enum reg_class riscv_regno_to_class[]; 1141 extern bool riscv_slow_unaligned_access_p; 1142 extern bool riscv_user_wants_strict_align; 1143 extern unsigned riscv_stack_boundary; 1144 extern unsigned riscv_bytes_per_vector_chunk; 1145 extern poly_uint16 riscv_vector_chunks; 1146 extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int); 1147 extern poly_int64 riscv_v_adjust_nunits (machine_mode, bool, int, int); 1148 extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int); 1149 extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int); 1150 /* The number of bits and bytes in a RVV vector. */ 1151 #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8)) 1152 #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk)) 1153 #endif 1154 1155 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1156 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) 1157 1158 #define XLEN_SPEC \ 1159 "%{march=rv32*:32}" \ 1160 "%{march=rv64*:64}" \ 1161 1162 #define ABI_SPEC \ 1163 "%{mabi=ilp32:ilp32}" \ 1164 "%{mabi=ilp32e:ilp32e}" \ 1165 "%{mabi=ilp32f:ilp32f}" \ 1166 "%{mabi=ilp32d:ilp32d}" \ 1167 "%{mabi=lp64:lp64}" \ 1168 "%{mabi=lp64e:lp64e}" \ 1169 "%{mabi=lp64f:lp64f}" \ 1170 "%{mabi=lp64d:lp64d}" \ 1171 1172 /* ISA constants needed for code generation. */ 1173 #define OPCODE_LW 0x2003 1174 #define OPCODE_LD 0x3003 1175 #define OPCODE_AUIPC 0x17 1176 #define OPCODE_JALR 0x67 1177 #define OPCODE_LUI 0x37 1178 #define OPCODE_ADDI 0x13 1179 #define SHIFT_RD 7 1180 #define SHIFT_RS1 15 1181 #define SHIFT_IMM 20 1182 #define IMM_BITS 12 1183 #define C_S_BITS 5 1184 #define C_SxSP_BITS 6 1185 1186 #define IMM_REACH (1LL << IMM_BITS) 1187 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1)) 1188 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE)) 1189 1190 #define SWSP_REACH (4LL << C_SxSP_BITS) 1191 #define SDSP_REACH (8LL << C_SxSP_BITS) 1192 1193 /* This is the maximum value that can be represented in a compressed load/store 1194 offset (an unsigned 5-bit value scaled by 4). */ 1195 #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3) 1196 1197 /* Called from RISCV_REORG, this is defined in riscv-sr.cc. */ 1198 1199 extern void riscv_remove_unneeded_save_restore_calls (void); 1200 1201 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO) 1202 1203 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1204 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 1205 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1206 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 1207 1208 #define TARGET_SUPPORTS_WIDE_INT 1 1209 1210 #define REGISTER_TARGET_PRAGMAS() riscv_register_pragmas () 1211 1212 #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE) 1213 1214 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 1 /* VLENB */) 1215 1216 #define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \ 1217 ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO) 1218 1219 /* Like s390, riscv also defined this macro for the vector comparision. Then 1220 the simplify-rtx relational_result will canonicalize the result to the 1221 CONST1_RTX for the simplification. */ 1222 #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE)) 1223 1224 /* Mode switching (Lazy code motion) for RVV rounding mode instructions. */ 1225 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR) 1226 #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE} 1227 1228 /* The size difference between different RVV modes can be up to 64 times. 1229 e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64]. */ 1230 #define MAX_POLY_VARIANT 64 1231 1232 #define HAVE_POST_MODIFY_DISP TARGET_XTHEADMEMIDX 1233 #define HAVE_PRE_MODIFY_DISP TARGET_XTHEADMEMIDX 1234 1235 /* Check TLS Descriptors mechanism is selected. */ 1236 #define TARGET_TLSDESC (riscv_tls_dialect == TLS_DESCRIPTORS) 1237 1238 #endif /* ! GCC_RISCV_H */ 1239
Indexes created Fri Jun 26 00:24:39 UTC 2026