1 /* $NetBSD: i128reg.h,v 1.5 2020/04/16 23:29:53 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: i128reg.h,v 1.5 2020/04/16 23:29:53 rin Exp $"); 31 32 /* 33 * register definition for Number Nine Imagine 128 graphics controllers 34 * 35 * adapted from XFree86's i128 driver source 36 */ 37 38 #ifndef I128REG_H 39 #define I128REG_H 40 41 #define INTP 0x4000 42 #define INTP_DD_INT 0x01 /* drawing op completed */ 43 #define INTP_CL_INT 0x02 44 #define INTM 0x4004 45 #define INTM_DD_MSK 0x01 46 #define INTM_CL_MSK 0x02 47 #define FLOW 0x4008 48 #define FLOW_DEB 0x01 /* drawing engine busy */ 49 #define FLOW_MCB 0x02 /* mem controller busy */ 50 #define FLOW_CLP 0x04 51 #define FLOW_PRV 0x08 /* prev cmd still running or cache ready */ 52 #define BUSY 0x400C 53 #define BUSY_BUSY 0x01 /* command pipeline busy */ 54 #define XYW_AD 0x4010 55 #define Z_CTRL 0x4018 56 #define BUF_CTRL 0x4020 57 #define BC_AMV 0x02 58 #define BC_MP 0x04 59 #define BC_AMD 0x08 60 #define BC_SEN_MSK 0x0300 61 #define BC_SEN_DB 0x0000 62 #define BC_SEN_VB 0x0100 63 #define BC_SEN_MB 0x0200 64 #define BC_SEN_CB 0x0300 65 #define BC_DEN_MSK 0x0C00 66 #define BC_DEN_DB 0x0000 67 #define BC_DEN_VB 0x0400 68 #define BC_DEN_MB 0x0800 69 #define BC_DEN_CB 0x0C00 70 #define BC_DSE 0x1000 71 #define BC_VSE 0x2000 72 #define BC_MSE 0x4000 73 #define BC_PS_MSK 0x001F0000 74 #define BC_MDM_MSK 0x00600000 75 #define BC_MDM_KEY 0x00200000 76 #define BC_MDM_PLN 0x00400000 77 #define BC_BLK_ENA 0x00800000 78 #define BC_PSIZ_MSK 0x03000000 79 #define BC_PSIZ_8B 0x00000000 80 #define BC_PSIZ_16B 0x01000000 81 #define BC_PSIZ_32B 0x02000000 82 #define BC_PSIZ_NOB 0x03000000 83 #define BC_CO 0x40000000 84 #define BC_CR 0x80000000 85 #define DE_PGE 0x4024 86 #define DP_DVP_MSK 0x0000001F 87 #define DP_MP_MSK 0x000F0000 88 #define DE_SORG 0x4028 89 #define DE_DORG 0x402C 90 #define DE_MSRC 0x4030 91 #define DE_WKEY 0x4038 92 #define DE_KYDAT 0x403C 93 #define DE_ZPTCH 0x403C 94 #define DE_SPTCH 0x4040 95 #define DE_DPTCH 0x4044 96 #define CMD 0x4048 97 #define CMD_OPC_MSK 0x000000FF 98 #define CMD_ROP_MSK 0x0000FF00 99 #define CMD_STL_MSK 0x001F0000 100 #define CMD_CLP_MSK 0x00E00000 101 #define CMD_PAT_MSK 0x0F000000 102 #define CMD_HDF_MSK 0x70000000 103 #define CMD_OPC 0x4050 104 #define CO_NOOP 0x00 105 #define CO_BITBLT 0x01 106 #define CO_LINE 0x02 107 #define CO_ELINE 0x03 108 #define CO_TRIAN 0x04 109 #define CO_RXFER 0x06 110 #define CO_WXFER 0x07 111 #define CMD_ROP 0x4054 112 #define CR_CLEAR 0x00 113 #define CR_NOR 0x01 114 #define CR_AND_INV 0x02 115 #define CR_COPY_INV 0x03 116 #define CR_AND_REV 0x04 117 #define CR_INVERT 0x05 118 #define CR_XOR 0x06 119 #define CR_NAND 0x07 120 #define CR_AND 0x08 121 #define CR_EQUIV 0x09 122 #define CR_NOOP 0x0A 123 #define CR_OR_INV 0x0B 124 #define CR_COPY 0x0C 125 #define CR_OR_REV 0x0D 126 #define CR_OR 0x0E 127 #define CR_SET 0x0F 128 #define CMD_STYLE 0x4058 129 #define CS_SOLID 0x01 130 #define CS_TRNSP 0x02 131 #define CS_STP_NO 0x00 132 #define CS_STP_PL 0x04 133 #define CS_STP_PA32 0x08 134 #define CS_STP_PA8 0x0C 135 #define CS_EDI 0x10 136 #define CMD_PATRN 0x405C 137 #define CP_APAT_NO 0x00 138 #define CP_APAT_8X 0x01 139 #define CP_APAT_32X 0x02 140 #define CP_NLST 0x04 141 #define CP_PRST 0x08 142 #define CMD_CLP 0x4060 143 #define CC_NOCLP 0x00 144 #define CC_CLPRECI 0x02 145 #define CC_CLPRECO 0x03 146 #define CC_CLPSTOP 0x04 147 #define CMD_HDF 0x4064 148 #define CH_BIT_SWP 0x01 149 #define CH_BYT_SWP 0x02 150 #define CH_WRD_SWP 0x04 151 #define FORE 0x4068 152 #define BACK 0x406C 153 #define MASK 0x4070 154 #define RMSK 0x4074 155 #define LPAT 0x4078 156 #define PCTRL 0x407C 157 #define PC_PLEN_MSK 0x0000001F 158 #define PC_PSCL_MSK 0x000000E0 159 #define PC_SPTR_MSK 0x00001F00 160 #define PC_SSCL_MSK 0x0000E000 161 #define PC_STATE_MSK 0xFFFF0000 162 #define CLPTL 0x4080 /* clipping top/left */ 163 #define CLPTLY_MSK 0x0000FFFF 164 #define CLPTLX_MSK 0xFFFF0000 165 #define CLPBR 0x4084 /* clipping bottom/right */ 166 #define CLPBRY_MSK 0x0000FFFF 167 #define CLPBRX_MSK 0xFFFF0000 168 #define XY0_SRC 0x4088 169 #define XY1_DST 0x408C /* trigger */ 170 #define XY2_WH 0x4090 171 #define XY3_DIR 0x4094 172 #define DIR_LR_TB 0x00000000 173 #define DIR_LR_BT 0x00000001 174 #define DIR_RL_TB 0x00000002 175 #define DIR_RL_BT 0x00000003 176 #define DIR_BT 0x00000001 177 #define DIR_RL 0x00000002 178 #define XY4_ZM 0x4098 179 #define ZOOM_NONE 0x00000000 180 #define XY_Y_DATA 0x0000FFFF 181 #define XY_X_DATA 0xFFFF0000 182 #define XY_I_DATA1 0x0000FFFF 183 #define XY_I_DATA2 0xFFFF0000 184 #define DL_ADR 0x40F8 185 #define DL_CNTRL 0x40FC 186 #define ACNTRL 0x416C 187 188 /* wait until the blitter can accept another command */ 189 #define I128_READY(tag, regh) \ 190 do {} while ((bus_space_read_4(tag, regh, BUSY) & BUSY_BUSY) != 0); 191 192 /* wait until it's safe to access video memory */ 193 #define I128_DONE(tag, regh) \ 194 do {} while ((bus_space_read_4(tag, regh, FLOW) & 0x0f) != 0); 195 196 #endif /* I128REG_H */ 197
Indexes created Mon Sep 22 13:09:51 GMT 2025