1 /* $NetBSD: bus_defs.h,v 1.21 2026/02/19 08:50:04 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _ARM_BUS_DEFS_H_ 65 #define _ARM_BUS_DEFS_H_ 66 67 #if defined(_KERNEL_OPT) 68 #include "opt_arm_bus_space.h" 69 #include "opt_kasan.h" 70 #endif 71 72 /* 73 * Addresses (in bus space). 74 */ 75 typedef u_long bus_addr_t; 76 typedef u_long bus_size_t; 77 78 #define PRIxBUSADDR "lx" 79 #define PRIxBUSSIZE "lx" 80 #define PRIuBUSSIZE "lu" 81 82 /* 83 * Access methods for bus space. 84 */ 85 typedef struct bus_space *bus_space_tag_t; 86 typedef u_long bus_space_handle_t; 87 88 #define PRIxBSH "lx" 89 90 /* 91 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, 92 * bus_size_t size, int flags, bus_space_handle_t *bshp); 93 * 94 * Map a region of bus space. 95 */ 96 97 #define BUS_SPACE_MAP_BUS1 0x0100 98 #define BUS_SPACE_MAP_BUS2 0x0200 99 #define BUS_SPACE_MAP_BUS3 0x0400 100 #define BUS_SPACE_MAP_BUS4 0x0800 101 102 #define BUS_SPACE_MAP_NONPOSTED BUS_SPACE_MAP_BUS1 103 104 struct bus_space { 105 /* cookie */ 106 void *bs_cookie; 107 108 /* used for aarch64. require ".bs_cookie = bus_space" */ 109 int bs_stride; /* offset <<= bs_stride (if needed) */ 110 int bs_flags; 111 112 /* mapping/unmapping */ 113 int (*bs_map)(void *, bus_addr_t, bus_size_t, 114 int, bus_space_handle_t *); 115 void (*bs_unmap)(void *, bus_space_handle_t, 116 bus_size_t); 117 int (*bs_subregion)(void *, bus_space_handle_t, 118 bus_size_t, bus_size_t, bus_space_handle_t *); 119 120 /* allocation/deallocation */ 121 int (*bs_alloc)(void *, bus_addr_t, bus_addr_t, 122 bus_size_t, bus_size_t, bus_size_t, int, 123 bus_addr_t *, bus_space_handle_t *); 124 void (*bs_free)(void *, bus_space_handle_t, 125 bus_size_t); 126 127 /* get kernel virtual address */ 128 void * (*bs_vaddr)(void *, bus_space_handle_t); 129 130 /* mmap bus space for user */ 131 paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int); 132 133 /* barrier */ 134 void (*bs_barrier)(void *, bus_space_handle_t, 135 bus_size_t, bus_size_t, int); 136 137 /* read (single) */ 138 uint8_t (*bs_r_1)(void *, bus_space_handle_t, 139 bus_size_t); 140 uint16_t (*bs_r_2)(void *, bus_space_handle_t, 141 bus_size_t); 142 uint32_t (*bs_r_4)(void *, bus_space_handle_t, 143 bus_size_t); 144 uint64_t (*bs_r_8)(void *, bus_space_handle_t, 145 bus_size_t); 146 147 /* read multiple */ 148 void (*bs_rm_1)(void *, bus_space_handle_t, 149 bus_size_t, uint8_t *, bus_size_t); 150 void (*bs_rm_2)(void *, bus_space_handle_t, 151 bus_size_t, uint16_t *, bus_size_t); 152 void (*bs_rm_4)(void *, bus_space_handle_t, 153 bus_size_t, uint32_t *, bus_size_t); 154 void (*bs_rm_8)(void *, bus_space_handle_t, 155 bus_size_t, uint64_t *, bus_size_t); 156 157 /* read region */ 158 void (*bs_rr_1)(void *, bus_space_handle_t, 159 bus_size_t, uint8_t *, bus_size_t); 160 void (*bs_rr_2)(void *, bus_space_handle_t, 161 bus_size_t, uint16_t *, bus_size_t); 162 void (*bs_rr_4)(void *, bus_space_handle_t, 163 bus_size_t, uint32_t *, bus_size_t); 164 void (*bs_rr_8)(void *, bus_space_handle_t, 165 bus_size_t, uint64_t *, bus_size_t); 166 167 /* write (single) */ 168 void (*bs_w_1)(void *, bus_space_handle_t, 169 bus_size_t, uint8_t); 170 void (*bs_w_2)(void *, bus_space_handle_t, 171 bus_size_t, uint16_t); 172 void (*bs_w_4)(void *, bus_space_handle_t, 173 bus_size_t, uint32_t); 174 void (*bs_w_8)(void *, bus_space_handle_t, 175 bus_size_t, uint64_t); 176 177 /* write multiple */ 178 void (*bs_wm_1)(void *, bus_space_handle_t, 179 bus_size_t, const uint8_t *, bus_size_t); 180 void (*bs_wm_2)(void *, bus_space_handle_t, 181 bus_size_t, const uint16_t *, bus_size_t); 182 void (*bs_wm_4)(void *, bus_space_handle_t, 183 bus_size_t, const uint32_t *, bus_size_t); 184 void (*bs_wm_8)(void *, bus_space_handle_t, 185 bus_size_t, const uint64_t *, bus_size_t); 186 187 /* write region */ 188 void (*bs_wr_1)(void *, bus_space_handle_t, 189 bus_size_t, const uint8_t *, bus_size_t); 190 void (*bs_wr_2)(void *, bus_space_handle_t, 191 bus_size_t, const uint16_t *, bus_size_t); 192 void (*bs_wr_4)(void *, bus_space_handle_t, 193 bus_size_t, const uint32_t *, bus_size_t); 194 void (*bs_wr_8)(void *, bus_space_handle_t, 195 bus_size_t, const uint64_t *, bus_size_t); 196 197 /* set multiple */ 198 void (*bs_sm_1)(void *, bus_space_handle_t, 199 bus_size_t, uint8_t, bus_size_t); 200 void (*bs_sm_2)(void *, bus_space_handle_t, 201 bus_size_t, uint16_t, bus_size_t); 202 void (*bs_sm_4)(void *, bus_space_handle_t, 203 bus_size_t, uint32_t, bus_size_t); 204 void (*bs_sm_8)(void *, bus_space_handle_t, 205 bus_size_t, uint64_t, bus_size_t); 206 207 /* set region */ 208 void (*bs_sr_1)(void *, bus_space_handle_t, 209 bus_size_t, uint8_t, bus_size_t); 210 void (*bs_sr_2)(void *, bus_space_handle_t, 211 bus_size_t, uint16_t, bus_size_t); 212 void (*bs_sr_4)(void *, bus_space_handle_t, 213 bus_size_t, uint32_t, bus_size_t); 214 void (*bs_sr_8)(void *, bus_space_handle_t, 215 bus_size_t, uint64_t, bus_size_t); 216 217 /* copy */ 218 void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t, 219 bus_space_handle_t, bus_size_t, bus_size_t); 220 void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t, 221 bus_space_handle_t, bus_size_t, bus_size_t); 222 void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t, 223 bus_space_handle_t, bus_size_t, bus_size_t); 224 void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t, 225 bus_space_handle_t, bus_size_t, bus_size_t); 226 227 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 228 /* read stream (single) */ 229 uint8_t (*bs_r_1_s)(void *, bus_space_handle_t, 230 bus_size_t); 231 uint16_t (*bs_r_2_s)(void *, bus_space_handle_t, 232 bus_size_t); 233 uint32_t (*bs_r_4_s)(void *, bus_space_handle_t, 234 bus_size_t); 235 uint64_t (*bs_r_8_s)(void *, bus_space_handle_t, 236 bus_size_t); 237 238 /* read multiple stream */ 239 void (*bs_rm_1_s)(void *, bus_space_handle_t, 240 bus_size_t, uint8_t *, bus_size_t); 241 void (*bs_rm_2_s)(void *, bus_space_handle_t, 242 bus_size_t, uint16_t *, bus_size_t); 243 void (*bs_rm_4_s)(void *, bus_space_handle_t, 244 bus_size_t, uint32_t *, bus_size_t); 245 void (*bs_rm_8_s)(void *, bus_space_handle_t, 246 bus_size_t, uint64_t *, bus_size_t); 247 248 /* read region stream */ 249 void (*bs_rr_1_s)(void *, bus_space_handle_t, 250 bus_size_t, uint8_t *, bus_size_t); 251 void (*bs_rr_2_s)(void *, bus_space_handle_t, 252 bus_size_t, uint16_t *, bus_size_t); 253 void (*bs_rr_4_s)(void *, bus_space_handle_t, 254 bus_size_t, uint32_t *, bus_size_t); 255 void (*bs_rr_8_s)(void *, bus_space_handle_t, 256 bus_size_t, uint64_t *, bus_size_t); 257 258 /* write stream (single) */ 259 void (*bs_w_1_s)(void *, bus_space_handle_t, 260 bus_size_t, uint8_t); 261 void (*bs_w_2_s)(void *, bus_space_handle_t, 262 bus_size_t, uint16_t); 263 void (*bs_w_4_s)(void *, bus_space_handle_t, 264 bus_size_t, uint32_t); 265 void (*bs_w_8_s)(void *, bus_space_handle_t, 266 bus_size_t, uint64_t); 267 268 /* write multiple stream */ 269 void (*bs_wm_1_s)(void *, bus_space_handle_t, 270 bus_size_t, const uint8_t *, bus_size_t); 271 void (*bs_wm_2_s)(void *, bus_space_handle_t, 272 bus_size_t, const uint16_t *, bus_size_t); 273 void (*bs_wm_4_s)(void *, bus_space_handle_t, 274 bus_size_t, const uint32_t *, bus_size_t); 275 void (*bs_wm_8_s)(void *, bus_space_handle_t, 276 bus_size_t, const uint64_t *, bus_size_t); 277 278 /* write region stream */ 279 void (*bs_wr_1_s)(void *, bus_space_handle_t, 280 bus_size_t, const uint8_t *, bus_size_t); 281 void (*bs_wr_2_s)(void *, bus_space_handle_t, 282 bus_size_t, const uint16_t *, bus_size_t); 283 void (*bs_wr_4_s)(void *, bus_space_handle_t, 284 bus_size_t, const uint32_t *, bus_size_t); 285 void (*bs_wr_8_s)(void *, bus_space_handle_t, 286 bus_size_t, const uint64_t *, bus_size_t); 287 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 288 289 #ifdef __BUS_SPACE_HAS_PROBING_METHODS 290 /* peek */ 291 int (*bs_pe_1)(void *, bus_space_handle_t, 292 bus_size_t, uint8_t *); 293 int (*bs_pe_2)(void *, bus_space_handle_t, 294 bus_size_t, uint16_t *); 295 int (*bs_pe_4)(void *, bus_space_handle_t, 296 bus_size_t, uint32_t *); 297 int (*bs_pe_8)(void *, bus_space_handle_t, 298 bus_size_t, uint64_t *); 299 300 /* poke */ 301 int (*bs_po_1)(void *, bus_space_handle_t, 302 bus_size_t, uint8_t); 303 int (*bs_po_2)(void *, bus_space_handle_t, 304 bus_size_t, uint16_t); 305 int (*bs_po_4)(void *, bus_space_handle_t, 306 bus_size_t, uint32_t); 307 int (*bs_po_8)(void *, bus_space_handle_t, 308 bus_size_t, uint64_t); 309 #endif /* __BUS_SPACE_HAS_PROBING_METHODS */ 310 }; 311 312 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 313 314 /* Bus DMA macros */ 315 316 /* 317 * Private flags stored in the DMA map. 318 */ 319 #define _BUS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ 320 #define _BUS_DMAMAP_IS_BOUNCING 0x20000 /* is bouncing current xfer */ 321 #define _BUS_DMAMAP_NOALLOC 0x40000 /* don't alloc memory from this range */ 322 323 /* Forwards needed by prototypes below. */ 324 struct mbuf; 325 struct uio; 326 327 typedef struct arm32_bus_dma_tag *bus_dma_tag_t; 328 typedef struct arm32_bus_dmamap *bus_dmamap_t; 329 330 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 331 332 /* 333 * bus_dma_segment_t 334 * 335 * Describes a single contiguous DMA transaction. Values 336 * are suitable for programming into DMA registers. 337 */ 338 struct arm32_bus_dma_segment { 339 /* 340 * PUBLIC MEMBERS: these are used by machine-independent code. 341 */ 342 bus_addr_t ds_addr; /* DMA address */ 343 bus_size_t ds_len; /* length of transfer */ 344 345 /* 346 * PRIVATE MEMBERS: 347 */ 348 uint32_t _ds_flags; /* _BUS_DMAMAP_COHERENT */ 349 paddr_t _ds_paddr; /* CPU address */ 350 }; 351 typedef struct arm32_bus_dma_segment bus_dma_segment_t; 352 353 /* 354 * arm32_dma_range 355 * 356 * This structure describes a valid DMA range. 357 */ 358 struct arm32_dma_range { 359 paddr_t dr_sysbase; /* system base address */ 360 bus_addr_t dr_busbase; /* appears here on bus */ 361 bus_size_t dr_len; /* length of range */ 362 uint32_t dr_flags; /* flags for range */ 363 }; 364 365 /* 366 * bus_dma_tag_t 367 * 368 * A machine-dependent opaque type describing the implementation of 369 * DMA for a given bus. 370 */ 371 372 struct arm32_bus_dma_tag { 373 /* 374 * DMA range for this tag. If the page doesn't fall within 375 * one of these ranges, an error is returned. The caller 376 * may then decide what to do with the transfer. If the 377 * range pointer is NULL, it is ignored. 378 */ 379 struct arm32_dma_range *_ranges; 380 int _nranges; 381 382 /* 383 * Opaque cookie for use by back-end. 384 */ 385 void *_cookie; 386 387 /* 388 * DMA mapping methods. 389 */ 390 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 391 bus_size_t, bus_size_t, int, bus_dmamap_t *); 392 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 393 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 394 bus_size_t, struct proc *, int); 395 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 396 struct mbuf *, int); 397 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 398 struct uio *, int); 399 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 400 bus_dma_segment_t *, int, bus_size_t, int); 401 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 402 void (*_dmamap_sync_pre)(bus_dma_tag_t, bus_dmamap_t, 403 bus_addr_t, bus_size_t, int); 404 void (*_dmamap_sync_post)(bus_dma_tag_t, bus_dmamap_t, 405 bus_addr_t, bus_size_t, int); 406 407 /* 408 * DMA memory utility functions. 409 */ 410 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 411 bus_size_t, bus_dma_segment_t *, int, int *, int); 412 void (*_dmamem_free)(bus_dma_tag_t, 413 bus_dma_segment_t *, int); 414 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 415 int, size_t, void **, int); 416 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 417 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 418 int, off_t, int, int); 419 420 /* 421 * DMA tag utility functions 422 */ 423 int (*_dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t, 424 bus_dma_tag_t *, int); 425 void (*_dmatag_destroy)(bus_dma_tag_t); 426 427 /* 428 * State for bounce buffers 429 */ 430 int _tag_needs_free; 431 int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *); 432 }; 433 434 /* 435 * bus_dmamap_t 436 * 437 * Describes a DMA mapping. 438 */ 439 struct arm32_bus_dmamap { 440 /* 441 * PRIVATE MEMBERS: not for use by machine-independent code. 442 */ 443 bus_size_t _dm_size; /* largest DMA transfer mappable */ 444 int _dm_segcnt; /* number of segs this map can map */ 445 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 446 bus_size_t _dm_boundary; /* don't cross this */ 447 int _dm_flags; /* misc. flags */ 448 449 void *_dm_origbuf; /* pointer to original buffer */ 450 int _dm_buftype; /* type of buffer */ 451 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 452 453 void *_dm_cookie; /* cookie for bus-specific functions */ 454 void *_dm_iommu; /* cookie for iommu functions */ 455 456 /* 457 * PUBLIC MEMBERS: these are used by machine-independent code. 458 */ 459 #if defined(KASAN) 460 void *dm_buf; 461 bus_size_t dm_buflen; 462 int dm_buftype; 463 #endif 464 bus_size_t dm_maxsegsz; /* largest possible segment */ 465 bus_size_t dm_mapsize; /* size of the mapping */ 466 int dm_nsegs; /* # valid segments in mapping */ 467 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 468 }; 469 470 /* _dm_buftype */ 471 #define _BUS_DMA_BUFTYPE_INVALID 0 472 #define _BUS_DMA_BUFTYPE_LINEAR 1 473 #define _BUS_DMA_BUFTYPE_MBUF 2 474 #define _BUS_DMA_BUFTYPE_UIO 3 475 #define _BUS_DMA_BUFTYPE_RAW 4 476 477 #ifdef _ARM32_BUS_DMA_PRIVATE 478 #define _BUS_AVAIL_END (physical_end - 1) 479 /* 480 * Cookie used for bounce buffers. A pointer to one of these it stashed in 481 * the DMA map. 482 */ 483 struct arm32_bus_dma_cookie { 484 int id_flags; /* flags; see below */ 485 486 /* 487 * Information about the original buffer used during 488 * DMA map syncs. Note that origibuflen is only used 489 * for ID_BUFTYPE_LINEAR. 490 */ 491 union { 492 void *un_origbuf; /* pointer to orig buffer if 493 bouncing */ 494 char *un_linearbuf; 495 struct mbuf *un_mbuf; 496 struct uio *un_uio; 497 } id_origbuf_un; 498 #define id_origbuf id_origbuf_un.un_origbuf 499 #define id_origlinearbuf id_origbuf_un.un_linearbuf 500 #define id_origmbuf id_origbuf_un.un_mbuf 501 #define id_origuio id_origbuf_un.un_uio 502 bus_size_t id_origbuflen; /* ...and size */ 503 504 void *id_bouncebuf; /* pointer to the bounce buffer */ 505 bus_size_t id_bouncebuflen; /* ...and size */ 506 int id_nbouncesegs; /* number of valid bounce segs */ 507 bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer 508 physical memory segments */ 509 }; 510 511 /* id_flags */ 512 #define _BUS_DMA_IS_BOUNCING 0x04 /* is bouncing current xfer */ 513 #define _BUS_DMA_HAS_BOUNCE 0x02 /* has bounce buffers */ 514 #endif /* _ARM32_BUS_DMA_PRIVATE */ 515 #define _BUS_DMA_MIGHT_NEED_BOUNCE 0x01 /* may need bounce buffers */ 516 517 #endif /* _ARM_BUS_DEFS_H_ */ 518
Indexes created Sun Oct 11 00:26:46 UTC 2026