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    Searched defs:BW (Results 1 - 20 of 20) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonGenExtract.cpp 161 unsigned BW = Ty->getPrimitiveSizeInBits();
162 if (BW != 32 && BW != 64)
174 APInt A = APInt(BW, ~0ULL).lshr(SR).shl(SL);
185 uint32_t U = BW - std::max(SL, SR);
200 APInt C = APInt::getHighBitsSet(BW, BW-U);
212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu
HexagonConstPropagation.cpp 1595 unsigned BW = A1.getBitWidth();
1596 (void)BW;
1597 assert(Width >= Bits && BW >= Bits);
1626 unsigned BW = A1.getBitWidth();
1627 assert(Width >= Bits && BW >= Bits);
1636 if (BW <= 64 && Bits != 0) {
1661 if (Bits < BW)
1663 else // Bits == BW
1691 unsigned BW = A1.getBitWidth();
1699 Result = APInt(BW, static_cast<uint64_t>(Count), false)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/IR/
ConstantRange.cpp 668 auto BW = getBitWidth();
669 APInt Min = APInt::getMinValue(BW).zextOrSelf(ResultBitWidth);
670 APInt Max = APInt::getMaxValue(BW).zextOrSelf(ResultBitWidth);
675 auto BW = getBitWidth();
676 APInt SMin = APInt::getSignedMinValue(BW).sextOrSelf(ResultBitWidth);
677 APInt SMax = APInt::getSignedMaxValue(BW).sextOrSelf(ResultBitWidth);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
Float2Int.cpp 49 MaxIntegerBW("float2int-max-integer-bw", cl::init(64), cl::Hidden,
206 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits();
207 auto Input = ConstantRange::getFull(BW);
ConstantHoisting.cpp 530 unsigned BW = V1.getBitWidth() > V2.getBitWidth() ?
539 return APInt(BW, Diff, true);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
LibCallsShrinkWrap.cpp 455 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits();
457 if (BW == 8)
459 else if (BW == 16)
461 else if (BW == 32)
  /src/external/gpl3/binutils/dist/opcodes/
msp430-decode.c 96 #define BW(x) msp430->size = (x ? 8 : 16)
2159 opcode:4 sreg:4 Ad:1 BW:1 As:2 Dreg:4
2162 opcode:9 BW:1 Ad:2 DSreg:4
  /src/external/gpl3/binutils.old/dist/opcodes/
msp430-decode.c 96 #define BW(x) msp430->size = (x ? 8 : 16)
2159 opcode:4 sreg:4 Ad:1 BW:1 As:2 Dreg:4
2162 opcode:9 BW:1 Ad:2 DSreg:4
  /src/external/gpl3/gdb.old/dist/opcodes/
msp430-decode.c 96 #define BW(x) msp430->size = (x ? 8 : 16)
2159 opcode:4 sreg:4 Ad:1 BW:1 As:2 Dreg:4
2162 opcode:9 BW:1 Ad:2 DSreg:4
  /src/external/gpl3/gdb/dist/opcodes/
msp430-decode.c 96 #define BW(x) msp430->size = (x ? 8 : 16)
2159 opcode:4 sreg:4 Ad:1 BW:1 As:2 Dreg:4
2162 opcode:9 BW:1 Ad:2 DSreg:4
  /src/sys/arch/arm/imx/
imxuart.c 281 #define BW BUS_SPACE_BARRIER_WRITE
2167 IMXUART_BARRIER(regsp, BR | BW);
  /src/sys/arch/arm/s3c2xx0/
sscom.c 249 #define BW BUS_SPACE_BARRIER_WRITE
1967 SSCOM_BARRIER(sscomconstag, sscomconsioh, BR | BW);
2042 SSCOM_BARRIER(sscom_kgdb_iot, sscom_kgdb_ioh, BR | BW);
  /src/sys/arch/evbarm/dev/
plcom.c 261 #define BW BUS_SPACE_BARRIER_WRITE
2079 PLCOM_BARRIER(pi, BR | BW);
2391 PLCOM_BARRIER(pi, BR | BW);
2465 PLCOM_BARRIER(pi, BR | BW);
  /src/sys/dev/ic/
com.c 293 #define BW BUS_SPACE_BARRIER_WRITE
2770 COM_BARRIER(regsp, BR | BW);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 983 unsigned BW = VT.getScalarSizeInBits();
985 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
1267 unsigned BW = VT.getScalarSizeInBits();
1268 assert((BW == 64 || BW == 32) &&
1271 SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT);
1276 uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF;
1281 DAG.getConstantFP(1ULL << (BW / 2), DL, Node->getValueType(0));
  /src/sys/arch/arm/xilinx/
zynq_uart.c 360 #define BW BUS_SPACE_BARRIER_WRITE
1942 ZYNQUART_BARRIER(regsp, BR | BW);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 2259 unsigned BW = VT.getSizeInBits();
2260 if (BW > 64)
2311 TestBit = BW - 1;
2319 if (cast<ConstantInt>(RHS)->getValue() != APInt(BW, -1, true))
2322 TestBit = BW - 1;
2335 bool Is64Bit = BW == 64;
2346 if (BW == 64 && !Is64Bit)
2349 if ((BW < 32) && !IsBitTest)
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 1166 uint64_t BW = DL.getIndexSizeInBits(0u);
1168 return Range <= BW;
  /src/external/apache2/llvm/dist/clang/lib/Sema/
SemaDecl.cpp 17166 Expr * BW = IntegerLiteral::Create(Context, Zero, Context.IntTy, DeclLoc);
17173 ObjCIvarDecl::Private, BW,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 5389 // Check that (every element of) Reg is undef or not an exact multiple of BW.
5391 Register Reg, unsigned BW) {
5397 return !CI || CI->getValue().urem(BW) != 0;
5411 unsigned BW = Ty.getScalarSizeInBits();
5413 if (!isPowerOf2_32(BW))
5419 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) {
5453 const unsigned BW = Ty.getScalarSizeInBits();
5460 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) {
5461 // fshl: X << C | Y >> (BW - C)
5462 // fshr: X << (BW - C) | Y >>
    [all...]

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