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    Searched defs:Bank (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsRegisterBankInfo.cpp 325 // Determine InstType from register bank of phys register that is
373 const RegisterBank *Bank =
376 if (Bank == &Mips::FPRBRegBank)
378 else if (Bank == &Mips::GPRBRegBank)
381 llvm_unreachable("Unsupported register bank.\n");
542 // Use default handling for PHI, i.e. set reg bank of def operand to match
551 const RegisterBankInfo::ValueMapping *Bank = getFprbMapping(Op0Size);
553 {Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank});
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  /src/sys/dev/acpi/
apei_cper.h 128 uint16_t Bank;
181 "b\006" "BANK\0" \
199 enum { /* struct cper_memory_error::Bank */
  /src/external/gpl3/gdb.old/dist/sim/arm/
armdefs.h 90 ARMword Bank; /* the current register bank */
218 * Mode and Bank Constants *
249 #define BANK_CAN_ACCESS_SPSR(bank) \
250 ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.cpp 14 /// AMDGPU has unique register bank constraints that require special high level
16 /// VGPR (vector), and SGPR (scalar). Additionally the VCC register bank is a
17 /// sort of pseudo-register bank needed to represent SGPRs used in a vector
18 /// boolean context. There is also the AGPR bank, which is a special purpose
19 /// physical register bank present on some subtargets.
32 /// register. These are represented with the VCC bank. During selection, we need
34 /// bank. To distinguish whether an SGPR should use the SGPR or VCC register
35 /// bank, we need to know the use context type. An SGPR s1 value always means a
36 /// VCC bank value, otherwise it will be the SGPR bank. A scalar compare set
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