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    Searched defs:BaseOpc (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 701 int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm
713 BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm
736 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) {
754 if (BaseOpc == ARM::tADDrSPi) {
756 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
761 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
767 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FastISel.cpp 2880 unsigned BaseOpc, CondCode;
2884 BaseOpc = ISD::ADD; CondCode = X86::COND_O; break;
2886 BaseOpc = ISD::ADD; CondCode = X86::COND_B; break;
2888 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break;
2890 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break;
2892 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break;
2894 BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break;
2909 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) &&
2913 bool IsDec = BaseOpc == ISD::SUB
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorTypes.cpp 881 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(N->getOpcode());
884 return DAG.getNode(BaseOpc, SDLoc(N), N->getValueType(0),
5072 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc);
5073 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags);
5098 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc);
5099 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 3563 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Op.getOpcode());
3572 Vec = DAG.getNode(BaseOpc, DL, VecEVT, Lo, Hi);
3598 DAG.getNeutralElement(BaseOpc, DL, VecEltVT, SDNodeFlags());

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