HomeSort by: relevance | last modified time | path
    Searched defs:Br (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCPreEmitPeephole.cpp 483 MachineInstr *Br = &*I;
484 if (Br->getOpcode() != PPC::BC && Br->getOpcode() != PPC::BCn)
487 Register CRBit = Br->getOperand(0).getReg();
490 MachineBasicBlock::reverse_iterator It = Br, Er = MBB.rend();
505 if ((Br->getOpcode() == PPC::BCn && CRSetOp == PPC::CRSET) ||
506 (Br->getOpcode() == PPC::BC && CRSetOp == PPC::CRUNSET)) {
508 InstrsToErase.push_back(Br);
509 MBB.removeSuccessor(Br->getOperand(1).getMBB());
514 MachineBasicBlock::iterator It = Br, Er = MBB.end()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
ConstraintElimination.cpp 271 auto *Br = dyn_cast<BranchInst>(BB.getTerminator());
272 if (!Br || !Br->isConditional())
288 if (match(Br->getCondition(), m_LogicalOr(m_Value(Op0), m_Value(Op1))) &&
290 BasicBlock *FalseSuccessor = Br->getSuccessor(1);
303 if (match(Br->getCondition(), m_LogicalAnd(m_Value(Op0), m_Value(Op1))) &&
305 BasicBlock *TrueSuccessor = Br->getSuccessor(0);
315 auto *CmpI = dyn_cast<CmpInst>(Br->getCondition());
318 if (CanAdd(Br->getSuccessor(0)))
319 WorkList.emplace_back(DT.getNode(Br->getSuccessor(0)), CmpI, false)
    [all...]
LoopFlatten.cpp 307 BranchInst *Br = dyn_cast<BranchInst>(&I);
308 if (Br && Br->isUnconditional() &&
309 Br->getSuccessor(0) == FI.InnerLoop->getHeader())
StructurizeCFG.cpp 959 auto Br = dyn_cast<BranchInst>(E->getEntry()->getTerminator());
960 if (!Br || !Br->isConditional())
963 if (!DA.isUniform(Br))
969 LLVM_DEBUG(dbgs() << "BB: " << Br->getParent()->getName()
982 auto Br = dyn_cast<BranchInst>(BB->getTerminator());
983 if (!Br || !Br->isConditional())
986 if (!Br->getMetadata(UniformMDKindID)) {
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
VPlanHCFGBuilder.cpp 205 if (auto *Br = dyn_cast<BranchInst>(Inst)) {
208 if (Br->isConditional())
209 getOrCreateVPOperand(Br->getCondition());
298 auto *Br = cast<BranchInst>(TI);
299 Value *BrCond = Br->getCondition();
LoopVectorizationLegality.cpp 435 auto *Br = dyn_cast<BranchInst>(BB->getTerminator());
436 if (!Br) {
452 if (!EnableVPlanPredication && Br && Br->isConditional() &&
453 !TheLoop->isLoopInvariant(Br->getCondition()) &&
454 !LI->isLoopHeader(Br->getSuccessor(0)) &&
455 !LI->isLoopHeader(Br->getSuccessor(1))) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsBranchExpansion.cpp 129 MachineInstr *Br = nullptr;
156 int64_t computeOffset(const MachineInstr *Br);
158 void replaceBranch(MachineBasicBlock &MBB, Iter Br, const DebugLoc &DL,
223 /// Iterate over list of Br's operands and search for a MachineBasicBlock
225 static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) {
226 for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
227 const MachineOperand &MO = Br.getOperand(I);
304 int64_t MipsBranchExpansion::computeOffset(const MachineInstr *Br) {
306 int ThisMBB = Br->getParent()->getNumber();
307 int TargetMBB = getTargetMBB(*Br)->getNumber()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyFastISel.cpp 1301 const auto *Br = cast<BranchInst>(I);
1302 if (Br->isUnconditional()) {
1303 MachineBasicBlock *MSucc = FuncInfo.MBBMap[Br->getSuccessor(0)];
1304 fastEmitBranch(MSucc, Br->getDebugLoc());
1308 MachineBasicBlock *TBB = FuncInfo.MBBMap[Br->getSuccessor(0)];
1309 MachineBasicBlock *FBB = FuncInfo.MBBMap[Br->getSuccessor(1)];
1312 unsigned CondReg = getRegForI1Value(Br->getCondition(), Not);
1324 finishCondBranch(Br->getParent(), TBB, FBB);
1416 case Instruction::Br:
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
InlineFunction.cpp 2522 Instruction *Br = OrigBB->getTerminator();
2523 assert(Br && Br->getOpcode() == Instruction::Br &&
2525 Br->setOperand(0, &*FirstNewBlock);
2617 assert(cast<BranchInst>(Br)->isUnconditional() && "splitBasicBlock broken!");
2618 BasicBlock *CalleeEntry = cast<BranchInst>(Br)->getSuccessor(0);
2623 OrigBB->getInstList().splice(Br->getIterator(), CalleeEntry->getInstList());
2626 OrigBB->getInstList().erase(Br);
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
IRBuilder.h 966 /// Create an unconditional 'br label X' instruction.
971 /// Create a conditional 'br Cond, TrueDest, FalseDest'
980 /// Create a conditional 'br Cond, TrueDest, FalseDest'
984 BranchInst *Br = BranchInst::Create(True, False, Cond);
988 Br->copyMetadata(*MDSrc, makeArrayRef(&WL[0], 4));
990 return Insert(Br);
  /src/external/apache2/llvm/dist/llvm/lib/Frontend/OpenMP/
OMPIRBuilder.cpp 1468 auto *Br = cast<BranchInst>(Term);
1469 Br->setSuccessor(0, OuterCond);
1504 auto *Br = cast<BranchInst>(Term);
1505 assert(!Br->isConditional() &&
1507 BasicBlock *Succ = Br->getSuccessor(0);
1509 Br->setSuccessor(0, Target);
  /src/external/apache2/llvm/dist/llvm/bindings/go/llvm/
ir.go 134 Br Opcode = C.LLVMBr
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 1693 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2351 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2446 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, getControlRoot(),
2521 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2583 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2590 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, CopyTo,
2705 SDValue Br = DAG.getNode(ISD::BR, dl,
2709 DAG.setRoot(Br);
2800 Root = DAG.getNode(ISD::BR, dl, MVT::Other, Root, DAG.getBasicBlock(MBB))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 4162 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
4164 Br->getOperand(1).setIsUndef(true); // read undef SCC
4969 /// last parameter, also switches branch target with BR if the need arise
4976 SDNode *BR = nullptr;
4985 // Get the target from BR if we don't negate the condition
4986 BR = findUser(BRCOND, ISD::BR);
4987 assert(BR && "brcond missing unconditional branch user");
4988 Target = BR->getOperand(1);
5027 if (BR) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 16636 assert((N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BR)
16637 && "expected single br user");
16638 SDNode *Br = *N->use_begin();
16639 SDValue OtherTarget = Br->getOperand(1);
16642 auto UpdateUncondBr = [](SDNode *Br, SDValue Dest, SelectionDAG &DAG) {
16643 SDValue NewBrOps[] = { Br->getOperand(0), Dest };
16644 SDValue NewBr = DAG.getNode(ISD::BR, SDLoc(Br), MVT::Other, NewBrOps);
16645 DAG.ReplaceAllUsesOfValueWith(SDValue(Br, 0), NewBr);
16657 // basic block target: the target of the proceeding br
    [all...]

Completed in 57 milliseconds