1 /* $NetBSD: cpu.h,v 1.30 2026/03/24 15:56:59 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 39 */ 40 41 #ifndef _M68K_CPU_H_ 42 #define _M68K_CPU_H_ 43 44 #if defined(_KERNEL_OPT) 45 #include "opt_m68k_arch.h" /* XXX Should not do this here. */ 46 #endif 47 48 /* 49 * Exported definitions common to Motorola m68k-based ports. 50 */ 51 52 /* 53 * XXX The remaining contents of this file should be split out 54 * XXX into separate files (like m68k.h) and then this file 55 * XXX should go away. Furthermore, most of the stuff defined 56 * XXX here does NOT belong in <machine/cpu.h>, and the ports 57 * XXX using this file should remove <m68k/cpu.h> from there. 58 */ 59 60 #include <m68k/m68k.h> 61 62 /* XXX - Move this stuff into <m68k/cacr.h> maybe? */ 63 64 /* fields in the 68020 cache control register */ 65 #define IC_ENABLE 0x0001 /* enable instruction cache */ 66 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 67 #define IC_CE 0x0004 /* clear instruction cache entry */ 68 #define IC_CLR 0x0008 /* clear entire instruction cache */ 69 70 /* additional fields in the 68030 cache control register */ 71 #define IC_BE 0x0010 /* instruction burst enable */ 72 #define DC_ENABLE 0x0100 /* data cache enable */ 73 #define DC_FREEZE 0x0200 /* data cache freeze */ 74 #define DC_CE 0x0400 /* clear data cache entry */ 75 #define DC_CLR 0x0800 /* clear entire data cache */ 76 #define DC_BE 0x1000 /* data burst enable */ 77 #define DC_WA 0x2000 /* write allocate */ 78 79 /* fields in the 68040 cache control register */ 80 #define IC40_ENABLE 0x00008000 /* instruction cache enable bit */ 81 #define DC40_ENABLE 0x80000000 /* data cache enable bit */ 82 83 /* additional fields in the 68060 cache control register */ 84 #define DC60_NAD 0x40000000 /* no allocate mode, data cache */ 85 #define DC60_ESB 0x20000000 /* enable store buffer */ 86 #define DC60_DPI 0x10000000 /* disable CPUSH invalidation */ 87 #define DC60_FOC 0x08000000 /* four kB data cache mode (else 8) */ 88 89 #define IC60_EBC 0x00800000 /* enable branch cache */ 90 #define IC60_CABC 0x00400000 /* clear all branch cache entries */ 91 #define IC60_CUBC 0x00200000 /* clear user branch cache entries */ 92 93 #define IC60_NAI 0x00004000 /* no allocate mode, instr. cache */ 94 #define IC60_FIC 0x00002000 /* four kB instr. cache (else 8) */ 95 96 #define CACHE2030_ON (DC_WA|DC_CLR|DC_ENABLE|IC_CLR|IC_ENABLE) 97 #define CACHE2030_BE (DC_BE|IC_BE) 98 99 #define _IC_CLEAR(x) ((x) & ~DC_CLR) 100 #define _DC_CLEAR(x) ((x) & ~IC_CLR) 101 102 #ifdef _KERNEL 103 #ifdef __HAVE_M68K_DYNAMIC_CACR 104 extern int cacr_cache_on; 105 extern int cacr_cache_clr; 106 extern int cacr_ic_clr; 107 extern int cacr_dc_clr; 108 109 #define CACHE_ON cacr_cache_on 110 #define CACHE_CLR cacr_cache_clr 111 #define IC_CLEAR cacr_ic_clr 112 #define DC_CLEAR cacr_dc_clr 113 #else 114 #define CACHE_ON (CACHE2030_ON | CACHE2030_BE) 115 #define CACHE_CLR (CACHE_ON) 116 #define IC_CLEAR _IC_CLEAR(CACHE_CLR) 117 #define DC_CLEAR _DC_CLEAR(CACHE_CLR) 118 #endif /* __HAVE_M68K_DYNAMIC_CACR */ 119 #endif /* _KERNEL */ 120 121 #define CACHE_OFF (DC_CLR|IC_CLR) 122 123 #define CACHE40_ON (IC40_ENABLE|DC40_ENABLE) 124 #define CACHE40_OFF (0x00000000) 125 126 #define CACHE60_ON (CACHE40_ON |IC60_CABC|IC60_EBC|DC60_ESB) 127 #define CACHE60_OFF (CACHE40_OFF|IC60_CABC) 128 129 #define CACHELINE_SIZE 16 130 #define CACHELINE_MASK (CACHELINE_SIZE - 1) 131 132 /* CTL_MACHDEP definitions. (Common to all m68k ports.) */ 133 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 134 #define CPU_ROOT_DEVICE 2 /* string: root device name */ 135 #define CPU_BOOTED_KERNEL 3 /* string: booted kernel name */ 136 #define CPU_BROKEN_RMC 4 /* bool: has non-working /RMC */ 137 138 #if defined(_KERNEL) || defined(_KMEMUSER) 139 #include <sys/cpu_data.h> 140 141 struct cpu_info { 142 struct cpu_data ci_data; /* MI per-cpu data */ 143 cpuid_t ci_cpuid; 144 int ci_mtx_count; 145 int ci_mtx_oldspl; 146 volatile int ci_want_resched; 147 volatile int ci_idepth; 148 struct lwp *ci_onproc; /* current user LWP / kthread */ 149 }; 150 #endif /* _KERNEL || _KMEMUSER */ 151 152 #ifdef _KERNEL 153 extern struct cpu_info cpu_info_store; 154 155 struct proc; 156 void cpu_proc_fork(struct proc *, struct proc *); 157 158 #define curcpu() (&cpu_info_store) 159 160 /* 161 * definitions of cpu-dependent requirements 162 * referenced in generic code 163 */ 164 #define cpu_number() 0 165 166 #define LWP_PC(l) (((struct trapframe *)((l)->l_md.md_regs))->tf_pc) 167 168 /* 169 * Arguments to hardclock and gatherstats encapsulate the previous 170 * machine state in an opaque clockframe. On the m68k platforms, we use 171 * what the interrupt stub puts on the stack before calling C code. 172 */ 173 struct clockframe { 174 /* regs saved on the stack by the interrupt stub */ 175 u_int cf_regs[4]; /* d0,d1,a0,a1 */ 176 /* hardware frame */ 177 u_short cf_sr; /* sr at time of interrupt */ 178 u_long cf_pc; /* pc at time of interrupt */ 179 u_short cf_vo; /* vector offset (4-word HW frame) */ 180 } __attribute__((__packed__)); 181 182 #define CLKF_USERMODE(framep) (((framep)->cf_sr & PSL_S) == 0) 183 #define CLKF_PC(framep) ((framep)->cf_pc) 184 185 #if 0 186 /* 187 * We can determine if we were previously in an interrupt context 188 * if we were running on the interrupt stack (as opposed to the 189 * "master" stack). 190 * 191 * XXX Actually, we can't, because we don't use the master stack 192 * XXX right now. 193 * 194 * (Actually, it's unlikely that we'll ever use the master stack in NetBSD. 195 * It would complicate the spl*() functions considerably and it just doesn't 196 * seem like a good trade-off for what seems like extremely marginal gains. 197 * So, just blissfully run the kernel on the interrupt stack all the time, 198 * and it's been that way for >30 years and no one has really complained 199 * about it.) 200 */ 201 #define CLKF_INTR(framep) (((framep)->cf_sr & PSL_M) == 0) 202 #else 203 /* 204 * The clock interrupt handler can determine if it's a nested 205 * interrupt by checking for intr_depth > 1. 206 * (Remember, the clock interrupt handler itself will cause the 207 * depth counter to be incremented). 208 */ 209 extern volatile unsigned int intr_depth; 210 #define CLKF_INTR(framep) (intr_depth > 1) 211 #endif 212 213 #ifndef __HAVE_M68K_HW_AST 214 #define cpu_set_hw_ast(l) __nothing 215 #endif 216 217 extern volatile int astpending; 218 #define cpu_set_ast(l) \ 219 do { \ 220 __USE(l); astpending = 1; cpu_set_hw_ast(l); \ 221 } while (/*CONSTCOND*/0) 222 223 /* 224 * Preempt the current process if in interrupt from user mode, 225 * or after the current trap/syscall if in system mode. 226 */ 227 #define cpu_need_resched(ci, l, flags) \ 228 do { \ 229 __USE(ci); __USE(flags); cpu_set_ast(l); \ 230 } while (/*CONSTCOND*/0) 231 232 /* 233 * Give a profiling tick to the current process when the user profiling 234 * buffer pages are invalid. On m68k, request an ast to send us through 235 * trap, marking the proc as needing a profiling tick. 236 */ 237 #define cpu_need_proftick(l) \ 238 do { \ 239 (l)->l_pflag |= LP_OWEUPC; cpu_set_ast(l); \ 240 } while (/*CONSTCOND*/0) 241 242 /* 243 * Notify the current process (p) that it has a signal pending, 244 * process as soon as possible. 245 */ 246 #define cpu_signotify(l) cpu_set_ast(l) 247 248 #endif /* _KERNEL */ 249 250 #endif /* _M68K_CPU_H_ */ 251
Indexes created Fri Jun 12 00:25:51 UTC 2026