1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the SystemZ implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H 14 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H 15 16 #include "SystemZ.h" 17 #include "SystemZRegisterInfo.h" 18 #include "llvm/ADT/ArrayRef.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include <cstdint> 24 25 #define GET_INSTRINFO_HEADER 26 #include "SystemZGenInstrInfo.inc" 27 28 namespace llvm { 29 30 class SystemZSubtarget; 31 32 namespace SystemZII { 33 34 enum { 35 // See comments in SystemZInstrFormats.td. 36 SimpleBDXLoad = (1 << 0), 37 SimpleBDXStore = (1 << 1), 38 Has20BitOffset = (1 << 2), 39 HasIndex = (1 << 3), 40 Is128Bit = (1 << 4), 41 AccessSizeMask = (31 << 5), 42 AccessSizeShift = 5, 43 CCValuesMask = (15 << 10), 44 CCValuesShift = 10, 45 CompareZeroCCMaskMask = (15 << 14), 46 CompareZeroCCMaskShift = 14, 47 CCMaskFirst = (1 << 18), 48 CCMaskLast = (1 << 19), 49 IsLogical = (1 << 20), 50 CCIfNoSignedWrap = (1 << 21) 51 }; 52 53 static inline unsigned getAccessSize(unsigned int Flags) { 54 return (Flags & AccessSizeMask) >> AccessSizeShift; 55 } 56 57 static inline unsigned getCCValues(unsigned int Flags) { 58 return (Flags & CCValuesMask) >> CCValuesShift; 59 } 60 61 static inline unsigned getCompareZeroCCMask(unsigned int Flags) { 62 return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift; 63 } 64 65 // SystemZ MachineOperand target flags. 66 enum { 67 // Masks out the bits for the access model. 68 MO_SYMBOL_MODIFIER = (3 << 0), 69 70 // @GOT (aka @GOTENT) 71 MO_GOT = (1 << 0), 72 73 // @INDNTPOFF 74 MO_INDNTPOFF = (2 << 0) 75 }; 76 77 // Classifies a branch. 78 enum BranchType { 79 // An instruction that branches on the current value of CC. 80 BranchNormal, 81 82 // An instruction that peforms a 32-bit signed comparison and branches 83 // on the result. 84 BranchC, 85 86 // An instruction that peforms a 32-bit unsigned comparison and branches 87 // on the result. 88 BranchCL, 89 90 // An instruction that peforms a 64-bit signed comparison and branches 91 // on the result. 92 BranchCG, 93 94 // An instruction that peforms a 64-bit unsigned comparison and branches 95 // on the result. 96 BranchCLG, 97 98 // An instruction that decrements a 32-bit register and branches if 99 // the result is nonzero. 100 BranchCT, 101 102 // An instruction that decrements a 64-bit register and branches if 103 // the result is nonzero. 104 BranchCTG, 105 106 // An instruction representing an asm goto statement. 107 AsmGoto 108 }; 109 110 // Information about a branch instruction. 111 class Branch { 112 // The target of the branch. In case of INLINEASM_BR, this is nullptr. 113 const MachineOperand *Target; 114 115 public: 116 // The type of the branch. 117 BranchType Type; 118 119 // CCMASK_<N> is set if CC might be equal to N. 120 unsigned CCValid; 121 122 // CCMASK_<N> is set if the branch should be taken when CC == N. 123 unsigned CCMask; 124 125 Branch(BranchType type, unsigned ccValid, unsigned ccMask, 126 const MachineOperand *target) 127 : Target(target), Type(type), CCValid(ccValid), CCMask(ccMask) {} 128 129 bool isIndirect() { return Target != nullptr && Target->isReg(); } 130 bool hasMBBTarget() { return Target != nullptr && Target->isMBB(); } 131 MachineBasicBlock *getMBBTarget() { 132 return hasMBBTarget() ? Target->getMBB() : nullptr; 133 } 134 }; 135 136 // Kinds of fused compares in compare-and-* instructions. Together with type 137 // of the converted compare, this identifies the compare-and-* 138 // instruction. 139 enum FusedCompareType { 140 // Relative branch - CRJ etc. 141 CompareAndBranch, 142 143 // Indirect branch, used for return - CRBReturn etc. 144 CompareAndReturn, 145 146 // Indirect branch, used for sibcall - CRBCall etc. 147 CompareAndSibcall, 148 149 // Trap 150 CompareAndTrap 151 }; 152 153 } // end namespace SystemZII 154 155 namespace SystemZ { 156 int getTwoOperandOpcode(uint16_t Opcode); 157 int getTargetMemOpcode(uint16_t Opcode); 158 159 // Return a version of comparison CC mask CCMask in which the LT and GT 160 // actions are swapped. 161 unsigned reverseCCMask(unsigned CCMask); 162 163 // Create a new basic block after MBB. 164 MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB); 165 // Split MBB after MI and return the new block (the one that contains 166 // instructions after MI). 167 MachineBasicBlock *splitBlockAfter(MachineBasicBlock::iterator MI, 168 MachineBasicBlock *MBB); 169 // Split MBB before MI and return the new block (the one that contains MI). 170 MachineBasicBlock *splitBlockBefore(MachineBasicBlock::iterator MI, 171 MachineBasicBlock *MBB); 172 } 173 174 class SystemZInstrInfo : public SystemZGenInstrInfo { 175 const SystemZRegisterInfo RI; 176 SystemZSubtarget &STI; 177 178 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const; 179 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const; 180 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode, 181 bool ConvertHigh) const; 182 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode, 183 unsigned LowOpcodeK, unsigned HighOpcode) const; 184 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode, 185 unsigned HighOpcode) const; 186 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode, 187 unsigned HighOpcode) const; 188 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode, 189 unsigned Size) const; 190 void expandLoadStackGuard(MachineInstr *MI) const; 191 192 MachineInstrBuilder 193 emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 194 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 195 unsigned LowLowOpcode, unsigned Size, bool KillSrc, 196 bool UndefSrc) const; 197 198 virtual void anchor(); 199 200 protected: 201 /// Commutes the operands in the given instruction by changing the operands 202 /// order and/or changing the instruction's opcode and/or the immediate value 203 /// operand. 204 /// 205 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands 206 /// to be commuted. 207 /// 208 /// Do not call this method for a non-commutable instruction or 209 /// non-commutable operands. 210 /// Even though the instruction is commutable, the method may still 211 /// fail to commute the operands, null pointer is returned in such cases. 212 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 213 unsigned CommuteOpIdx1, 214 unsigned CommuteOpIdx2) const override; 215 216 public: 217 explicit SystemZInstrInfo(SystemZSubtarget &STI); 218 219 // Override TargetInstrInfo. 220 unsigned isLoadFromStackSlot(const MachineInstr &MI, 221 int &FrameIndex) const override; 222 unsigned isStoreToStackSlot(const MachineInstr &MI, 223 int &FrameIndex) const override; 224 bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, 225 int &SrcFrameIndex) const override; 226 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 227 MachineBasicBlock *&FBB, 228 SmallVectorImpl<MachineOperand> &Cond, 229 bool AllowModify) const override; 230 unsigned removeBranch(MachineBasicBlock &MBB, 231 int *BytesRemoved = nullptr) const override; 232 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 233 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 234 const DebugLoc &DL, 235 int *BytesAdded = nullptr) const override; 236 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 237 Register &SrcReg2, int &Mask, int &Value) const override; 238 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 239 Register, Register, Register, int &, int &, 240 int &) const override; 241 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 242 const DebugLoc &DL, Register DstReg, 243 ArrayRef<MachineOperand> Cond, Register TrueReg, 244 Register FalseReg) const override; 245 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 246 MachineRegisterInfo *MRI) const override; 247 bool isPredicable(const MachineInstr &MI) const override; 248 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 249 unsigned ExtraPredCycles, 250 BranchProbability Probability) const override; 251 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 252 unsigned NumCyclesT, unsigned ExtraPredCyclesT, 253 MachineBasicBlock &FMBB, 254 unsigned NumCyclesF, unsigned ExtraPredCyclesF, 255 BranchProbability Probability) const override; 256 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 257 BranchProbability Probability) const override; 258 bool PredicateInstruction(MachineInstr &MI, 259 ArrayRef<MachineOperand> Pred) const override; 260 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 261 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 262 bool KillSrc) const override; 263 void storeRegToStackSlot(MachineBasicBlock &MBB, 264 MachineBasicBlock::iterator MBBI, 265 Register SrcReg, bool isKill, int FrameIndex, 266 const TargetRegisterClass *RC, 267 const TargetRegisterInfo *TRI) const override; 268 void loadRegFromStackSlot(MachineBasicBlock &MBB, 269 MachineBasicBlock::iterator MBBI, 270 Register DestReg, int FrameIdx, 271 const TargetRegisterClass *RC, 272 const TargetRegisterInfo *TRI) const override; 273 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 274 MachineInstr &MI, 275 LiveVariables *LV) const override; 276 MachineInstr * 277 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 278 ArrayRef<unsigned> Ops, 279 MachineBasicBlock::iterator InsertPt, int FrameIndex, 280 LiveIntervals *LIS = nullptr, 281 VirtRegMap *VRM = nullptr) const override; 282 MachineInstr *foldMemoryOperandImpl( 283 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 284 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, 285 LiveIntervals *LIS = nullptr) const override; 286 bool expandPostRAPseudo(MachineInstr &MBBI) const override; 287 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 288 override; 289 290 // Return the SystemZRegisterInfo, which this class owns. 291 const SystemZRegisterInfo &getRegisterInfo() const { return RI; } 292 293 // Return the size in bytes of MI. 294 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 295 296 // Return true if MI is a conditional or unconditional branch. 297 // When returning true, set Cond to the mask of condition-code 298 // values on which the instruction will branch, and set Target 299 // to the operand that contains the branch target. This target 300 // can be a register or a basic block. 301 SystemZII::Branch getBranchInfo(const MachineInstr &MI) const; 302 303 // Get the load and store opcodes for a given register class. 304 void getLoadStoreOpcodes(const TargetRegisterClass *RC, 305 unsigned &LoadOpcode, unsigned &StoreOpcode) const; 306 307 // Opcode is the opcode of an instruction that has an address operand, 308 // and the caller wants to perform that instruction's operation on an 309 // address that has displacement Offset. Return the opcode of a suitable 310 // instruction (which might be Opcode itself) or 0 if no such instruction 311 // exists. 312 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const; 313 314 // If Opcode is a load instruction that has a LOAD AND TEST form, 315 // return the opcode for the testing form, otherwise return 0. 316 unsigned getLoadAndTest(unsigned Opcode) const; 317 318 // Return true if ROTATE AND ... SELECTED BITS can be used to select bits 319 // Mask of the R2 operand, given that only the low BitSize bits of Mask are 320 // significant. Set Start and End to the I3 and I4 operands if so. 321 bool isRxSBGMask(uint64_t Mask, unsigned BitSize, 322 unsigned &Start, unsigned &End) const; 323 324 // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND * 325 // operation exists, return the opcode for the latter, otherwise return 0. 326 // MI, if nonnull, is the compare instruction. 327 unsigned getFusedCompare(unsigned Opcode, 328 SystemZII::FusedCompareType Type, 329 const MachineInstr *MI = nullptr) const; 330 331 // Try to find all CC users of the compare instruction (MBBI) and update 332 // all of them to maintain equivalent behavior after swapping the compare 333 // operands. Return false if not all users can be conclusively found and 334 // handled. The compare instruction is *not* changed. 335 bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const; 336 337 // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP 338 // operation exists, returh the opcode for the latter, otherwise return 0. 339 unsigned getLoadAndTrap(unsigned Opcode) const; 340 341 // Emit code before MBBI in MI to move immediate value Value into 342 // physical register Reg. 343 void loadImmediate(MachineBasicBlock &MBB, 344 MachineBasicBlock::iterator MBBI, 345 unsigned Reg, uint64_t Value) const; 346 347 // Perform target specific instruction verification. 348 bool verifyInstruction(const MachineInstr &MI, 349 StringRef &ErrInfo) const override; 350 351 // Sometimes, it is possible for the target to tell, even without 352 // aliasing information, that two MIs access different memory 353 // addresses. This function returns true if two MIs access different 354 // memory addresses and false otherwise. 355 bool 356 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 357 const MachineInstr &MIb) const override; 358 }; 359 360 } // end namespace llvm 361 362 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H 363
Indexes created Tue Feb 24 08:35:24 UTC 2026