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    Searched defs:CCReg (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZSelectionDAGInfo.cpp 170 static SDValue addIPMSequence(const SDLoc &DL, SDValue CCReg,
172 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, CCReg);
188 SDValue CCReg = emitCLC(DAG, DL, Chain, Src2, Src1, Bytes);
189 Chain = CCReg.getValue(1);
190 return std::make_pair(addIPMSequence(DL, CCReg, DAG), Chain);
208 SDValue CCReg = End.getValue(1);
216 DAG.getTargetConstant(SystemZ::CCMASK_SRST_FOUND, DL, MVT::i32), CCReg};
239 SDValue CCReg = Unused.getValue(1);
241 return std::make_pair(addIPMSequence(DL, CCReg, DAG), Chain);
SystemZISelDAGToDAG.cpp 1890 SDValue CCReg = Node->getOperand(4);
1892 SDValue Result = CurDAG->getNode(SystemZISD::IPM, DL, MVT::i32, CCReg);
SystemZISelLowering.cpp 2698 // Return an i32 value that is 1 if the CC value produced by CCReg is
2701 static SDValue emitSETCC(SelectionDAG &DAG, const SDLoc &DL, SDValue CCReg,
2706 DAG.getTargetConstant(CCMask, DL, MVT::i32), CCReg};
2926 SDValue CCReg = emitCmp(DAG, DL, C);
2927 return emitSETCC(DAG, DL, CCReg, C.CCValid, C.CCMask);
2946 SDValue CCReg = emitCmp(DAG, DL, C);
2947 CCReg->setFlags(Op->getFlags());
2948 SDValue Result = emitSETCC(DAG, DL, CCReg, C.CCValid, C.CCMask);
2949 SDValue Ops[2] = { Result, CCReg.getValue(1) };
2961 SDValue CCReg = emitCmp(DAG, DL, C)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/
PPCInstPrinter.cpp 489 unsigned CCReg = MI->getOperand(OpNo).getReg();
491 switch (CCReg) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMConstantIslandPass.cpp 1703 Register CCReg = MI->getOperand(2).getReg();
1760 .addMBB(NextBB).addImm(CC).addReg(CCReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 1038 Register CCReg = I.getOperand(0).getReg();
1039 if (!isVCC(CCReg, *MRI)) {
1046 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg)
1050 RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI);
1772 Register CCReg = CCOp.getReg();
1773 if (!isVCC(CCReg, *MRI)) {
1777 .addReg(CCReg);
1782 if (!MRI->getRegClassOrNull(CCReg))
1783 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI));

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