1 /* $NetBSD: rs780d.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __RS780D_H__ 26 #define __RS780D_H__ 27 28 #define CG_SPLL_FUNC_CNTL 0x600 29 # define SPLL_RESET (1 << 0) 30 # define SPLL_SLEEP (1 << 1) 31 # define SPLL_REF_DIV(x) ((x) << 2) 32 # define SPLL_REF_DIV_MASK (7 << 2) 33 # define SPLL_REF_DIV_SHIFT 2 34 # define SPLL_FB_DIV(x) ((x) << 5) 35 # define SPLL_FB_DIV_MASK (0xff << 2) 36 # define SPLL_FB_DIV_SHIFT 2 37 # define SPLL_PULSEEN (1 << 13) 38 # define SPLL_PULSENUM(x) ((x) << 14) 39 # define SPLL_PULSENUM_MASK (3 << 14) 40 # define SPLL_SW_HILEN(x) ((x) << 16) 41 # define SPLL_SW_HILEN_MASK (0xf << 16) 42 # define SPLL_SW_HILEN_SHIFT 16 43 # define SPLL_SW_LOLEN(x) ((x) << 20) 44 # define SPLL_SW_LOLEN_MASK (0xf << 20) 45 # define SPLL_SW_LOLEN_SHIFT 20 46 # define SPLL_DIVEN (1 << 24) 47 # define SPLL_BYPASS_EN (1 << 25) 48 # define SPLL_CHG_STATUS (1 << 29) 49 # define SPLL_CTLREQ (1 << 30) 50 # define SPLL_CTLACK (1 << 31) 51 52 /* RS780/RS880 PM */ 53 #define FVTHROT_CNTRL_REG 0x3000 54 #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0) 55 #define MINIMUM_CIP(x) ((x) << 1) 56 #define MINIMUM_CIP_SHIFT 1 57 #define MINIMUM_CIP_MASK 0x1fffffe 58 #define REFRESH_RATE_DIVISOR(x) ((x) << 25) 59 #define REFRESH_RATE_DIVISOR_SHIFT 25 60 #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25) 61 #define ENABLE_FV_THROT (1 << 27) 62 #define ENABLE_FV_UPDATE (1 << 28) 63 #define TREND_SEL_MODE (1 << 29) 64 #define FORCE_TREND_SEL (1 << 30) 65 #define ENABLE_FV_THROT_IO (1 << 31) 66 #define FVTHROT_TARGET_REG 0x3004 67 #define TARGET_IDLE_COUNT(x) ((x) << 0) 68 #define TARGET_IDLE_COUNT_MASK 0xffffff 69 #define TARGET_IDLE_COUNT_SHIFT 0 70 #define FVTHROT_CB1 0x3008 71 #define FVTHROT_CB2 0x300c 72 #define FVTHROT_CB3 0x3010 73 #define FVTHROT_CB4 0x3014 74 #define FVTHROT_UTC0 0x3018 75 #define FVTHROT_UTC1 0x301c 76 #define FVTHROT_UTC2 0x3020 77 #define FVTHROT_UTC3 0x3024 78 #define FVTHROT_UTC4 0x3028 79 #define FVTHROT_DTC0 0x302c 80 #define FVTHROT_DTC1 0x3030 81 #define FVTHROT_DTC2 0x3034 82 #define FVTHROT_DTC3 0x3038 83 #define FVTHROT_DTC4 0x303c 84 #define FVTHROT_FBDIV_REG0 0x3040 85 #define MIN_FEEDBACK_DIV(x) ((x) << 0) 86 #define MIN_FEEDBACK_DIV_MASK 0xfff 87 #define MIN_FEEDBACK_DIV_SHIFT 0 88 #define MAX_FEEDBACK_DIV(x) ((x) << 12) 89 #define MAX_FEEDBACK_DIV_MASK (0xfff << 12) 90 #define MAX_FEEDBACK_DIV_SHIFT 12 91 #define FVTHROT_FBDIV_REG1 0x3044 92 #define MAX_FEEDBACK_STEP(x) ((x) << 0) 93 #define MAX_FEEDBACK_STEP_MASK 0xfff 94 #define MAX_FEEDBACK_STEP_SHIFT 0 95 #define STARTING_FEEDBACK_DIV(x) ((x) << 12) 96 #define STARTING_FEEDBACK_DIV_MASK (0xfff << 12) 97 #define STARTING_FEEDBACK_DIV_SHIFT 12 98 #define FORCE_FEEDBACK_DIV (1 << 24) 99 #define FVTHROT_FBDIV_REG2 0x3048 100 #define FORCED_FEEDBACK_DIV(x) ((x) << 0) 101 #define FORCED_FEEDBACK_DIV_MASK 0xfff 102 #define FORCED_FEEDBACK_DIV_SHIFT 0 103 #define FB_DIV_TIMER_VAL(x) ((x) << 12) 104 #define FB_DIV_TIMER_VAL_MASK (0xffff << 12) 105 #define FB_DIV_TIMER_VAL_SHIFT 12 106 #define FVTHROT_FB_US_REG0 0x304c 107 #define FVTHROT_FB_US_REG1 0x3050 108 #define FVTHROT_FB_DS_REG0 0x3054 109 #define FVTHROT_FB_DS_REG1 0x3058 110 #define FVTHROT_PWM_CTRL_REG0 0x305c 111 #define STARTING_PWM_HIGHTIME(x) ((x) << 0) 112 #define STARTING_PWM_HIGHTIME_MASK 0xfff 113 #define STARTING_PWM_HIGHTIME_SHIFT 0 114 #define NUMBER_OF_CYCLES_IN_PERIOD(x) ((x) << 12) 115 #define NUMBER_OF_CYCLES_IN_PERIOD_MASK (0xfff << 12) 116 #define NUMBER_OF_CYCLES_IN_PERIOD_SHIFT 12 117 #define FORCE_STARTING_PWM_HIGHTIME (1 << 24) 118 #define INVERT_PWM_WAVEFORM (1 << 25) 119 #define FVTHROT_PWM_CTRL_REG1 0x3060 120 #define MIN_PWM_HIGHTIME(x) ((x) << 0) 121 #define MIN_PWM_HIGHTIME_MASK 0xfff 122 #define MIN_PWM_HIGHTIME_SHIFT 0 123 #define MAX_PWM_HIGHTIME(x) ((x) << 12) 124 #define MAX_PWM_HIGHTIME_MASK (0xfff << 12) 125 #define MAX_PWM_HIGHTIME_SHIFT 12 126 #define FVTHROT_PWM_US_REG0 0x3064 127 #define FVTHROT_PWM_US_REG1 0x3068 128 #define FVTHROT_PWM_DS_REG0 0x306c 129 #define FVTHROT_PWM_DS_REG1 0x3070 130 #define FVTHROT_STATUS_REG0 0x3074 131 #define CURRENT_FEEDBACK_DIV_MASK 0xfff 132 #define CURRENT_FEEDBACK_DIV_SHIFT 0 133 #define FVTHROT_STATUS_REG1 0x3078 134 #define FVTHROT_STATUS_REG2 0x307c 135 #define CG_INTGFX_MISC 0x3080 136 #define FVTHROT_VBLANK_SEL (1 << 9) 137 #define FVTHROT_PWM_FEEDBACK_DIV_REG1 0x308c 138 #define RANGE0_PWM_FEEDBACK_DIV(x) ((x) << 0) 139 #define RANGE0_PWM_FEEDBACK_DIV_MASK 0xfff 140 #define RANGE0_PWM_FEEDBACK_DIV_SHIFT 0 141 #define RANGE_PWM_FEEDBACK_DIV_EN (1 << 12) 142 #define FVTHROT_PWM_FEEDBACK_DIV_REG2 0x3090 143 #define RANGE1_PWM_FEEDBACK_DIV(x) ((x) << 0) 144 #define RANGE1_PWM_FEEDBACK_DIV_MASK 0xfff 145 #define RANGE1_PWM_FEEDBACK_DIV_SHIFT 0 146 #define RANGE2_PWM_FEEDBACK_DIV(x) ((x) << 12) 147 #define RANGE2_PWM_FEEDBACK_DIV_MASK (0xfff << 12) 148 #define RANGE2_PWM_FEEDBACK_DIV_SHIFT 12 149 #define FVTHROT_PWM_FEEDBACK_DIV_REG3 0x3094 150 #define RANGE0_PWM(x) ((x) << 0) 151 #define RANGE0_PWM_MASK 0xfff 152 #define RANGE0_PWM_SHIFT 0 153 #define RANGE1_PWM(x) ((x) << 12) 154 #define RANGE1_PWM_MASK (0xfff << 12) 155 #define RANGE1_PWM_SHIFT 12 156 #define FVTHROT_PWM_FEEDBACK_DIV_REG4 0x3098 157 #define RANGE2_PWM(x) ((x) << 0) 158 #define RANGE2_PWM_MASK 0xfff 159 #define RANGE2_PWM_SHIFT 0 160 #define RANGE3_PWM(x) ((x) << 12) 161 #define RANGE3_PWM_MASK (0xfff << 12) 162 #define RANGE3_PWM_SHIFT 12 163 #define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 0x30ac 164 #define RANGE0_SLOW_CLK_FEEDBACK_DIV(x) ((x) << 0) 165 #define RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK 0xfff 166 #define RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT 0 167 #define RANGE_SLOW_CLK_FEEDBACK_DIV_EN (1 << 12) 168 169 #define GFX_MACRO_BYPASS_CNTL 0x30c0 170 #define SPLL_BYPASS_CNTL (1 << 0) 171 #define UPLL_BYPASS_CNTL (1 << 1) 172 173 #endif 174
Indexes created Tue Sep 23 21:09:50 GMT 2025