1 /* $NetBSD: clockreg.h,v 1.11 2011/02/08 20:20:13 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: Utah $Hdr: clockreg.h 1.14 91/01/18$ 37 * 38 * @(#)clockreg.h 8.2 (Berkeley) 1/12/94 39 */ 40 41 /* 42 * MC6840 PTM registers 43 */ 44 45 struct clkreg { 46 u_char clk_dummy1; 47 u_char clk_cr3; 48 #define clk_cr1 clk_cr3 49 u_char clk_dummy2; 50 u_char clk_cr2; 51 #define clk_sr clk_cr2 52 u_char clk_dummy3; 53 u_char clk_msb1; 54 u_char clk_dummy4; 55 u_char clk_lsb1; 56 u_char clk_dummy5; 57 u_char clk_msb2; 58 u_char clk_dummy6; 59 u_char clk_lsb2; 60 u_char clk_dummy7; 61 u_char clk_msb3; 62 u_char clk_dummy8; 63 u_char clk_lsb3; 64 }; 65 66 /* base/offsets for register access (for locore.s) */ 67 #define CLKBASE IIOPOFF(0x5F8000) 68 #define CLKCR1 0x1 69 #define CLKCR2 0x3 70 #define CLKCR3 CLKCR1 71 #define CLKSR CLKCR2 72 #define CLKMSB1 0x5 73 #define CLKMSB2 0x9 74 #define CLKMSB3 0xD 75 76 /* output of counter 3 clocks counter 2 */ 77 78 #define CLK_OENAB 0x80 /* output enable */ 79 #define CLK_IENAB 0x40 /* interrupt enable */ 80 #define CLK_8BIT 0x04 /* 8 bit mode */ 81 #define CLK_RESET 0x01 /* chip reset (CR1 only) */ 82 #define CLK_CR1 0x01 /* select CR1 (CR2 only) */ 83 #define CLK_CR3 0x00 /* select CR3 (CR2 only) */ 84 #define CLK_INT1 0x01 /* interrupt flag for timer 1 (SR only) */ 85 #define CLK_INT2 0x02 /* interrupt flag for timer 2 (SR only) */ 86 #define CLK_INT3 0x04 /* interrupt flag for timer 3 (SR only) */ 87 #define CLK_INTR 0x80 /* composite interrupt flag (SR only) */ 88 89 #define CLK_RESOLUTION 4 /* 4 usec resolution (250 kHz) */ 90 #define CLK_INTERVAL 2500 /* 10msec interval at 250 kHz */ 91 #ifdef NOTDEF 92 #define CLK_INTERVAL 5000 /* 20msec interval at 250 kHz */ 93 #endif 94
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