1 /* $NetBSD: mt8173-clk.h,v 1.1.1.5 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2014 MediaTek Inc. 6 * Author: James Liao <jamesjj.liao (at) mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_MT8173_H 10 #define _DT_BINDINGS_CLK_MT8173_H 11 12 /* TOPCKGEN */ 13 14 #define CLK_TOP_CLKPH_MCK_O 1 15 #define CLK_TOP_USB_SYSPLL_125M 3 16 #define CLK_TOP_HDMITX_DIG_CTS 4 17 #define CLK_TOP_ARMCA7PLL_754M 5 18 #define CLK_TOP_ARMCA7PLL_502M 6 19 #define CLK_TOP_MAIN_H546M 7 20 #define CLK_TOP_MAIN_H364M 8 21 #define CLK_TOP_MAIN_H218P4M 9 22 #define CLK_TOP_MAIN_H156M 10 23 #define CLK_TOP_TVDPLL_445P5M 11 24 #define CLK_TOP_TVDPLL_594M 12 25 #define CLK_TOP_UNIV_624M 13 26 #define CLK_TOP_UNIV_416M 14 27 #define CLK_TOP_UNIV_249P6M 15 28 #define CLK_TOP_UNIV_178P3M 16 29 #define CLK_TOP_UNIV_48M 17 30 #define CLK_TOP_CLKRTC_EXT 18 31 #define CLK_TOP_CLKRTC_INT 19 32 #define CLK_TOP_FPC 20 33 #define CLK_TOP_HDMITXPLL_D2 21 34 #define CLK_TOP_HDMITXPLL_D3 22 35 #define CLK_TOP_ARMCA7PLL_D2 23 36 #define CLK_TOP_ARMCA7PLL_D3 24 37 #define CLK_TOP_APLL1 25 38 #define CLK_TOP_APLL2 26 39 #define CLK_TOP_DMPLL 27 40 #define CLK_TOP_DMPLL_D2 28 41 #define CLK_TOP_DMPLL_D4 29 42 #define CLK_TOP_DMPLL_D8 30 43 #define CLK_TOP_DMPLL_D16 31 44 #define CLK_TOP_LVDSPLL_D2 32 45 #define CLK_TOP_LVDSPLL_D4 33 46 #define CLK_TOP_LVDSPLL_D8 34 47 #define CLK_TOP_MMPLL 35 48 #define CLK_TOP_MMPLL_D2 36 49 #define CLK_TOP_MSDCPLL 37 50 #define CLK_TOP_MSDCPLL_D2 38 51 #define CLK_TOP_MSDCPLL_D4 39 52 #define CLK_TOP_MSDCPLL2 40 53 #define CLK_TOP_MSDCPLL2_D2 41 54 #define CLK_TOP_MSDCPLL2_D4 42 55 #define CLK_TOP_SYSPLL_D2 43 56 #define CLK_TOP_SYSPLL1_D2 44 57 #define CLK_TOP_SYSPLL1_D4 45 58 #define CLK_TOP_SYSPLL1_D8 46 59 #define CLK_TOP_SYSPLL1_D16 47 60 #define CLK_TOP_SYSPLL_D3 48 61 #define CLK_TOP_SYSPLL2_D2 49 62 #define CLK_TOP_SYSPLL2_D4 50 63 #define CLK_TOP_SYSPLL_D5 51 64 #define CLK_TOP_SYSPLL3_D2 52 65 #define CLK_TOP_SYSPLL3_D4 53 66 #define CLK_TOP_SYSPLL_D7 54 67 #define CLK_TOP_SYSPLL4_D2 55 68 #define CLK_TOP_SYSPLL4_D4 56 69 #define CLK_TOP_TVDPLL 57 70 #define CLK_TOP_TVDPLL_D2 58 71 #define CLK_TOP_TVDPLL_D4 59 72 #define CLK_TOP_TVDPLL_D8 60 73 #define CLK_TOP_TVDPLL_D16 61 74 #define CLK_TOP_UNIVPLL_D2 62 75 #define CLK_TOP_UNIVPLL1_D2 63 76 #define CLK_TOP_UNIVPLL1_D4 64 77 #define CLK_TOP_UNIVPLL1_D8 65 78 #define CLK_TOP_UNIVPLL_D3 66 79 #define CLK_TOP_UNIVPLL2_D2 67 80 #define CLK_TOP_UNIVPLL2_D4 68 81 #define CLK_TOP_UNIVPLL2_D8 69 82 #define CLK_TOP_UNIVPLL_D5 70 83 #define CLK_TOP_UNIVPLL3_D2 71 84 #define CLK_TOP_UNIVPLL3_D4 72 85 #define CLK_TOP_UNIVPLL3_D8 73 86 #define CLK_TOP_UNIVPLL_D7 74 87 #define CLK_TOP_UNIVPLL_D26 75 88 #define CLK_TOP_UNIVPLL_D52 76 89 #define CLK_TOP_VCODECPLL 77 90 #define CLK_TOP_VCODECPLL_370P5 78 91 #define CLK_TOP_VENCPLL 79 92 #define CLK_TOP_VENCPLL_D2 80 93 #define CLK_TOP_VENCPLL_D4 81 94 #define CLK_TOP_AXI_SEL 82 95 #define CLK_TOP_MEM_SEL 83 96 #define CLK_TOP_DDRPHYCFG_SEL 84 97 #define CLK_TOP_MM_SEL 85 98 #define CLK_TOP_PWM_SEL 86 99 #define CLK_TOP_VDEC_SEL 87 100 #define CLK_TOP_VENC_SEL 88 101 #define CLK_TOP_MFG_SEL 89 102 #define CLK_TOP_CAMTG_SEL 90 103 #define CLK_TOP_UART_SEL 91 104 #define CLK_TOP_SPI_SEL 92 105 #define CLK_TOP_USB20_SEL 93 106 #define CLK_TOP_USB30_SEL 94 107 #define CLK_TOP_MSDC50_0_H_SEL 95 108 #define CLK_TOP_MSDC50_0_SEL 96 109 #define CLK_TOP_MSDC30_1_SEL 97 110 #define CLK_TOP_MSDC30_2_SEL 98 111 #define CLK_TOP_MSDC30_3_SEL 99 112 #define CLK_TOP_AUDIO_SEL 100 113 #define CLK_TOP_AUD_INTBUS_SEL 101 114 #define CLK_TOP_PMICSPI_SEL 102 115 #define CLK_TOP_SCP_SEL 103 116 #define CLK_TOP_ATB_SEL 104 117 #define CLK_TOP_VENC_LT_SEL 105 118 #define CLK_TOP_DPI0_SEL 106 119 #define CLK_TOP_IRDA_SEL 107 120 #define CLK_TOP_CCI400_SEL 108 121 #define CLK_TOP_AUD_1_SEL 109 122 #define CLK_TOP_AUD_2_SEL 110 123 #define CLK_TOP_MEM_MFG_IN_SEL 111 124 #define CLK_TOP_AXI_MFG_IN_SEL 112 125 #define CLK_TOP_SCAM_SEL 113 126 #define CLK_TOP_SPINFI_IFR_SEL 114 127 #define CLK_TOP_HDMI_SEL 115 128 #define CLK_TOP_DPILVDS_SEL 116 129 #define CLK_TOP_MSDC50_2_H_SEL 117 130 #define CLK_TOP_HDCP_SEL 118 131 #define CLK_TOP_HDCP_24M_SEL 119 132 #define CLK_TOP_RTC_SEL 120 133 #define CLK_TOP_APLL1_DIV0 121 134 #define CLK_TOP_APLL1_DIV1 122 135 #define CLK_TOP_APLL1_DIV2 123 136 #define CLK_TOP_APLL1_DIV3 124 137 #define CLK_TOP_APLL1_DIV4 125 138 #define CLK_TOP_APLL1_DIV5 126 139 #define CLK_TOP_APLL2_DIV0 127 140 #define CLK_TOP_APLL2_DIV1 128 141 #define CLK_TOP_APLL2_DIV2 129 142 #define CLK_TOP_APLL2_DIV3 130 143 #define CLK_TOP_APLL2_DIV4 131 144 #define CLK_TOP_APLL2_DIV5 132 145 #define CLK_TOP_I2S0_M_SEL 133 146 #define CLK_TOP_I2S1_M_SEL 134 147 #define CLK_TOP_I2S2_M_SEL 135 148 #define CLK_TOP_I2S3_M_SEL 136 149 #define CLK_TOP_I2S3_B_SEL 137 150 #define CLK_TOP_DSI0_DIG 138 151 #define CLK_TOP_DSI1_DIG 139 152 #define CLK_TOP_LVDS_PXL 140 153 #define CLK_TOP_LVDS_CTS 141 154 #define CLK_TOP_NR_CLK 142 155 156 /* APMIXED_SYS */ 157 158 #define CLK_APMIXED_ARMCA15PLL 1 159 #define CLK_APMIXED_ARMCA7PLL 2 160 #define CLK_APMIXED_MAINPLL 3 161 #define CLK_APMIXED_UNIVPLL 4 162 #define CLK_APMIXED_MMPLL 5 163 #define CLK_APMIXED_MSDCPLL 6 164 #define CLK_APMIXED_VENCPLL 7 165 #define CLK_APMIXED_TVDPLL 8 166 #define CLK_APMIXED_MPLL 9 167 #define CLK_APMIXED_VCODECPLL 10 168 #define CLK_APMIXED_APLL1 11 169 #define CLK_APMIXED_APLL2 12 170 #define CLK_APMIXED_LVDSPLL 13 171 #define CLK_APMIXED_MSDCPLL2 14 172 #define CLK_APMIXED_REF2USB_TX 15 173 #define CLK_APMIXED_HDMI_REF 16 174 #define CLK_APMIXED_NR_CLK 17 175 176 /* INFRA_SYS */ 177 178 #define CLK_INFRA_DBGCLK 1 179 #define CLK_INFRA_SMI 2 180 #define CLK_INFRA_AUDIO 3 181 #define CLK_INFRA_GCE 4 182 #define CLK_INFRA_L2C_SRAM 5 183 #define CLK_INFRA_M4U 6 184 #define CLK_INFRA_CPUM 7 185 #define CLK_INFRA_KP 8 186 #define CLK_INFRA_CEC 9 187 #define CLK_INFRA_PMICSPI 10 188 #define CLK_INFRA_PMICWRAP 11 189 #define CLK_INFRA_CLK_13M 12 190 #define CLK_INFRA_CA53SEL 13 191 #define CLK_INFRA_CA72SEL 14 192 #define CLK_INFRA_NR_CLK 15 193 194 /* PERI_SYS */ 195 196 #define CLK_PERI_NFI 1 197 #define CLK_PERI_THERM 2 198 #define CLK_PERI_PWM1 3 199 #define CLK_PERI_PWM2 4 200 #define CLK_PERI_PWM3 5 201 #define CLK_PERI_PWM4 6 202 #define CLK_PERI_PWM5 7 203 #define CLK_PERI_PWM6 8 204 #define CLK_PERI_PWM7 9 205 #define CLK_PERI_PWM 10 206 #define CLK_PERI_USB0 11 207 #define CLK_PERI_USB1 12 208 #define CLK_PERI_AP_DMA 13 209 #define CLK_PERI_MSDC30_0 14 210 #define CLK_PERI_MSDC30_1 15 211 #define CLK_PERI_MSDC30_2 16 212 #define CLK_PERI_MSDC30_3 17 213 #define CLK_PERI_NLI_ARB 18 214 #define CLK_PERI_IRDA 19 215 #define CLK_PERI_UART0 20 216 #define CLK_PERI_UART1 21 217 #define CLK_PERI_UART2 22 218 #define CLK_PERI_UART3 23 219 #define CLK_PERI_I2C0 24 220 #define CLK_PERI_I2C1 25 221 #define CLK_PERI_I2C2 26 222 #define CLK_PERI_I2C3 27 223 #define CLK_PERI_I2C4 28 224 #define CLK_PERI_AUXADC 29 225 #define CLK_PERI_SPI0 30 226 #define CLK_PERI_I2C5 31 227 #define CLK_PERI_NFIECC 32 228 #define CLK_PERI_SPI 33 229 #define CLK_PERI_IRRX 34 230 #define CLK_PERI_I2C6 35 231 #define CLK_PERI_UART0_SEL 36 232 #define CLK_PERI_UART1_SEL 37 233 #define CLK_PERI_UART2_SEL 38 234 #define CLK_PERI_UART3_SEL 39 235 #define CLK_PERI_NR_CLK 40 236 237 /* IMG_SYS */ 238 239 #define CLK_IMG_LARB2_SMI 1 240 #define CLK_IMG_CAM_SMI 2 241 #define CLK_IMG_CAM_CAM 3 242 #define CLK_IMG_SEN_TG 4 243 #define CLK_IMG_SEN_CAM 5 244 #define CLK_IMG_CAM_SV 6 245 #define CLK_IMG_FD 7 246 #define CLK_IMG_NR_CLK 8 247 248 /* MM_SYS */ 249 250 #define CLK_MM_SMI_COMMON 1 251 #define CLK_MM_SMI_LARB0 2 252 #define CLK_MM_CAM_MDP 3 253 #define CLK_MM_MDP_RDMA0 4 254 #define CLK_MM_MDP_RDMA1 5 255 #define CLK_MM_MDP_RSZ0 6 256 #define CLK_MM_MDP_RSZ1 7 257 #define CLK_MM_MDP_RSZ2 8 258 #define CLK_MM_MDP_TDSHP0 9 259 #define CLK_MM_MDP_TDSHP1 10 260 #define CLK_MM_MDP_WDMA 11 261 #define CLK_MM_MDP_WROT0 12 262 #define CLK_MM_MDP_WROT1 13 263 #define CLK_MM_FAKE_ENG 14 264 #define CLK_MM_MUTEX_32K 15 265 #define CLK_MM_DISP_OVL0 16 266 #define CLK_MM_DISP_OVL1 17 267 #define CLK_MM_DISP_RDMA0 18 268 #define CLK_MM_DISP_RDMA1 19 269 #define CLK_MM_DISP_RDMA2 20 270 #define CLK_MM_DISP_WDMA0 21 271 #define CLK_MM_DISP_WDMA1 22 272 #define CLK_MM_DISP_COLOR0 23 273 #define CLK_MM_DISP_COLOR1 24 274 #define CLK_MM_DISP_AAL 25 275 #define CLK_MM_DISP_GAMMA 26 276 #define CLK_MM_DISP_UFOE 27 277 #define CLK_MM_DISP_SPLIT0 28 278 #define CLK_MM_DISP_SPLIT1 29 279 #define CLK_MM_DISP_MERGE 30 280 #define CLK_MM_DISP_OD 31 281 #define CLK_MM_DISP_PWM0MM 32 282 #define CLK_MM_DISP_PWM026M 33 283 #define CLK_MM_DISP_PWM1MM 34 284 #define CLK_MM_DISP_PWM126M 35 285 #define CLK_MM_DSI0_ENGINE 36 286 #define CLK_MM_DSI0_DIGITAL 37 287 #define CLK_MM_DSI1_ENGINE 38 288 #define CLK_MM_DSI1_DIGITAL 39 289 #define CLK_MM_DPI_PIXEL 40 290 #define CLK_MM_DPI_ENGINE 41 291 #define CLK_MM_DPI1_PIXEL 42 292 #define CLK_MM_DPI1_ENGINE 43 293 #define CLK_MM_HDMI_PIXEL 44 294 #define CLK_MM_HDMI_PLLCK 45 295 #define CLK_MM_HDMI_AUDIO 46 296 #define CLK_MM_HDMI_SPDIF 47 297 #define CLK_MM_LVDS_PIXEL 48 298 #define CLK_MM_LVDS_CTS 49 299 #define CLK_MM_SMI_LARB4 50 300 #define CLK_MM_HDMI_HDCP 51 301 #define CLK_MM_HDMI_HDCP24M 52 302 #define CLK_MM_NR_CLK 53 303 304 /* VDEC_SYS */ 305 306 #define CLK_VDEC_CKEN 1 307 #define CLK_VDEC_LARB_CKEN 2 308 #define CLK_VDEC_NR_CLK 3 309 310 /* VENC_SYS */ 311 312 #define CLK_VENC_CKE0 1 313 #define CLK_VENC_CKE1 2 314 #define CLK_VENC_CKE2 3 315 #define CLK_VENC_CKE3 4 316 #define CLK_VENC_NR_CLK 5 317 318 /* VENCLT_SYS */ 319 320 #define CLK_VENCLT_CKE0 1 321 #define CLK_VENCLT_CKE1 2 322 #define CLK_VENCLT_NR_CLK 3 323 324 #endif /* _DT_BINDINGS_CLK_MT8173_H */ 325
Indexes created Thu Sep 25 16:09:42 GMT 2025