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    Searched defs:CLK_PLL (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/arch/arm/nxp/
imx6_ccmvar.h 195 #define CLK_PLL(_name, _parent, _type, _reg, _mask, _powerdown, _ref) { \
  /src/sys/arch/arm/nvidia/
tegra124_car.c 297 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \
436 CLK_PLL("pll_p", "clk_m", CAR_PLLP_BASE_REG,
438 CLK_PLL("pll_c", "clk_m", CAR_PLLC_BASE_REG,
440 CLK_PLL("pll_u", "clk_m", CAR_PLLU_BASE_REG,
442 CLK_PLL("pll_x", "clk_m", CAR_PLLX_BASE_REG,
444 CLK_PLL("pll_e", "clk_m", CAR_PLLE_BASE_REG,
446 CLK_PLL("pll_d", "clk_m", CAR_PLLD_BASE_REG,
448 CLK_PLL("pll_d2", "clk_m", CAR_PLLD2_BASE_REG,
450 CLK_PLL("pll_re", "clk_m", CAR_PLLREFE_BASE_REG,
tegra210_car.c 309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \
465 CLK_PLL("PLL_P", "CLK_M", CAR_PLLP_BASE_REG,
467 CLK_PLL("PLL_C", "CLK_M", CAR_PLLC_BASE_REG,
469 CLK_PLL("PLL_U", "CLK_M", CAR_PLLU_BASE_REG,
471 CLK_PLL("PLL_X", "CLK_M", CAR_PLLX_BASE_REG,
473 CLK_PLL("PLL_E", "CLK_M", CAR_PLLE_BASE_REG,
475 CLK_PLL("PLL_D", "CLK_M", CAR_PLLD_BASE_REG,
477 CLK_PLL("PLL_D2", "CLK_M", CAR_PLLD2_BASE_REG,
479 CLK_PLL("PLL_REF", "CLK_M", CAR_PLLREFE_BASE_REG,
  /src/sys/arch/arm/samsung/
exynos5410_clock.c 136 #define CLK_PLL(_name, _parent, _lock, _con0) { \
262 CLK_PLL("fout_apll", "fin_pll", EXYNOS5410_APLL_LOCK,
264 CLK_PLL("fout_bpll", "fin_pll", EXYNOS5410_BPLL_LOCK,
266 CLK_PLL("fout_cpll", "fin_pll", EXYNOS5410_CPLL_LOCK,
268 CLK_PLL("fout_epll", "fin_pll", EXYNOS5410_EPLL_LOCK,
270 CLK_PLL("fout_mpll", "fin_pll", EXYNOS5410_MPLL_LOCK,
272 CLK_PLL("fout_kpll", "fin_pll", EXYNOS5410_KPLL_LOCK,
exynos5422_clock.c 280 #define CLK_PLL(_name, _parent, _lock, _con0) { \
420 CLK_PLL("fout_apll", "fin_pll", EXYNOS5422_APLL_LOCK,
422 CLK_PLL("fout_cpll", "fin_pll", EXYNOS5422_CPLL_LOCK,
424 CLK_PLL("fout_dpll", "fin_pll", EXYNOS5422_DPLL_LOCK,
426 CLK_PLL("fout_epll", "fin_pll", EXYNOS5422_EPLL_LOCK,
428 CLK_PLL("fout_rpll", "fin_pll", EXYNOS5422_RPLL_LOCK,
430 CLK_PLL("fout_ipll", "fin_pll", EXYNOS5422_IPLL_LOCK,
432 CLK_PLL("fout_spll", "fin_pll", EXYNOS5422_SPLL_LOCK,
434 CLK_PLL("fout_vpll", "fin_pll", EXYNOS5422_VPLL_LOCK,
436 CLK_PLL("fout_mpll", "fin_pll", EXYNOS5422_MPLL_LOCK
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