1 /* $NetBSD: imx8mq_ccm.h,v 1.1 2020/12/23 14:42:38 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _IMX8MQ_CCM_H 30 #define _IMX8MQ_CCM_H 31 32 /* 33 * Clocks 34 */ 35 36 #define CLK_DUMMY 0 37 #define CLK_32K 1 38 #define CLK_25M 2 39 #define CLK_27M 3 40 #define CLK_EXT1 4 41 #define CLK_EXT2 5 42 #define CLK_EXT3 6 43 #define CLK_EXT4 7 44 #define ARM_PLL_REF_SEL 8 45 #define ARM_PLL_REF_DIV 9 46 #define ARM_PLL 10 47 #define ARM_PLL_BYPASS 11 48 #define ARM_PLL_OUT 12 49 #define GPU_PLL_REF_SEL 13 50 #define GPU_PLL_REF_DIV 14 51 #define GPU_PLL 15 52 #define GPU_PLL_BYPASS 16 53 #define GPU_PLL_OUT 17 54 #define VPU_PLL_REF_SEL 18 55 #define VPU_PLL_REF_DIV 19 56 #define VPU_PLL 20 57 #define VPU_PLL_BYPASS 21 58 #define VPU_PLL_OUT 22 59 #define AUDIO_PLL1_REF_SEL 23 60 #define AUDIO_PLL1_REF_DIV 24 61 #define AUDIO_PLL1 25 62 #define AUDIO_PLL1_BYPASS 26 63 #define AUDIO_PLL1_OUT 27 64 #define AUDIO_PLL2_REF_SEL 28 65 #define AUDIO_PLL2_REF_DIV 29 66 #define AUDIO_PLL2 30 67 #define AUDIO_PLL2_BYPASS 31 68 #define AUDIO_PLL2_OUT 32 69 #define VIDEO_PLL1_REF_SEL 33 70 #define VIDEO_PLL1_REF_DIV 34 71 #define VIDEO_PLL1 35 72 #define VIDEO_PLL1_BYPASS 36 73 #define VIDEO_PLL1_OUT 37 74 #define SYS1_PLL1_REF_SEL 38 75 #define SYS1_PLL1_REF_DIV 39 76 #define SYS1_PLL1 40 77 #define SYS1_PLL1_OUT 41 78 #define SYS1_PLL1_OUT_DIV 42 79 #define SYS1_PLL2 43 80 #define SYS1_PLL2_DIV 44 81 #define SYS1_PLL2_OUT 45 82 #define SYS2_PLL1_REF_SEL 46 83 #define SYS2_PLL1_REF_DIV 47 84 #define SYS2_PLL1 48 85 #define SYS2_PLL1_OUT 49 86 #define SYS2_PLL1_OUT_DIV 50 87 #define SYS2_PLL2 51 88 #define SYS2_PLL2_DIV 52 89 #define SYS2_PLL2_OUT 53 90 #define SYS3_PLL1_REF_SEL 54 91 #define SYS3_PLL1_REF_DIV 55 92 #define SYS3_PLL1 56 93 #define SYS3_PLL1_OUT 57 94 #define SYS3_PLL1_OUT_DIV 58 95 #define SYS3_PLL2 59 96 #define SYS3_PLL2_DIV 60 97 #define SYS3_PLL2_OUT 61 98 #define DRAM_PLL1_REF_SEL 62 99 #define DRAM_PLL1_REF_DIV 63 100 #define DRAM_PLL1 64 101 #define DRAM_PLL1_OUT 65 102 #define DRAM_PLL1_OUT_DIV 66 103 #define DRAM_PLL2 67 104 #define DRAM_PLL2_DIV 68 105 #define DRAM_PLL2_OUT 69 106 #define SYS1_PLL_40M 70 107 #define SYS1_PLL_80M 71 108 #define SYS1_PLL_100M 72 109 #define SYS1_PLL_133M 73 110 #define SYS1_PLL_160M 74 111 #define SYS1_PLL_200M 75 112 #define SYS1_PLL_266M 76 113 #define SYS1_PLL_400M 77 114 #define SYS1_PLL_800M 78 115 #define SYS2_PLL_50M 79 116 #define SYS2_PLL_100M 80 117 #define SYS2_PLL_125M 81 118 #define SYS2_PLL_166M 82 119 #define SYS2_PLL_200M 83 120 #define SYS2_PLL_250M 84 121 #define SYS2_PLL_333M 85 122 #define SYS2_PLL_500M 86 123 #define SYS2_PLL_1000M 87 124 #define CLK_A53_SRC 88 125 #define CLK_A53_CG 89 126 #define CLK_A53_DIV 90 127 #define CLK_M4_SRC 91 128 #define CLK_M4_CG 92 129 #define CLK_M4_DIV 93 130 #define CLK_VPU_SRC 94 131 #define CLK_VPU_CG 95 132 #define CLK_VPU_DIV 96 133 #define CLK_GPU_CORE_SRC 97 134 #define CLK_GPU_CORE_CG 98 135 #define CLK_GPU_CORE_DIV 99 136 #define CLK_GPU_SHADER_SRC 100 137 #define CLK_GPU_SHADER_CG 101 138 #define CLK_GPU_SHADER_DIV 102 139 #define CLK_MAIN_AXI 103 140 #define CLK_ENET_AXI 104 141 #define CLK_NAND_USDHC_BUS 105 142 #define CLK_VPU_BUS 106 143 #define CLK_DISP_AXI 107 144 #define CLK_DISP_APB 108 145 #define CLK_DISP_RTRM 109 146 #define CLK_USB_BUS 110 147 #define CLK_GPU_AXI 111 148 #define CLK_GPU_AHB 112 149 #define CLK_NOC 113 150 #define CLK_NOC_APB 115 151 #define CLK_AHB 116 152 #define CLK_AUDIO_AHB 117 153 #define CLK_DRAM_ALT 118 154 #define CLK_DRAM_APB 119 155 #define CLK_VPU_G1 120 156 #define CLK_VPU_G2 121 157 #define CLK_DISP_DTRC 122 158 #define CLK_DISP_DC8000 123 159 #define CLK_PCIE1_CTRL 124 160 #define CLK_PCIE1_PHY 125 161 #define CLK_PCIE1_AUX 126 162 #define CLK_DC_PIXEL 127 163 #define CLK_LCDIF_PIXEL 128 164 #define CLK_SAI1 129 165 #define CLK_SAI2 130 166 #define CLK_SAI3 131 167 #define CLK_SAI4 132 168 #define CLK_SAI5 133 169 #define CLK_SAI6 134 170 #define CLK_SPDIF1 135 171 #define CLK_SPDIF2 136 172 #define CLK_ENET_REF 137 173 #define CLK_ENET_TIMER 138 174 #define CLK_ENET_PHY_REF 139 175 #define CLK_NAND 140 176 #define CLK_QSPI 141 177 #define CLK_USDHC1 142 178 #define CLK_USDHC2 143 179 #define CLK_I2C1 144 180 #define CLK_I2C2 145 181 #define CLK_I2C3 146 182 #define CLK_I2C4 147 183 #define CLK_UART1 148 184 #define CLK_UART2 149 185 #define CLK_UART3 150 186 #define CLK_UART4 151 187 #define CLK_USB_CORE_REF 152 188 #define CLK_USB_PHY_REF 153 189 #define CLK_ECSPI1 154 190 #define CLK_ECSPI2 155 191 #define CLK_PWM1 156 192 #define CLK_PWM2 157 193 #define CLK_PWM3 158 194 #define CLK_PWM4 159 195 #define CLK_GPT1 160 196 #define CLK_WDOG 161 197 #define CLK_WRCLK 162 198 #define CLK_DSI_CORE 163 199 #define CLK_DSI_PHY_REF 164 200 #define CLK_DSI_DBI 165 201 #define CLK_DSI_ESC 166 202 #define CLK_CSI1_CORE 167 203 #define CLK_CSI1_PHY_REF 168 204 #define CLK_CSI1_ESC 169 205 #define CLK_CSI2_CORE 170 206 #define CLK_CSI2_PHY_REF 171 207 #define CLK_CSI2_ESC 172 208 #define CLK_PCIE2_CTRL 173 209 #define CLK_PCIE2_PHY 174 210 #define CLK_PCIE2_AUX 175 211 #define CLK_ECSPI3 176 212 #define CLK_A53_ROOT 177 213 #define CLK_DRAM_ROOT 178 214 #define CLK_ECSPI1_ROOT 179 215 #define CLK_ECSPI2_ROOT 180 216 #define CLK_ECSPI3_ROOT 181 217 #define CLK_ENET1_ROOT 182 218 #define CLK_GPT1_ROOT 183 219 #define CLK_I2C1_ROOT 184 220 #define CLK_I2C2_ROOT 185 221 #define CLK_I2C3_ROOT 186 222 #define CLK_I2C4_ROOT 187 223 #define CLK_M4_ROOT 188 224 #define CLK_PCIE1_ROOT 189 225 #define CLK_PCIE2_ROOT 190 226 #define CLK_PWM1_ROOT 191 227 #define CLK_PWM2_ROOT 192 228 #define CLK_PWM3_ROOT 193 229 #define CLK_PWM4_ROOT 194 230 #define CLK_QSPI_ROOT 195 231 #define CLK_SAI1_ROOT 196 232 #define CLK_SAI2_ROOT 197 233 #define CLK_SAI3_ROOT 198 234 #define CLK_SAI4_ROOT 199 235 #define CLK_SAI5_ROOT 200 236 #define CLK_SAI6_ROOT 201 237 #define CLK_UART1_ROOT 202 238 #define CLK_UART2_ROOT 203 239 #define CLK_UART3_ROOT 204 240 #define CLK_UART4_ROOT 205 241 #define CLK_USB1_CTRL_ROOT 206 242 #define CLK_USB2_CTRL_ROOT 207 243 #define CLK_USB1_PHY_ROOT 208 244 #define CLK_USB2_PHY_ROOT 209 245 #define CLK_USDHC1_ROOT 210 246 #define CLK_USDHC2_ROOT 211 247 #define CLK_WDOG1_ROOT 212 248 #define CLK_WDOG2_ROOT 213 249 #define CLK_WDOG3_ROOT 214 250 #define CLK_GPU_ROOT 215 251 #define CLK_HEVC_ROOT 216 252 #define CLK_AVC_ROOT 217 253 #define CLK_VP9_ROOT 218 254 #define CLK_HEVC_INTER_ROOT 219 255 #define CLK_DISP_ROOT 220 256 #define CLK_HDMI_ROOT 221 257 #define CLK_HDMI_PHY_ROOT 222 258 #define CLK_VPU_DEC_ROOT 223 259 #define CLK_CSI1_ROOT 224 260 #define CLK_CSI2_ROOT 225 261 #define CLK_RAWNAND_ROOT 226 262 #define CLK_SDMA1_ROOT 227 263 #define CLK_SDMA2_ROOT 228 264 #define CLK_VPU_G1_ROOT 229 265 #define CLK_VPU_G2_ROOT 230 266 #define SYS1_PLL_OUT 231 267 #define SYS2_PLL_OUT 232 268 #define SYS3_PLL_OUT 233 269 #define DRAM_PLL_OUT 234 270 #define GPT_3M_CLK 235 271 #define CLK_IPG_ROOT 236 272 #define CLK_IPG_AUDIO_ROOT 237 273 #define CLK_SAI1_IPG 238 274 #define CLK_SAI2_IPG 239 275 #define CLK_SAI3_IPG 240 276 #define CLK_SAI4_IPG 241 277 #define CLK_SAI5_IPG 242 278 #define CLK_SAI6_IPG 243 279 #define CLK_DSI_AHB 244 280 #define CLK_DSI_IPG_DIV 245 281 #define CLK_TMU_ROOT 246 282 #define CLK_DISP_AXI_ROOT 247 283 #define CLK_DISP_APB_ROOT 248 284 #define CLK_DISP_RTRM_ROOT 249 285 #define CLK_OCOTP_ROOT 250 286 #define CLK_DRAM_ALT_ROOT 251 287 #define CLK_DRAM_CORE 252 288 #define CLK_MU_ROOT 253 289 #define VIDEO2_PLL_OUT 254 290 #define CLK_CLKO2 255 291 #define CLK_NAND_USDHC_BUS_RAWNAND_CLK 256 292 #define CLK_CLKO1 257 293 #define CLK_ARM 258 294 #define CLK_GPIO1_ROOT 259 295 #define CLK_GPIO2_ROOT 260 296 #define CLK_GPIO3_ROOT 261 297 #define CLK_GPIO4_ROOT 262 298 #define CLK_GPIO5_ROOT 263 299 #define CLK_SNVS_ROOT 264 300 #define CLK_GIC 265 301 #define VIDEO2_PLL1_REF_SEL 266 302 #define SYS1_PLL_40M_CG 267 303 #define SYS1_PLL_80M_CG 268 304 #define SYS1_PLL_100M_CG 269 305 #define SYS1_PLL_133M_CG 270 306 #define SYS1_PLL_160M_CG 271 307 #define SYS1_PLL_200M_CG 272 308 #define SYS1_PLL_266M_CG 273 309 #define SYS1_PLL_400M_CG 274 310 #define SYS1_PLL_800M_CG 275 311 #define SYS2_PLL_50M_CG 276 312 #define SYS2_PLL_100M_CG 277 313 #define SYS2_PLL_125M_CG 278 314 #define SYS2_PLL_166M_CG 279 315 #define SYS2_PLL_200M_CG 280 316 #define SYS2_PLL_250M_CG 281 317 #define SYS2_PLL_333M_CG 282 318 #define SYS2_PLL_500M_CG 283 319 #define SYS2_PLL_1000M_CG 284 320 321 #endif /* !_IMX8MQ_CCM_H */ 322
Indexes created Sat Sep 20 22:09:52 GMT 2025