1 /* $NetBSD: smu12_driver_if.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef SMU12_DRIVER_IF_H 27 #define SMU12_DRIVER_IF_H 28 29 // *** IMPORTANT *** 30 // SMU TEAM: Always increment the interface version if 31 // any structure is changed in this file 32 #define SMU12_DRIVER_IF_VERSION 11 33 34 typedef struct { 35 int32_t value; 36 uint32_t numFractionalBits; 37 } FloatInIntFormat_t; 38 39 typedef enum { 40 DSPCLK_DCFCLK = 0, 41 DSPCLK_DISPCLK, 42 DSPCLK_PIXCLK, 43 DSPCLK_PHYCLK, 44 DSPCLK_COUNT, 45 } DSPCLK_e; 46 47 typedef struct { 48 uint16_t Freq; // in MHz 49 uint16_t Vid; // min voltage in SVI2 VID 50 } DisplayClockTable_t; 51 52 typedef struct { 53 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) 54 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) 55 uint16_t MinMclk; 56 uint16_t MaxMclk; 57 58 uint8_t WmSetting; 59 uint8_t WmType; // Used for normal pstate change or memory retraining 60 uint8_t Padding[2]; 61 } WatermarkRowGeneric_t; 62 63 #define NUM_WM_RANGES 4 64 #define WM_PSTATE_CHG 0 65 #define WM_RETRAINING 1 66 67 typedef enum { 68 WM_SOCCLK = 0, 69 WM_DCFCLK, 70 WM_COUNT, 71 } WM_CLOCK_e; 72 73 typedef struct { 74 // Watermarks 75 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 76 77 uint32_t MmHubPadding[7]; // SMU internal use 78 } Watermarks_t; 79 80 typedef enum { 81 CUSTOM_DPM_SETTING_GFXCLK, 82 CUSTOM_DPM_SETTING_CCLK, 83 CUSTOM_DPM_SETTING_FCLK_CCX, 84 CUSTOM_DPM_SETTING_FCLK_GFX, 85 CUSTOM_DPM_SETTING_FCLK_STALLS, 86 CUSTOM_DPM_SETTING_LCLK, 87 CUSTOM_DPM_SETTING_COUNT, 88 } CUSTOM_DPM_SETTING_e; 89 90 typedef struct { 91 uint8_t ActiveHystLimit; 92 uint8_t IdleHystLimit; 93 uint8_t FPS; 94 uint8_t MinActiveFreqType; 95 FloatInIntFormat_t MinActiveFreq; 96 FloatInIntFormat_t PD_Data_limit; 97 FloatInIntFormat_t PD_Data_time_constant; 98 FloatInIntFormat_t PD_Data_error_coeff; 99 FloatInIntFormat_t PD_Data_error_rate_coeff; 100 } DpmActivityMonitorCoeffExt_t; 101 102 typedef struct { 103 DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT]; 104 } CustomDpmSettings_t; 105 106 107 #define NUM_DCFCLK_DPM_LEVELS 8 108 #define NUM_SOCCLK_DPM_LEVELS 8 109 #define NUM_FCLK_DPM_LEVELS 4 110 #define NUM_MEMCLK_DPM_LEVELS 4 111 #define NUM_VCN_DPM_LEVELS 8 112 113 typedef struct { 114 uint32_t Freq; // In MHz 115 uint32_t Vol; // Millivolts with 2 fractional bits 116 } DpmClock_t; 117 118 typedef struct { 119 DpmClock_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; 120 DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; 121 DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS]; 122 DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS]; 123 DpmClock_t VClocks[NUM_VCN_DPM_LEVELS]; 124 DpmClock_t DClocks[NUM_VCN_DPM_LEVELS]; 125 126 uint8_t NumDcfClkDpmEnabled; 127 uint8_t NumSocClkDpmEnabled; 128 uint8_t NumFClkDpmEnabled; 129 uint8_t NumMemClkDpmEnabled; 130 uint8_t NumVClkDpmEnabled; 131 uint8_t NumDClkDpmEnabled; 132 uint8_t spare[2]; 133 } DpmClocks_t; 134 135 136 typedef enum { 137 CLOCK_SMNCLK = 0, 138 CLOCK_SOCCLK, 139 CLOCK_MP0CLK, 140 CLOCK_MP1CLK, 141 CLOCK_MP2CLK, 142 CLOCK_VCLK, 143 CLOCK_LCLK, 144 CLOCK_DCLK, 145 CLOCK_ACLK, 146 CLOCK_ISPCLK, 147 CLOCK_SHUBCLK, 148 CLOCK_DISPCLK, 149 CLOCK_DPPCLK, 150 CLOCK_DPREFCLK, 151 CLOCK_DCFCLK, 152 CLOCK_FCLK, 153 CLOCK_UMCCLK, 154 CLOCK_GFXCLK, 155 CLOCK_COUNT, 156 } CLOCK_IDs_e; 157 158 // Throttler Status Bitmask 159 #define THROTTLER_STATUS_BIT_SPL 0 160 #define THROTTLER_STATUS_BIT_FPPT 1 161 #define THROTTLER_STATUS_BIT_SPPT 2 162 #define THROTTLER_STATUS_BIT_SPPT_APU 3 163 #define THROTTLER_STATUS_BIT_THM_CORE 4 164 #define THROTTLER_STATUS_BIT_THM_GFX 5 165 #define THROTTLER_STATUS_BIT_THM_SOC 6 166 #define THROTTLER_STATUS_BIT_TDC_VDD 7 167 #define THROTTLER_STATUS_BIT_TDC_SOC 8 168 169 typedef struct { 170 uint16_t ClockFrequency[CLOCK_COUNT]; //[MHz] 171 172 uint16_t AverageGfxclkFrequency; //[MHz] 173 uint16_t AverageSocclkFrequency; //[MHz] 174 uint16_t AverageVclkFrequency; //[MHz] 175 uint16_t AverageFclkFrequency; //[MHz] 176 177 uint16_t AverageGfxActivity; //[centi] 178 uint16_t AverageUvdActivity; //[centi] 179 180 uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC 181 uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC 182 uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC 183 184 uint16_t FanPwm; //[milli] 185 uint16_t CurrentSocketPower; //[mW] 186 187 uint16_t CoreFrequency[8]; //[MHz] 188 uint16_t CorePower[8]; //[mW] 189 uint16_t CoreTemperature[8]; //[centi-Celsius] 190 uint16_t L3Frequency[2]; //[MHz] 191 uint16_t L3Temperature[2]; //[centi-Celsius] 192 193 uint16_t GfxTemperature; //[centi-Celsius] 194 uint16_t SocTemperature; //[centi-Celsius] 195 uint16_t ThrottlerStatus; 196 uint16_t spare; 197 198 uint16_t StapmOriginalLimit; //[mW] 199 uint16_t StapmCurrentLimit; //[mW] 200 uint16_t ApuPower; //[mW] 201 uint16_t dGpuPower; //[mW] 202 } SmuMetrics_t; 203 204 205 // Workload bits 206 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 207 #define WORKLOAD_PPLIB_VIDEO_BIT 2 208 #define WORKLOAD_PPLIB_VR_BIT 3 209 #define WORKLOAD_PPLIB_COMPUTE_BIT 4 210 #define WORKLOAD_PPLIB_CUSTOM_BIT 5 211 #define WORKLOAD_PPLIB_COUNT 6 212 213 #define TABLE_BIOS_IF 0 // Called by BIOS 214 #define TABLE_WATERMARKS 1 // Called by Driver 215 #define TABLE_CUSTOM_DPM 2 // Called by Driver 216 #define TABLE_SPARE1 3 217 #define TABLE_DPMCLOCKS 4 // Called by Driver 218 #define TABLE_MOMENTARY_PM 5 // Called by Tools 219 #define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log 220 #define TABLE_SMU_METRICS 7 // Called by Driver 221 #define TABLE_COUNT 8 222 223 224 #endif 225
Indexes created Mon Sep 22 05:09:51 GMT 2025