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      1 /*	$NetBSD: imx51_ipuv3reg.h,v 1.2 2014/11/07 11:54:18 hkenken Exp $	*/
      2 /*
      3  * Copyright (c) 2011, 2012  Genetec Corporation.  All rights reserved.
      4  * Written by Hashimoto Kenichi for Genetec Corporation.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     17  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     18  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
     19  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 #ifndef _ARM_IMX_IMX51_IPUV3REG_H
     28 #define _ARM_IMX_IMX51_IPUV3REG_H
     29 
     30 /* register offset address */
     31 
     32 /*
     33  * CM
     34  * Control Module
     35  */
     36 #define IPU_CM_CONF			0x00000000
     37 #define  CM_CONF_CSI_SEL		__BIT(31)
     38 #define  CM_CONF_IC_INPUT		__BIT(30)
     39 #define  CM_CONF_CSI1_DATA_SOURCE	__BIT(29)
     40 #define  CM_CONF_CSI0_DATA_SOURCE	__BIT(28)
     41 #define  CM_CONF_VDI_DMFC_SYNC		__BIT(27)
     42 #define  CM_CONF_IC_DMFC_SYNC		__BIT(26)
     43 #define  CM_CONF_IC_DMFC_SEL		__BIT(25)
     44 #define  CM_CONF_ISP_DOUBLE_FLOW	__BIT(24)
     45 #define  CM_CONF_IDMAC_DISABLE		__BIT(22)
     46 #define  CM_CONF_IPU_DIAGBUS_ON		__BIT(21)
     47 #define  CM_CONF_IPU_DIAGBUS_MODE	__BITS(20, 16)
     48 #define  CM_CONF_VDI_EN			__BIT(12)
     49 #define  CM_CONF_SISG_EN		__BIT(11)
     50 #define  CM_CONF_DMFC_EN		__BIT(10)
     51 #define  CM_CONF_DC_EN			__BIT(9)
     52 #define  CM_CONF_SMFC_EN		__BIT(8)
     53 #define  CM_CONF_DI1_EN			__BIT(7)
     54 #define  CM_CONF_DI0_EN			__BIT(6)
     55 #define  CM_CONF_DP_EN			__BIT(5)
     56 #define  CM_CONF_ISP_EN			__BIT(4)
     57 #define  CM_CONF_IRT_EN			__BIT(3)
     58 #define  CM_CONF_IC_EN			__BIT(2)
     59 #define  CM_CONF_CSI1_EN		__BIT(1)
     60 #define  CM_CONF_CSI0_EN		__BIT(0)
     61 #define IPU_SISG_CTRL0			0x00000004
     62 #define IPU_SISG_CTRL1			0x00000008
     63 #define IPU_CM_INT_CTRL_1		0x0000003c
     64 #define IPU_CM_INT_CTRL_2		0x00000040
     65 #define IPU_CM_INT_CTRL_3		0x00000044
     66 #define IPU_CM_INT_CTRL_4		0x00000048
     67 #define IPU_CM_INT_CTRL_5		0x0000004c
     68 #define IPU_CM_INT_CTRL_6		0x00000050
     69 #define IPU_CM_INT_CTRL_7		0x00000054
     70 #define IPU_CM_INT_CTRL_8		0x00000058
     71 #define IPU_CM_INT_CTRL_9		0x0000005c
     72 #define IPU_CM_INT_CTRL_10		0x00000060
     73 #define IPU_CM_INT_CTRL_11		0x00000064
     74 #define IPU_CM_INT_CTRL_12		0x00000068
     75 #define IPU_CM_INT_CTRL_13		0x0000006c
     76 #define IPU_CM_INT_CTRL_14		0x00000070
     77 #define IPU_CM_INT_CTRL_15		0x00000074
     78 #define IPU_CM_SDMA_EVENT_1		0x00000078
     79 #define IPU_CM_SDMA_EVENT_2		0x0000007c
     80 #define IPU_CM_SDMA_EVENT_3		0x00000080
     81 #define IPU_CM_SDMA_EVENT_4		0x00000084
     82 #define IPU_CM_SDMA_EVENT_7		0x00000088
     83 #define IPU_CM_SDMA_EVENT_8		0x0000008c
     84 #define IPU_CM_SDMA_EVENT_11		0x00000090
     85 #define IPU_CM_SDMA_EVENT_12		0x00000094
     86 #define IPU_CM_SDMA_EVENT_13		0x00000098
     87 #define IPU_CM_SDMA_EVENT_14		0x0000009c
     88 #define IPU_CM_SRM_PRI1			0x000000a0
     89 #define IPU_CM_SRM_PRI2			0x000000a4
     90 #define IPU_CM_FS_PROC_FLOW1		0x000000a8
     91 #define IPU_CM_FS_PROC_FLOW2		0x000000ac
     92 #define IPU_CM_FS_PROC_FLOW3		0x000000b0
     93 #define IPU_CM_FS_DISP_FLOW1		0x000000b4
     94 #define IPU_CM_FS_DISP_FLOW2		0x000000b8
     95 #define IPU_CM_SKIP			0x000000bc
     96 #define IPU_CM_DISP_ALT_CONF		0x000000c0
     97 #define IPU_CM_DISP_GEN			0x000000c4
     98 #define  CM_DISP_GEN_DI1_COUNTER_RELEASE	__BIT(25)
     99 #define  CM_DISP_GEN_DI0_COUNTER_RELEASE	__BIT(24)
    100 #define  CM_DISP_GEN_MCU_CSI_VSYNC_DEST	__BIT(23)
    101 #define  CM_DISP_GEN_MCU_MAX_BURST_STOP	__BIT(22)
    102 #define  CM_DISP_GEN_MCU_T		__BITS(18, 21)
    103 #define IPU_CM_DISP_ALT1		0x000000c8
    104 #define IPU_CM_DISP_ALT2		0x000000cc
    105 #define IPU_CM_DISP_ALT3		0x000000d0
    106 #define IPU_CM_DISP_ALT4		0x000000d4
    107 #define IPU_CM_SNOOP			0x000000d8
    108 #define IPU_CM_MEM_RST			0x000000dc
    109 #define  CM_MEM_START			__BIT(31)
    110 #define  CM_MEM_EN			__BITS(22, 0)
    111 #define IPU_CM_PM			0x000000e0
    112 #define IPU_CM_GPR			0x000000e4
    113 #define  CM_GPR_IPU_CH_BUF1_RDY1_CLR		__BIT(31)
    114 #define  CM_GPR_IPU_CH_BUF1_RDY0_CLR		__BIT(30)
    115 #define  CM_GPR_IPU_CH_BUF0_RDY1_CLR		__BIT(29)
    116 #define  CM_GPR_IPU_CH_BUF0_RDY0_CLR		__BIT(28)
    117 #define  CM_GPR_IPU_ALT_CH_BUF1_RDY1_CLR	__BIT(27)
    118 #define  CM_GPR_IPU_ALT_CH_BUF1_RDY0_CLR	__BIT(26)
    119 #define  CM_GPR_IPU_ALT_CH_BUF0_RDY1_CLR	__BIT(25)
    120 #define  CM_GPR_IPU_ALT_CH_BUF0_RDY0_CLR	__BIT(24)
    121 #define  CM_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS	__BIT(23)
    122 #define  CM_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS	__BIT(22)
    123 #define  CM_GPR_IPU_CH_BUF2_RDY1_CLR		__BIT(21)
    124 #define  CM_GPR_IPU_CH_BUF2_RDY0_CLR		__BIT(20)
    125 #define  CM_GPR_IPU_GP(n)			__BIT((n))
    126 #define IPU_CM_CH_DB_MODE_SEL_0		0x00000150
    127 #define IPU_CM_CH_DB_MODE_SEL_1		0x00000154
    128 #define IPU_CM_ALT_CH_DB_MODE_SEL_0	0x00000168
    129 #define IPU_CM_ALT_CH_DB_MODE_SEL_1	0x0000016c
    130 #define IPU_CM_CH_TRB_MODE_SEL_0	0x00000178
    131 #define IPU_CM_CH_TRB_MODE_SEL_1	0x0000017c
    132 #define IPU_CM_INT_STAT_1		0x00000200
    133 #define IPU_CM_INT_STAT_2		0x00000204
    134 #define IPU_CM_INT_STAT_3		0x00000208
    135 #define IPU_CM_INT_STAT_4		0x0000020c
    136 #define IPU_CM_INT_STAT_5		0x00000210
    137 #define IPU_CM_INT_STAT_6		0x00000214
    138 #define IPU_CM_INT_STAT_7		0x00000218
    139 #define IPU_CM_INT_STAT_8		0x0000021c
    140 #define IPU_CM_INT_STAT_9		0x00000220
    141 #define IPU_CM_INT_STAT_10		0x00000224
    142 #define IPU_CM_INT_STAT_11		0x00000228
    143 #define IPU_CM_INT_STAT_12		0x0000022c
    144 #define IPU_CM_INT_STAT_13		0x00000230
    145 #define IPU_CM_INT_STAT_14		0x00000234
    146 #define IPU_CM_INT_STAT_15		0x00000238
    147 #define IPU_CM_CUR_BUF_0		0x0000023c
    148 #define IPU_CM_CUR_BUF_1		0x00000240
    149 #define IPU_CM_ALT_CUR_BUF_0		0x00000244
    150 #define IPU_CM_ALT_CUR_BUF_1		0x00000248
    151 #define IPU_CM_SRM_STAT			0x0000024c
    152 #define IPU_CM_PROC_TASKS_STAT		0x00000250
    153 #define IPU_CM_DISP_TASKS_STAT		0x00000254
    154 #define IPU_CM_TRIPLE_CUR_BUF_0		0x00000258
    155 #define IPU_CM_TRIPLE_CUR_BUF_1		0x0000025c
    156 #define IPU_CM_TRIPLE_CUR_BUF_2		0x00000260
    157 #define IPU_CM_TRIPLE_CUR_BUF_3		0x00000264
    158 #define IPU_CM_CH_BUF0_RDY0		0x00000268
    159 #define IPU_CM_CH_BUF0_RDY1		0x0000026c
    160 #define IPU_CM_CH_BUF1_RDY0		0x00000270
    161 #define IPU_CM_CH_BUF1_RDY1		0x00000274
    162 #define IPU_CM_ALT_CH_BUF0_RDY0		0x00000278
    163 #define IPU_CM_ALT_CH_BUF0_RDY1		0x0000027c
    164 #define IPU_CM_ALT_CH_BUF1_RDY0		0x00000280
    165 #define IPU_CM_ALT_CH_BUF1_RDY1		0x00000284
    166 #define IPU_CM_CH_BUF2_RDY0		0x00000288
    167 #define IPU_CM_CH_BUF2_RDY1		0x0000028c
    168 
    169 /*
    170  * IDMAC
    171  * Image DMA Controller
    172  */
    173 #define IPU_IDMAC_CONF		0x00000000
    174 #define IPU_IDMAC_CH_EN_1	0x00000004
    175 #define IPU_IDMAC_CH_EN_2	0x00000008
    176 #define IPU_IDMAC_SEP_ALPHA	0x0000000c
    177 #define IPU_IDMAC_ALT_SEP_ALPHA	0x00000010
    178 #define IPU_IDMAC_CH_PRI_1	0x00000014
    179 #define IPU_IDMAC_CH_PRI_2	0x00000018
    180 #define IPU_IDMAC_WM_EN_1	0x0000001c
    181 #define IPU_IDMAC_WM_EN_2	0x00000020
    182 #define IPU_IDMAC_LOCK_EN_1	0x00000024
    183 #define IPU_IDMAC_LOCK_EN_2	0x00000028
    184 #define IPU_IDMAC_SUB_ADDR_0	0x0000002c
    185 #define IPU_IDMAC_SUB_ADDR_1	0x00000030
    186 #define IPU_IDMAC_SUB_ADDR_2	0x00000034
    187 #define IPU_IDMAC_SUB_ADDR_3	0x00000038
    188 #define IPU_IDMAC_SUB_ADDR_4	0x0000003c
    189 #define IPU_IDMAC_BNDM_EN_1	0x00000040
    190 #define IPU_IDMAC_BNDM_EN_2	0x00000044
    191 #define IPU_IDMAC_SC_CORD	0x00000048
    192 #define IPU_IDMAC_SC_CORD1	0x0000004c
    193 #define IPU_IDMAC_CH_BUSY_1	0x00000100
    194 #define IPU_IDMAC_CH_BUSY_2	0x00000104
    195 
    196 #define CH_PANNEL_BG	23
    197 #define CH_PANNEL_FG	27
    198 
    199 /*
    200  * DP
    201  * Display Port
    202  */
    203 #define IPU_DP_DEBUG_CNT	0x000000bc
    204 #define IPU_DP_DEBUG_STAT	0x000000c0
    205 
    206 /*
    207  * IC
    208  * Image Converter
    209  */
    210 #define IPU_IC_CONF		0x00000000
    211 #define IPU_IC_PRP_ENC_RSC	0x00000004
    212 #define IPU_IC_PRP_VF_RSC	0x00000008
    213 #define IPU_IC_PP_RSC		0x0000000c
    214 #define IPU_IC_CMBP_1		0x00000010
    215 #define IPU_IC_CMBP_2		0x00000014
    216 #define IPU_IC_IDMAC_1		0x00000018
    217 #define IPU_IC_IDMAC_2		0x0000001c
    218 #define IPU_IC_IDMAC_3		0x00000020
    219 #define IPU_IC_IDMAC_4		0x00000024
    220 
    221 /*
    222  * CSI
    223  * Camera Sensor Interface
    224  */
    225 #define IPU_CSI0_SENS_CONF	0x00000000
    226 #define IPU_CSI0_SENS_FRM_SIZE	0x00000004
    227 #define IPU_CSI0_ACT_FRM_SIZE	0x00000008
    228 #define IPU_CSI0_OUT_FRM_CTRL	0x0000000c
    229 #define IPU_CSI0_TST_CTRL	0x00000010
    230 #define IPU_CSI0_CCIR_CODE_1	0x00000014
    231 #define IPU_CSI0_CCIR_CODE_2	0x00000018
    232 #define IPU_CSI0_CCIR_CODE_3	0x0000001c
    233 #define IPU_CSI0_DI		0x00000020
    234 #define IPU_CSI0_SKIP		0x00000024
    235 #define IPU_CSI0_CPD_CTRL	0x00000028
    236 #define IPU_CSI0_CPD_OFFSET1	0x000000ec
    237 #define IPU_CSI0_CPD_OFFSET2	0x000000f0
    238 
    239 #define IPU_CSI1_SENS_CONF	0x00000000
    240 #define IPU_CSI1_SENS_FRM_SIZE	0x00000004
    241 #define IPU_CSI1_ACT_FRM_SIZE	0x00000008
    242 #define IPU_CSI1_OUT_FRM_CTRL	0x0000000c
    243 #define IPU_CSI1_TST_CTRL	0x00000010
    244 #define IPU_CSI1_CCIR_CODE_1	0x00000014
    245 #define IPU_CSI1_CCIR_CODE_2	0x00000018
    246 #define IPU_CSI1_CCIR_CODE_3	0x0000001c
    247 #define IPU_CSI1_DI		0x00000020
    248 #define IPU_CSI1_SKIP		0x00000024
    249 #define IPU_CSI1_CPD_CTRL	0x00000028
    250 #define IPU_CSI1_CPD_OFFSET1	0x000000ec
    251 #define IPU_CSI1_CPD_OFFSET2	0x000000f0
    252 
    253 /*
    254  * DI
    255  * Display Interface
    256  */
    257 #define IPU_DI_GENERAL			0x00000000
    258 #define  DI_GENERAL_DISP_Y_SEL		__BITS(30, 28)
    259 #define  DI_GENERAL_CLOCK_STOP_MODE	__BITS(27, 24)
    260 #define  DI_GENERAL_DISP_CLOCK_INIT	__BIT(23)
    261 #define  DI_GENERAL_MASK_SEL		__BIT(22)
    262 #define  DI_GENERAL_VSYNC_EXT		__BIT(21)
    263 #define  DI_GENERAL_CLK_EXT		__BIT(20)
    264 #define  DI_GENERAL_WATCHDOG_MODE	__BITS(19, 18)
    265 #define  DI_GENERAL_POLARITY_DISP_CLK	__BIT(17)
    266 #define  DI_GENERAL_SYNC_COUNT_SEL	__BITS(15, 12)
    267 #define  DI_GENERAL_ERR_TREATMENT	__BIT(11)
    268 #define  DI_GENERAL_ERM_VSYNC_SEL	__BIT(10)
    269 #define  DI_GENERAL_POLARITY_CS(n)	(1 << ((n) + 8))
    270 #define  DI_GENERAL_POLARITY(n)		(1 << ((n) - 1))
    271 
    272 #define IPU_DI_BS_CLKGEN0		0x00000004
    273 #define  DI_BS_CLKGEN0_OFFSET		__BITS(24, 16)
    274 #define  DI_BS_CLKGEN0_PERIOD		__BITS(11, 0)
    275 #define IPU_DI_BS_CLKGEN1		0x00000008
    276 #define  DI_BS_CLKGEN1_DOWN		__BITS(24, 16)
    277 #define  DI_BS_CLKGEN1_UP		__BITS(8, 0)
    278 #define IPU_DI_SW_GEN0(n)		(0x0000000c + ((n) - 1) * 4)
    279 #define  DI_SW_GEN0_RUN_VAL		__BITS(30, 19)
    280 #define  DI_SW_GEN0_RUN_RESOL		__BITS(18, 16)
    281 #define  DI_SW_GEN0_OFFSET_VAL		__BITS(14,  3)
    282 #define  DI_SW_GEN0_OFFSET_RESOL	__BITS( 2,  0)
    283 #define  __DI_SW_GEN0(run_val, run_resol, offset_val, offset_resol)	\
    284 	(((run_val) << 19) | ((run_resol) << 16) | 			\
    285 	 ((offset_val) << 3) | (offset_resol))
    286 #define IPU_DI_SW_GEN1(n)		(0x00000030 + ((n) - 1) * 4)
    287 #define  DI_SW_GEN1_CNT_POL_GEN_EN	__BITS(30, 29)
    288 #define  DI_SW_GEN1_CNT_AUTO_RELOAD	__BIT(28)
    289 #define  DI_SW_GEN1_CNT_CLR_SEL		__BITS(27, 25)
    290 #define  DI_SW_GEN1_CNT_DOWN		__BITS(24, 16)
    291 #define  DI_SW_GEN1_CNT_POL_TRIG_SEL	__BITS(14, 12)
    292 #define  DI_SW_GEN1_CNT_POL_CLR_SEL	__BITS(11,  9)
    293 #define  DI_SW_GEN1_CNT_UP		__BITS( 8,  0)
    294 #define  __DI_SW_GEN1(pol_gen_en, auto_reload, clr_sel, down, pol_trig_sel, pol_clr_sel, up) \
    295 	(((pol_gen_en) << 29) | ((auto_reload) << 28) | \
    296 	 ((clr_sel) << 25) |				\
    297 	    ((down) << 16) | ((pol_trig_sel) << 12) |	\
    298 	 ((pol_clr_sel) << 9) | (up))
    299 #define IPU_DI_SYNC_AS_GEN		0x00000054
    300 #define  DI_SYNC_AS_GEN_SYNC_START_EN	__BIT(28)
    301 #define  DI_SYNC_AS_GEN_VSYNC_SEL	__BITS(15, 13)
    302 #define  DI_SYNC_AS_GEN_SYNC_START	__BITS(11,  0)
    303 #define IPU_DI_DW_GEN(n)		(0x00000058 + (n) * 4)
    304 #define  DI_DW_GEN_ACCESS_SIZE		__BITS(31, 24)
    305 #define  DI_DW_GEN_COMPONNENT_SIZE	__BITS(23, 16)
    306 #define  DI_DW_GEN_PIN(n)		__BITS((((n) - 11) * 2) + 1, \
    307 					       ((n) - 11) * 2)
    308 #define IPU_DI_DW_SET(n, m)	(0x00000088 + (n) * 4 + (m) * 0x30)
    309 #define  DI_DW_SET_DOWN		__BITS(24, 16)
    310 #define  DI_DW_SET_UP		__BITS(8, 0)
    311 #define IPU_DI_STP_REP(n)	(0x00000148 + ((n - 1) / 2) * 4)
    312 #define  DI_STP_REP(n)		(__BITS(11, 0) << (((n - 1) % 2) * 16))
    313 #define IPU_DI_SER_CONF			0x0000015c
    314 #define IPU_DI_SSC			0x00000160
    315 #define IPU_DI_POL			0x00000164
    316 #define  DI_POL_DRDY_POLARITY_17 	__BIT(6)
    317 #define  DI_POL_DRDY_POLARITY_16 	__BIT(5)
    318 #define  DI_POL_DRDY_POLARITY_15 	__BIT(4)
    319 #define  DI_POL_DRDY_POLARITY_14 	__BIT(3)
    320 #define  DI_POL_DRDY_POLARITY_13 	__BIT(2)
    321 #define  DI_POL_DRDY_POLARITY_12 	__BIT(1)
    322 #define  DI_POL_DRDY_POLARITY_11 	__BIT(0)
    323 #define IPU_DI_AW0			0x00000168
    324 #define IPU_DI_AW1			0x0000016c
    325 #define IPU_DI_SCR_CONF			0x00000170
    326 #define IPU_DI_STAT			0x00000174
    327 
    328 /*
    329  * SMFC
    330  * Sensor Multi FIFO Controller
    331  */
    332 #define IPU_SMFC_MAP	0x00000000
    333 #define IPU_SMFC_WMC	0x00000004
    334 #define IPU_SMFC_BS	0x00000008
    335 
    336 /*
    337  * DC
    338  * Display Controller
    339  */
    340 #define IPU_DC_READ_CH_CONF	0x00000000
    341 #define IPU_DC_READ_CH_ADDR	0x00000004
    342 
    343 #define IPU_DC_RL0_CH_0		0x00000008
    344 #define IPU_DC_RL1_CH_0		0x0000000c
    345 #define IPU_DC_RL2_CH_0		0x00000010
    346 #define IPU_DC_RL3_CH_0		0x00000014
    347 #define IPU_DC_RL4_CH_0		0x00000018
    348 #define IPU_DC_WR_CH_CONF_1	0x0000001c
    349 #define IPU_DC_WR_CH_ADDR_1	0x00000020
    350 #define IPU_DC_RL0_CH_1		0x00000024
    351 #define IPU_DC_RL1_CH_1		0x00000028
    352 #define IPU_DC_RL2_CH_1		0x0000002c
    353 #define IPU_DC_RL3_CH_1		0x00000030
    354 #define IPU_DC_RL4_CH_1		0x00000034
    355 #define IPU_DC_WR_CH_CONF_2	0x00000038
    356 #define IPU_DC_WR_CH_ADDR_2	0x0000003c
    357 #define IPU_DC_RL0_CH_2		0x00000040
    358 #define IPU_DC_RL1_CH_2		0x00000044
    359 #define IPU_DC_RL2_CH_2		0x00000048
    360 #define IPU_DC_RL3_CH_2		0x0000004c
    361 #define IPU_DC_RL4_CH_2		0x00000050
    362 #define IPU_DC_CMD_CH_CONF_3	0x00000054
    363 #define IPU_DC_CMD_CH_CONF_4	0x00000058
    364 #define IPU_DC_WR_CH_CONF_5	0x0000005c
    365 #define IPU_DC_WR_CH_ADDR_5	0x00000060
    366 #define IPU_DC_RL0_CH_5		0x00000064
    367 #define IPU_DC_RL1_CH_5		0x00000068
    368 #define IPU_DC_RL2_CH_5		0x0000006c
    369 #define IPU_DC_RL3_CH_5		0x00000070
    370 #define IPU_DC_RL4_CH_5		0x00000074
    371 #define IPU_DC_WR_CH_CONF_6	0x00000078
    372 #define IPU_DC_WR_CH_ADDR_6	0x0000007c
    373 #define IPU_DC_RL0_CH_6		0x00000080
    374 #define IPU_DC_RL1_CH_6		0x00000084
    375 #define IPU_DC_RL2_CH_6		0x00000088
    376 #define IPU_DC_RL3_CH_6		0x0000008c
    377 #define IPU_DC_RL4_CH_6		0x00000090
    378 #define IPU_DC_WR_CH_CONF1_8	0x00000094
    379 #define IPU_DC_WR_CH_CONF2_8	0x00000098
    380 #define IPU_DC_RL1_CH_8		0x0000009c
    381 #define IPU_DC_RL2_CH_8		0x000000a0
    382 #define IPU_DC_RL3_CH_8		0x000000a4
    383 #define IPU_DC_RL4_CH_8		0x000000a8
    384 #define IPU_DC_RL5_CH_8		0x000000ac
    385 #define IPU_DC_RL6_CH_8		0x000000b0
    386 #define IPU_DC_WR_CH_CONF1_9	0x000000b4
    387 #define IPU_DC_WR_CH_CONF2_9	0x000000b8
    388 #define IPU_DC_RL1_CH_9		0x000000bc
    389 #define IPU_DC_RL2_CH_9		0x000000c0
    390 #define IPU_DC_RL3_CH_9		0x000000c4
    391 #define IPU_DC_RL4_CH_9		0x000000c8
    392 #define IPU_DC_RL5_CH_9		0x000000cc
    393 #define IPU_DC_RL6_CH_9		0x000000d0
    394 
    395 #define IPU_DC_RL(chan_base, evt)	((chan_base) + (evt / 2) *0x4)
    396 #define  DC_RL_CH_0		IPU_DC_RL0_CH_0
    397 #define  DC_RL_CH_1		IPU_DC_RL0_CH_1
    398 #define  DC_RL_CH_2		IPU_DC_RL0_CH_2
    399 #define  DC_RL_CH_5		IPU_DC_RL0_CH_5
    400 #define  DC_RL_CH_6		IPU_DC_RL0_CH_6
    401 #define  DC_RL_CH_8		IPU_DC_RL0_CH_8
    402 
    403 #define  DC_RL_EVT_NF		0
    404 #define  DC_RL_EVT_NL		1
    405 #define  DC_RL_EVT_EOF		2
    406 #define  DC_RL_EVT_NFIELD	3
    407 #define  DC_RL_EVT_EOL		4
    408 #define  DC_RL_EVT_EOFIELD	5
    409 #define  DC_RL_EVT_NEW_ADDR	6
    410 #define  DC_RL_EVT_NEW_CHAN	7
    411 #define  DC_RL_EVT_NEW_DATA	8
    412 
    413 #define IPU_DC_GEN		0x000000d4
    414 #define IPU_DC_DISP_CONF1_0	0x000000d8
    415 #define IPU_DC_DISP_CONF1_1	0x000000dc
    416 #define IPU_DC_DISP_CONF1_2	0x000000e0
    417 #define IPU_DC_DISP_CONF1_3	0x000000e4
    418 #define IPU_DC_DISP_CONF2_0	0x000000e8
    419 #define IPU_DC_DISP_CONF2_1	0x000000ec
    420 #define IPU_DC_DISP_CONF2_2	0x000000f0
    421 #define IPU_DC_DISP_CONF2_3	0x000000f4
    422 #define IPU_DC_DI0_CONF_1	0x000000f8
    423 #define IPU_DC_DI0_CONF_2	0x000000fc
    424 #define IPU_DC_DI1_CONF_1	0x00000100
    425 #define IPU_DC_DI1_CONF_2	0x00000104
    426 
    427 #define IPU_DC_MAP_CONF_PNTR(n)	(0x00000108 + (n) * 4)
    428 #define IPU_DC_MAP_CONF_0	0x00000108
    429 #define IPU_DC_MAP_CONF_1	0x0000010c
    430 #define IPU_DC_MAP_CONF_2	0x00000110
    431 #define IPU_DC_MAP_CONF_3	0x00000114
    432 #define IPU_DC_MAP_CONF_4	0x00000118
    433 #define IPU_DC_MAP_CONF_5	0x0000011c
    434 #define IPU_DC_MAP_CONF_6	0x00000120
    435 #define IPU_DC_MAP_CONF_7	0x00000124
    436 #define IPU_DC_MAP_CONF_8	0x00000128
    437 #define IPU_DC_MAP_CONF_9	0x0000012c
    438 #define IPU_DC_MAP_CONF_10	0x00000130
    439 #define IPU_DC_MAP_CONF_11	0x00000134
    440 #define IPU_DC_MAP_CONF_12	0x00000138
    441 #define IPU_DC_MAP_CONF_13	0x0000013c
    442 #define IPU_DC_MAP_CONF_14	0x00000140
    443 
    444 #define IPU_DC_MAP_CONF_MASK(n)	(0x00000144 + (n) * 4)
    445 #define IPU_DC_MAP_CONF_15	0x00000144
    446 #define IPU_DC_MAP_CONF_16	0x00000148
    447 #define IPU_DC_MAP_CONF_17	0x0000014c
    448 #define IPU_DC_MAP_CONF_18	0x00000150
    449 #define IPU_DC_MAP_CONF_19	0x00000154
    450 #define IPU_DC_MAP_CONF_20	0x00000158
    451 #define IPU_DC_MAP_CONF_21	0x0000015c
    452 #define IPU_DC_MAP_CONF_22	0x00000160
    453 #define IPU_DC_MAP_CONF_23	0x00000164
    454 #define IPU_DC_MAP_CONF_24	0x00000168
    455 #define IPU_DC_MAP_CONF_25	0x0000016c
    456 #define IPU_DC_MAP_CONF_26	0x00000170
    457 
    458 #define IPU_DC_UGDE(m, n)	(0x00000174 + (m) * 0x10 + (n) +4)
    459 #define IPU_DC_UGDE0_0		0x00000174
    460 #define IPU_DC_UGDE0_1		0x00000178
    461 #define IPU_DC_UGDE0_2		0x0000017c
    462 #define IPU_DC_UGDE0_3		0x00000180
    463 #define IPU_DC_UGDE1_0		0x00000184
    464 #define IPU_DC_UGDE1_1		0x00000188
    465 #define IPU_DC_UGDE1_2		0x0000018c
    466 #define IPU_DC_UGDE1_3		0x00000190
    467 #define IPU_DC_UGDE2_0		0x00000194
    468 #define IPU_DC_UGDE2_1		0x00000198
    469 #define IPU_DC_UGDE2_2		0x0000019c
    470 #define IPU_DC_UGDE2_3		0x000001a0
    471 #define IPU_DC_UGDE3_0		0x000001a4
    472 #define IPU_DC_UGDE3_1		0x000001a8
    473 #define IPU_DC_UGDE3_2		0x000001ac
    474 #define IPU_DC_UGDE3_3		0x000001b0
    475 #define IPU_DC_LLA0		0x000001b4
    476 #define IPU_DC_LLA1		0x000001b8
    477 #define IPU_DC_R_LLA0		0x000001bc
    478 #define IPU_DC_R_LLA1		0x000001c0
    479 #define IPU_DC_WR_CH_ADDR_5_ALT	0x000001c4
    480 #define IPU_DC_STAT		0x000001c8
    481 
    482 /*
    483  * DMFC
    484  * Display Multi FIFO Controller
    485  */
    486 #define IPU_DMFC_RD_CHAN		0x00000000
    487 #define  DMFC_RD_CHAN_PPW_C		__BITS(25,24)
    488 #define  DMFC_RD_CHAN_WM_DR_0		__BITS(23,21)
    489 #define  DMFC_RD_CHAN_WM_SET_0		__BITS(20,18)
    490 #define  DMFC_RD_CHAN_WM_EN_0		__BIT(17)
    491 #define  DMFC_RD_CHAN_BURST_SIZE_0	__BITS( 7, 6)
    492 #define IPU_DMFC_WR_CHAN		0x00000004
    493 #define  DMFC_WR_CHAN_BUSRT_SIZE_2C	__BITS(31,30)
    494 #define  DMFC_WR_CHAN_FIFO_SIZE_2C	__BITS(29,27)
    495 #define  DMFC_WR_CHAN_ST_ADDR_2C	__BITS(26,24)
    496 #define  DMFC_WR_CHAN_BURST_SIZE_1C	__BITS(23,22)
    497 #define  DMFC_WR_CHAN_FIFO_SIZE_1C	__BITS(21,19)
    498 #define  DMFC_WR_CHAN_ST_ADDR_1C	__BITS(18,16)
    499 #define  DMFC_WR_CHAN_BURST_SIZE_2	__BITS(15,14)
    500 #define  DMFC_WR_CHAN_FIFO_SIZE_2	__BITS(13,11)
    501 #define  DMFC_WR_CHAN_ST_ADDR_2		__BITS(10, 8)
    502 #define  DMFC_WR_CHAN_BURST_SIZE_1	__BITS( 7, 6)
    503 #define  DMFC_WR_CHAN_FIFO_SIZE_1	__BITS( 5, 3)
    504 #define  DMFC_WR_CHAN_ST_ADDR_1		__BITS( 2, 0)
    505 #define IPU_DMFC_WR_CHAN_DEF		0x00000008
    506 #define  DMFC_WR_CHAN_DEF_WM_CLR_2C	__BITS(31,29)
    507 #define  DMFC_WR_CHAN_DEF_WM_SET_2C	__BITS(28,26)
    508 #define  DMFC_WR_CHAN_DEF_WM_EN_2C	__BIT(25)
    509 #define  DMFC_WR_CHAN_DEF_WM_CLR_1C	__BITS(23,21)
    510 #define  DMFC_WR_CHAN_DEF_WM_SET_1C	__BITS(20,18)
    511 #define  DMFC_WR_CHAN_DEF_WM_EN_1C	__BIT(17)
    512 #define  DMFC_WR_CHAN_DEF_WM_CLR_2	__BITS(15,13)
    513 #define  DMFC_WR_CHAN_DEF_WM_SET_2	__BITS(12,10)
    514 #define  DMFC_WR_CHAN_DEF_WM_EN_2	__BIT(9)
    515 #define  DMFC_WR_CHAN_DEF_WM_CLR_1	__BITS( 7, 5)
    516 #define  DMFC_WR_CHAN_DEF_WM_SET_1	__BITS( 3, 2)
    517 #define  DMFC_WR_CHAN_DEF_WM_EN_1	__BIT(1)
    518 #define IPU_DMFC_DP_CHAN		0x0000000c
    519 #define  DMFC_DP_CHAN_BUSRT_SIZE_6F	__BITS(31,30)
    520 #define  DMFC_DP_CHAN_FIFO_SIZE_6F	__BITS(29,27)
    521 #define  DMFC_DP_CHAN_ST_ADDR_6F	__BITS(26,24)
    522 #define  DMFC_DP_CHAN_BURST_SIZE_6B	__BITS(23,22)
    523 #define  DMFC_DP_CHAN_FIFO_SIZE_6B	__BITS(21,19)
    524 #define  DMFC_DP_CHAN_ST_ADDR_6B	__BITS(18,16)
    525 #define  DMFC_DP_CHAN_BURST_SIZE_5F	__BITS(15,14)
    526 #define  DMFC_DP_CHAN_FIFO_SIZE_5F	__BITS(13,11)
    527 #define  DMFC_DP_CHAN_ST_ADDR_5F	__BITS(10, 8)
    528 #define  DMFC_DP_CHAN_BURST_SIZE_5B	__BITS( 7, 6)
    529 #define  DMFC_DP_CHAN_FIFO_SIZE_5B	__BITS( 5, 3)
    530 #define  DMFC_DP_CHAN_ST_ADDR_5B	__BITS( 2, 0)
    531 #define IPU_DMFC_DP_CHAN_DEF		0x00000010
    532 #define  DMFC_DP_CHAN_DEF_WM_CLR_6F	__BITS(31,29)
    533 #define  DMFC_DP_CHAN_DEF_WM_SET_6F	__BITS(28,26)
    534 #define  DMFC_DP_CHAN_DEF_WM_EN_6F	__BIT(25)
    535 #define  DMFC_DP_CHAN_DEF_WM_CLR_6B	__BITS(23,21)
    536 #define  DMFC_DP_CHAN_DEF_WM_SET_6B	__BITS(20,18)
    537 #define  DMFC_DP_CHAN_DEF_WM_EN_6B	__BIT(17)
    538 #define  DMFC_DP_CHAN_DEF_WM_CLR_5F	__BITS(15,13)
    539 #define  DMFC_DP_CHAN_DEF_WM_SET_5F	__BITS(12,10)
    540 #define  DMFC_DP_CHAN_DEF_WM_EN_5F	__BIT(9)
    541 #define  DMFC_DP_CHAN_DEF_WM_CLR_5B	__BITS( 7, 5)
    542 #define  DMFC_DP_CHAN_DEF_WM_SET_5B	__BITS( 4, 2)
    543 #define  DMFC_DP_CHAN_DEF_WM_EN_5B	__BIT(1)
    544 #define IPU_DMFC_GENERAL1		0x00000014
    545 #define  DMFC_GENERAL1_WAIT4EOT_9	__BIT(24)
    546 #define  DMFC_GENERAL1_WAIT4EOT_6F	__BIT(23)
    547 #define  DMFC_GENERAL1_WAIT4EOT_6B	__BIT(22)
    548 #define  DMFC_GENERAL1_WAIT4EOT_5F	__BIT(21)
    549 #define  DMFC_GENERAL1_WAIT4EOT_5B	__BIT(20)
    550 #define  DMFC_GENERAL1_WAIT4EOT_4	__BIT(19)
    551 #define  DMFC_GENERAL1_WAIT4EOT_3	__BIT(18)
    552 #define  DMFC_GENERAL1_WAIT4EOT_2	__BIT(17)
    553 #define  DMFC_GENERAL1_WAIT4EOT_1	__BIT(16)
    554 #define  DMFC_GENERAL1_WM_CLR_9		__BITS(15,13)
    555 #define  DMFC_GENERAL1_WM_SET_9		__BITS(12,10)
    556 #define  DMFC_GENERAL1_BURST_SIZE_9	__BITS( 6, 5)
    557 #define  DMFC_GENERAL1_DCDP_SYNC_PR	__BITS( 1, 0)
    558 #define   DCDP_SYNC_PR_FORBIDDEN	0
    559 #define   DCDP_SYNC_PR_DC_DP		1
    560 #define   DCDP_SYNC_PR_DP_DC		2
    561 #define   DCDP_SYNC_PR_ROUNDROBIN	3
    562 #define IPU_DMFC_GENERAL2		0x00000018
    563 #define  DMFC_GENERAL2_FRAME_HEIGHT_RD	__BITS(28,16)
    564 #define  DMFC_GENERAL2_FRAME_WIDTH_RD	__BITS(12, 0)
    565 #define IPU_DMFC_IC_CTRL		0x0000001c
    566 #define  DMFC_IC_CTRL_IC_FRAME_HEIGHT_RD	__BITS(31,19)
    567 #define  DMFC_IC_CTRL_IC_FRAME_WIDTH_RD		__BITS(18, 6)
    568 #define  DMFC_IC_CTRL_IC_PPW_C			__BITS( 5, 4)
    569 #define  DMFC_IC_CTRL_IC_IN_PORT		__BITS( 2, 0)
    570 #define   IC_IN_PORT_CH28		0
    571 #define   IC_IN_PORT_CH41		1
    572 #define   IC_IN_PORT_DISABLE		2
    573 #define   IC_IN_PORT_CH23		4
    574 #define   IC_IN_PORT_CH27		5
    575 #define   IC_IN_PORT_CH24		6
    576 #define   IC_IN_PORT_CH29		7
    577 #define IPU_DMFC_WR_CHAN_ALT		0x00000020
    578 #define IPU_DMFC_WR_CHAN_DEF_ALT	0x00000024
    579 #define IPU_DMFC_DP_CHAN_ALT		0x00000028
    580 #define IPU_DMFC_DP_CHAN_DEF_ALT	0x0000002c
    581 #define  DMFC_DP_CHAN_DEF_ALT_WM_CLR_6F_ALT	__BITS(31,29)
    582 #define  DMFC_DP_CHAN_DEF_ALT_WM_SET_6F_ALT	__BITS(28,26)
    583 #define  DMFC_DP_CHAN_DEF_ALT_WM_EN_6F_ALT	__BIT(25)
    584 #define  DMFC_DP_CHAN_DEF_ALT_WM_CLR_6B_ALT	__BITS(23,21)
    585 #define  DMFC_DP_CHAN_DEF_ALT_WM_SET_6B_ALT	__BITS(20,18)
    586 #define  DMFC_DP_CHAN_DEF_ALT_WM_EN_6B_ALT	__BIT(17)
    587 #define  DMFC_DP_CHAN_DEF_ALT_WM_CLR_5B_ALT	__BITS( 7, 5)
    588 #define  DMFC_DP_CHAN_DEF_ALT_WM_SET_5B_ALT	__BITS( 4, 2)
    589 #define  DMFC_DP_CHAN_DEF_ALT_WM_EN_5B_ALT	__BIT(1)
    590 #define IPU_DMFC_GENERAL1_ALT		0x00000030
    591 #define  DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT	__BIT(23)
    592 #define  DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT	__BIT(22)
    593 #define  DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT	__BIT(20)
    594 #define  DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT	__BIT(17)
    595 #define IPU_DMFC_STAT			0x00000034
    596 #define  DMFC_STAT_IC_BUFFER_EMPTY	__BIT(25)
    597 #define  DMFC_STAT_IC_BUFFER_FULL	__BIT(24)
    598 #define  DMFC_STAT_FIFO_EMPTY(n)	__BIT(12 + (n))
    599 #define  DMFC_STAT_FIFO_FULL(n)		__BIT((n))
    600 
    601 /*
    602  * VCI
    603  * Video De Interkacing Module
    604  */
    605 #define IPU_VDI_FSIZE	0x00000000
    606 #define IPU_VDI_C	0x00000004
    607 
    608 /*
    609  * DP
    610  * Display Processor
    611  */
    612 #define IPU_DP_COM_CONF_SYNC		0x00000000
    613 #define  DP_FG_EN_SYNC			__BIT(0)
    614 #define  DP_DP_GWAM_SYNC		__BIT(2)
    615 #define IPU_DP_GRAPH_WIND_CTRL_SYNC	0x00000004
    616 #define IPU_DP_FG_POS_SYNC		0x00000008
    617 #define IPU_DP_CUR_POS_SYNC		0x0000000c
    618 #define IPU_DP_CUR_MAP_SYNC		0x00000010
    619 #define IPU_DP_CSC_SYNC_0		0x00000054
    620 #define IPU_DP_CSC_SYNC_1		0x00000058
    621 #define IPU_DP_CUR_POS_ALT		0x0000005c
    622 #define IPU_DP_COM_CONF_ASYNC0		0x00000060
    623 #define IPU_DP_GRAPH_WIND_CTRL_ASYNC0	0x00000064
    624 #define IPU_DP_FG_POS_ASYNC0		0x00000068
    625 #define IPU_DP_CUR_POS_ASYNC0		0x0000006c
    626 #define IPU_DP_CUR_MAP_ASYNC0		0x00000070
    627 #define IPU_DP_CSC_ASYNC0_0		0x000000b4
    628 #define IPU_DP_CSC_ASYNC0_1		0x000000b8
    629 #define IPU_DP_COM_CONF_ASYNC1		0x000000bc
    630 #define IPU_DP_GRAPH_WIND_CTRL_ASYNC1	0x000000c0
    631 #define IPU_DP_FG_POS_ASYNC1		0x000000c4
    632 #define IPU_DP_CUR_POS_ASYNC1		0x000000c8
    633 #define IPU_DP_CUR_MAP_ASYNC1		0x000000cc
    634 #define IPU_DP_CSC_ASYNC1_0		0x00000110
    635 #define IPU_DP_CSC_ASYNC1_1		0x00000114
    636 
    637 /* IDMA parameter */
    638 	/*
    639 	 * non-Interleaved parameter
    640 	 *
    641 	 * param 0: XV W0[ 9: 0]
    642 	 *          YV W0[18:10]
    643 	 *          XB W0[31:19]
    644 	 * param 1: YB W0[43:32]
    645 	 *          NSB W0[44]
    646 	 *          CF W0[45]
    647 	 *          UBO W0[61:46]
    648 	 * param 2: UBO W0[67:62]
    649 	 *          VBO W0[89:68]
    650 	 *          IOX W0[93:90]
    651 	 *          RDRW W0[94]
    652 	 *          Reserved W0[95]
    653 	 * param 3: Reserved W0[112:96]
    654 	 *          S0 W0[113]
    655 	 *          BNDM W0[116:114]
    656 	 *          BM W0[118:117]
    657 	 *          ROT W0[119]
    658 	 *          HF W0[120]
    659 	 *          VF W0[121]
    660 	 *          THF W0[122]
    661 	 *          CAP W0[123]
    662 	 *          CAE W0[124]
    663 	 *          FW W0[127:125]
    664 	 * param 4: FW W0[137:128]
    665 	 *          FH W0[149:138]
    666 	 * param 5: EBA0 W1[28:0]
    667 	 *          EBA1 W1[31:29]
    668 	 * param 6: EBA1 W1[57:32]
    669 	 *          ILO W1[63:58]
    670 	 * param 7: ILO W1[77:64]
    671 	 *          NPB W1[84:78]
    672 	 *          PFS W1[88:85]
    673 	 *          ALU W1[89]
    674 	 *          ALBM W1[92:90]
    675 	 *          ID W1[94:93]
    676 	 *          TH W1[95]
    677 	 * param 8: TH W1[101:96]
    678 	 *          SLY W1[115:102]
    679 	 *          WID3 W1[127:125]
    680 	 * param 9: SLUV W1[141:128]
    681 	 *          CRE W1[149]
    682 	 *
    683 	 * Interleaved parameter
    684 	 *
    685 	 * param 0: XV W0[ 9: 0]
    686 	 *          YV W0[18:10]
    687 	 *          XB W0[31:19]
    688 	 * param 1: YB W0[43:32]
    689 	 *          NSB W0[44]
    690 	 *          CF W0[45]
    691 	 *          SX W0[57:46]
    692 	 *          SY W0[61:58]
    693 	 * param 2: SY W0[68:62]
    694 	 *          NS W0[78:69]
    695 	 *          SDX W0[85:79]
    696 	 *          SM W0[95:86]
    697 	 * param 3: SCC W0[96]
    698 	 *          SCE W0[97]
    699 	 *          SDY W0[104:98]
    700 	 *          SDRX W0[105]
    701 	 *          SDRY W0[106]
    702 	 *          BPP W0[109:107]
    703 	 *	    DEC_SEL W0[111:110]
    704 	 *          DIM W0[112]
    705 	 *          SO W0[113]
    706 	 *          BNDM W0[116:114]
    707 	 *          BM W0[118:117]
    708 	 *          ROT W0[119]
    709 	 *          HF W0[120]
    710 	 *          VF W0[121]
    711 	 *          THF W0[122]
    712 	 *          CAP W0[123]
    713 	 *          CAE W0[124]
    714 	 *          FW W0[127:125]
    715 	 * param 4: FW W0[137:128]
    716 	 *          FH W0[149:138]
    717 	 * param 5: EBA0 W1[28:0]
    718 	 *          EBA1 W1[31:29]
    719 	 * param 6: EBA1 W1[57:32]
    720 	 *          ILO W1[63:58]
    721 	 * param 7: ILO W1[77:64]
    722 	 *          NPB W1[84:78]
    723 	 *          PFS W1[88:85]
    724 	 *          ALU W1[89]
    725 	 *          ALBM W1[92:90]
    726 	 *          ID W1[94:93]
    727 	 *          TH W1[95]
    728 	 * param 8: TH W1[101:96]
    729 	 *          SL W1[115:102]
    730 	 *          WID0 W1[118:116]
    731 	 *          WID1 W1[121:119]
    732 	 *          WID2 W1[124:122]
    733 	 *          WID3 W1[127:125]
    734 	 * param 9: OFS0 W1[132:128]
    735 	 *          OFS1 W1[137:133]
    736 	 *          OFS2 W1[142:138]
    737 	 *          OFS3 W1[147:143]
    738 	 *          SXYS W1[148]
    739 	 *          CRE W1[149]
    740 	 *          DEC_SEL2 W1[150]
    741 	 */
    742 
    743 #define __IDMA_PARAM(word, shift, size) \
    744 	((((word) & 0xff) << 16) | (((shift) & 0xff) << 8) | ((size) & 0xff))
    745 
    746 /* non-Interleaved parameter */
    747 /* W0 */
    748 #define IDMAC_Ch_PARAM_XV	__IDMA_PARAM(0,  0, 10)
    749 #define IDMAC_Ch_PARAM_YV	__IDMA_PARAM(0, 10,  9)
    750 #define IDMAC_Ch_PARAM_XB	__IDMA_PARAM(0, 19, 13)
    751 #define IDMAC_Ch_PARAM_YB	__IDMA_PARAM(0, 32, 12)
    752 #define IDMAC_Ch_PARAM_NSB	__IDMA_PARAM(0, 44,  1)
    753 #define IDMAC_Ch_PARAM_CF	__IDMA_PARAM(0, 45,  1)
    754 #define IDMAC_Ch_PARAM_UBO	__IDMA_PARAM(0, 46, 22)
    755 #define IDMAC_Ch_PARAM_VBO	__IDMA_PARAM(0, 68, 22)
    756 #define IDMAC_Ch_PARAM_IOX	__IDMA_PARAM(0, 90,  4)
    757 #define IDMAC_Ch_PARAM_RDRW	__IDMA_PARAM(0, 94,  1)
    758 #define IDMAC_Ch_PARAM_S0	__IDMA_PARAM(0,113,  1)
    759 #define IDMAC_Ch_PARAM_BNDM	__IDMA_PARAM(0,114,  3)
    760 #define IDMAC_Ch_PARAM_BM	__IDMA_PARAM(0,117,  2)
    761 #define IDMAC_Ch_PARAM_ROT	__IDMA_PARAM(0,119,  1)
    762 #define IDMAC_Ch_PARAM_HF	__IDMA_PARAM(0,120,  1)
    763 #define IDMAC_Ch_PARAM_VF	__IDMA_PARAM(0,121,  1)
    764 #define IDMAC_Ch_PARAM_THF	__IDMA_PARAM(0,122,  1)
    765 #define IDMAC_Ch_PARAM_CAP	__IDMA_PARAM(0,123,  1)
    766 #define IDMAC_Ch_PARAM_CAE	__IDMA_PARAM(0,124,  1)
    767 #define IDMAC_Ch_PARAM_FW	__IDMA_PARAM(0,125, 13)
    768 #define IDMAC_Ch_PARAM_FH	__IDMA_PARAM(0,138, 12)
    769 /* W1 */
    770 #define IDMAC_Ch_PARAM_EBA0	__IDMA_PARAM(1,  0, 29)
    771 #define IDMAC_Ch_PARAM_EBA1	__IDMA_PARAM(1, 29, 29)
    772 #define IDMAC_Ch_PARAM_ILO	__IDMA_PARAM(1, 58, 20)
    773 #define IDMAC_Ch_PARAM_NPB	__IDMA_PARAM(1, 78,  7)
    774 #define IDMAC_Ch_PARAM_PFS	__IDMA_PARAM(1, 85,  4)
    775 #define IDMAC_Ch_PARAM_ALU	__IDMA_PARAM(1, 89,  1)
    776 #define IDMAC_Ch_PARAM_ALBM	__IDMA_PARAM(1, 90,  3)
    777 #define IDMAC_Ch_PARAM_ID	__IDMA_PARAM(1, 93,  2)
    778 #define IDMAC_Ch_PARAM_TH	__IDMA_PARAM(1, 95,  7)
    779 #define IDMAC_Ch_PARAM_SL	__IDMA_PARAM(1,102, 14)
    780 #define IDMAC_Ch_PARAM_WID3	__IDMA_PARAM(1,125,  3)
    781 #define IDMAC_Ch_PARAM_SLUV	__IDMA_PARAM(1,128, 14)
    782 #define IDMAC_Ch_PARAM_CRE	__IDMA_PARAM(1,149,  1)
    783 
    784 /* Interleaved parameter */
    785 /* W0 */
    786 #define IDMAC_Ch_PARAM_XV	__IDMA_PARAM(0,  0, 10)
    787 #define IDMAC_Ch_PARAM_YV	__IDMA_PARAM(0, 10,  9)
    788 #define IDMAC_Ch_PARAM_XB	__IDMA_PARAM(0, 19, 13)
    789 #define IDMAC_Ch_PARAM_YB	__IDMA_PARAM(0, 32, 12)
    790 #define IDMAC_Ch_PARAM_NSB	__IDMA_PARAM(0, 44,  1)
    791 #define IDMAC_Ch_PARAM_CF	__IDMA_PARAM(0, 45,  1)
    792 #define IDMAC_Ch_PARAM_SX	__IDMA_PARAM(0, 46, 12)
    793 #define IDMAC_Ch_PARAM_SY	__IDMA_PARAM(0, 58, 11)
    794 #define IDMAC_Ch_PARAM_NS	__IDMA_PARAM(0, 69, 10)
    795 #define IDMAC_Ch_PARAM_SDX	__IDMA_PARAM(0, 79,  7)
    796 #define IDMAC_Ch_PARAM_SM	__IDMA_PARAM(0, 86, 10)
    797 #define IDMAC_Ch_PARAM_SCC	__IDMA_PARAM(0, 96,  1)
    798 #define IDMAC_Ch_PARAM_SCE	__IDMA_PARAM(0, 97,  1)
    799 #define IDMAC_Ch_PARAM_SDY	__IDMA_PARAM(0, 98,  7)
    800 #define IDMAC_Ch_PARAM_SDRX	__IDMA_PARAM(0,105,  1)
    801 #define IDMAC_Ch_PARAM_SDRY	__IDMA_PARAM(0,106,  1)
    802 #define IDMAC_Ch_PARAM_BPP	__IDMA_PARAM(0,107,  3)
    803 #define IDMAC_Ch_PARAM_DEC_SEL	__IDMA_PARAM(0,110,  2)
    804 #define IDMAC_Ch_PARAM_DIM	__IDMA_PARAM(0,112,  1)
    805 #define IDMAC_Ch_PARAM_SO	__IDMA_PARAM(0,113,  1)
    806 #define IDMAC_Ch_PARAM_BNDM	__IDMA_PARAM(0,114,  3)
    807 #define IDMAC_Ch_PARAM_BM	__IDMA_PARAM(0,117,  2)
    808 #define IDMAC_Ch_PARAM_ROT	__IDMA_PARAM(0,119,  1)
    809 #define IDMAC_Ch_PARAM_HF	__IDMA_PARAM(0,120,  1)
    810 #define IDMAC_Ch_PARAM_VF	__IDMA_PARAM(0,121,  1)
    811 #define IDMAC_Ch_PARAM_THF	__IDMA_PARAM(0,122,  1)
    812 #define IDMAC_Ch_PARAM_CAP	__IDMA_PARAM(0,123,  1)
    813 #define IDMAC_Ch_PARAM_CAE	__IDMA_PARAM(0,124,  1)
    814 #define IDMAC_Ch_PARAM_FW	__IDMA_PARAM(0,125, 13)
    815 #define IDMAC_Ch_PARAM_FH	__IDMA_PARAM(0,138, 12)
    816 /* W1 */
    817 #define IDMAC_Ch_PARAM_EBA0	__IDMA_PARAM(1,  0, 29)
    818 #define IDMAC_Ch_PARAM_EBA1	__IDMA_PARAM(1, 29, 29)
    819 #define IDMAC_Ch_PARAM_ILO	__IDMA_PARAM(1, 58, 20)
    820 #define IDMAC_Ch_PARAM_NPB	__IDMA_PARAM(1, 78,  7)
    821 #define IDMAC_Ch_PARAM_PFS	__IDMA_PARAM(1, 85,  4)
    822 #define IDMAC_Ch_PARAM_ALU	__IDMA_PARAM(1, 89,  1)
    823 #define IDMAC_Ch_PARAM_ALBM	__IDMA_PARAM(1, 90,  3)
    824 #define IDMAC_Ch_PARAM_ID	__IDMA_PARAM(1, 93,  2)
    825 #define IDMAC_Ch_PARAM_TH	__IDMA_PARAM(1, 95,  7)
    826 #define IDMAC_Ch_PARAM_SL	__IDMA_PARAM(1,102, 14)
    827 #define IDMAC_Ch_PARAM_WID0	__IDMA_PARAM(1,116,  3)
    828 #define IDMAC_Ch_PARAM_WID1	__IDMA_PARAM(1,119,  3)
    829 #define IDMAC_Ch_PARAM_WID2	__IDMA_PARAM(1,122,  3)
    830 #define IDMAC_Ch_PARAM_WID3	__IDMA_PARAM(1,125,  3)
    831 #define IDMAC_Ch_PARAM_OFS0	__IDMA_PARAM(1,128,  5)
    832 #define IDMAC_Ch_PARAM_OFS1	__IDMA_PARAM(1,133,  5)
    833 #define IDMAC_Ch_PARAM_OFS2	__IDMA_PARAM(1,138,  5)
    834 #define IDMAC_Ch_PARAM_OFS3	__IDMA_PARAM(1,143,  5)
    835 #define IDMAC_Ch_PARAM_SXYS	__IDMA_PARAM(1,148,  1)
    836 #define IDMAC_Ch_PARAM_CRE	__IDMA_PARAM(1,149,  1)
    837 #define IDMAC_Ch_PARAM_DEC_SEL2 __IDMA_PARAM(1,150,  1)
    838 
    839 #endif /* _ARM_IMX_IMX51_IPUV3REG_H */
    840