1 /* $NetBSD: p9100reg.h,v 1.6 2012/09/21 01:07:44 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #ifndef P9100_REG_H 34 #define P9100_REG_H 35 36 /* The Tadpole 3GX Technical Reference Manual lies. The ramdac registers 37 * are map in 4 byte increments, not 8. 38 */ 39 #define SCRN_RPNT_CTL_1 0x0138 /* Screen Respaint Timing Control 1 */ 40 #define VIDEO_ENABLED 0x00000020 41 #define PWRUP_CNFG 0x0194 /* Power Up Configuration */ 42 #define DAC_CMAP_WRIDX 0x0200 /* IBM RGB528 Palette Address (Write) */ 43 #define DAC_CMAP_DATA 0x0204 /* IBM RGB528 Palette Data */ 44 #define DAC_PXL_MASK 0x0208 /* IBM RGB528 Pixel Mask */ 45 #define DAC_CMAP_RDIDX 0x020c /* IBM RGB528 Palette Address (Read) */ 46 #define DAC_INDX_LO 0x0210 /* IBM RGB528 Index Low */ 47 #define DAC_INDX_HI 0x0214 /* IBM RGB528 Index High */ 48 #define DAC_INDX_DATA 0x0218 /* IBM RGB528 Index Data (Indexed Registers) */ 49 #define DAC_INDX_CTL 0x021c /* IBM RGB528 Index Control */ 50 #define DAC_INDX_AUTOINCR 0x01 51 52 #define DAC_VERSION 0x01 53 #define DAC_MISC_CLK 0x02 54 #define DAC_POWER_MGT 0x05 55 #define DAC_POWER_SCLK_DISABLE 0x10 56 #define DAC_POWER_DDOT_DISABLE 0x08 57 #define DAC_POWER_SYNC_DISABLE 0x04 58 /* Disable internal DAC clock */ 59 #define DAC_POWER_ICLK_DISABLE 0x02 60 /* Disable internal DAC power */ 61 #define DAC_POWER_IPWR_DISABLE 0x01 62 #define DAC_OPERATION 0x06 63 #define DAC_SYNC_ON_GREEN 0x08 64 #define DAC_PALETTE_CTRL 0x07 65 #define DAC_PIXEL_FMT 0x0a 66 #define DAC_8BIT_CTRL 0x0b 67 #define DAC8_DIRECT_COLOR 0x01 68 #define DAC_16BIT_CTRL 0x0c 69 #define DAC16_INDIRECT_COLOR 0x00 70 #define DAC16_DYNAMIC_COLOR 0x40 71 #define DAC16_DIRECT_COLOR 0xc0 72 #define DAC16_BYPASS_POLARITY 0x20 73 #define DAC16_BIT_FILL_LINEAR 0x04 74 #define DAC16_555 0x00 75 #define DAC16_565 0x02 76 #define DAC16_CONTIGUOUS 0x01 77 #define DAC_24BIT_CTRL 0x0d 78 #define DAC24_DIRECT_COLOR 0x01 79 #define DAC_32BIT_CTRL 0x0e 80 #define DAC32_BYPASS_POLARITY 0x04 81 #define DAC32_INDIRECT_COLOR 0x00 82 #define DAC32_DYNAMIC_COLOR 0x01 83 #define DAC32_DIRECT_COLOR 0x03 84 #define DAC_VCO_DIV 0x16 85 #define DAC_PLL0 0x20 86 #define DAC_MISC_1 0x70 87 #define DAC_MISC_2 0x71 88 #define DAC_MISC_3 0x72 89 90 #define DAC_CURSOR_CTL 0x30 91 #define DAC_CURSOR_OFF 0x00 92 #define DAC_CURSOR_WIN 0x02 93 #define DAC_CURSOR_X11 0x03 94 #define DAC_CURSOR_64 0x04 /* clear for 32x32 cursor */ 95 #define DAC_CURSOR_X 0x31 /* 8-low, 8-high */ 96 #define DAC_CURSOR_Y 0x33 /* 8-low, 8-high */ 97 #define DAC_CURSOR_HOT_X 0x35 /* hotspot */ 98 #define DAC_CURSOR_HOT_Y 0x36 99 #define DAC_CURSOR_COL_1 0x40 /* red. green and blue */ 100 #define DAC_CURSOR_COL_2 0x43 101 #define DAC_CURSOR_COL_3 0x46 102 #define DAC_PIX_PLL 0x8e 103 #define DAC_CURSOR_DATA 0x100 104 105 /* main registers */ 106 #define SYS_CONF 0x0004 /* System Configuration Register */ 107 #define BUFFER_WRITE_1 0x0200 /* writes got o buffer 1 */ 108 #define BUFFER_WRITE_0 0x0000 /* writes go to buffer 0 */ 109 #define BUFFER_READ_1 0x0400 /* read from buffer 1 */ 110 #define BUFFER_READ_0 0x0000 111 #define MEM_SWAP_BITS 0x0800 /* swap bits when accessing VRAM */ 112 #define MEM_SWAP_BYTES 0x1000 /* swap bytes when accessing VRAM */ 113 #define MEM_SWAP_HWORDS 0x2000 /* swap halfwords when accessing VRAM */ 114 #define SHIFT_0 14 115 #define SHIFT_1 17 116 #define SHIFT_2 20 117 #define SHIFT_3 29 118 #define PIXEL_SHIFT 26 119 #define SWAP_SHIFT 11 120 /* this is what the 3GX manual says */ 121 #define SC_8BIT 2 122 #define SC_16BIT 3 123 #define SC_24BIT 7 124 #define SC_32BIT 5 125 126 /* video controller registers */ 127 #define VID_HCOUNTER 0x104 128 #define VID_HTOTAL 0x108 129 #define VID_HSRE 0x10c /* hsync raising edge */ 130 #define VID_HBRE 0x110 /* hblank raising edge */ 131 #define VID_HBFE 0x114 /* hblank falling edge */ 132 #define VID_HCNTPRLD 0x118 /* hcounter preload */ 133 #define VID_VCOUNTER 0x11c /* vcounter */ 134 #define VID_VLENGTH 0x120 /* lines, including blanks */ 135 #define VID_VSRE 0x124 /* vsync raising edge */ 136 #define VID_VBRE 0x128 /* vblank raising edge */ 137 #define VID_VBFE 0x12c /* vblank falling edge */ 138 #define VID_VCNTPRLD 0x130 /* vcounter preload */ 139 #define VID_SRADDR 0x134 /* screen repaint address */ 140 #define VID_SRTC 0x138 /* screen repaint timing control */ 141 #define VID_QSFCNTR 0x13c /* QSF counter */ 142 143 #define VID_MEM_CONFIG 0x184 /* memory config */ 144 #define VID_RFPERIOD 0x188 /* refresh period */ 145 #define VID_RFCOUNT 0x18c /* refresh counter */ 146 #define VID_RLMAX 0x190 /* RAS low max */ 147 #define VID_RLCUR 0x194 /* RAS low current */ 148 #define VID_DACSYNC 0x198 /* read after last DAC access */ 149 150 #define ENGINE_STATUS 0x2000 /* drawing engine status register */ 151 #define BLITTER_BUSY 0x80000000 152 #define ENGINE_BUSY 0x40000000 153 #define COMMAND_BLIT 0x2004 154 #define COMMAND_QUAD 0x2008 155 #define COMMAND_PIXEL8 0x200c 156 /* pixel data for monochrome colour expansion */ 157 #define PIXEL_1 0x2080 158 /* apparently bits 2-6 control how many pixels we write - n+1 */ 159 160 /* drawing engine registers */ 161 #define COORD_INDEX 0x218c 162 #define WINDOW_OFFSET 0x2190 163 164 #define FOREGROUND_COLOR 0x2200 165 #define BACKGROUND_COLOR 0x2204 166 #define PLANE_MASK 0x2208 167 #define DRAW_MODE 0x220c 168 #define PATTERN_ORIGIN_X 0x2210 169 #define PATTERN_ORIGIN_Y 0x2214 170 #define RASTER_OP 0x2218 171 #define ROP_NO_SOLID 0x02000 /* if set use pattern instead of color for quad operations */ 172 #define ROP_2BIT_PATTERN 0x04000 /* 4-colour pattern instead of mono */ 173 #define ROP_PIX1_TRANS 0x08000 /* transparent background in mono */ 174 #define ROP_OVERSIZE 0x10000 175 #define ROP_PATTERN 0x20000 /* the manual says pattern enable */ 176 #define ROP_TRANS 0x20000 /* but XFree86 says trans */ 177 #define ROP_SRC 0xCC 178 #define ROP_PAT 0xF0 179 #define ROP_DST 0xAA 180 #define ROP_SET 0xff 181 182 #define PIXEL_8 0x221c 183 #define WINDOW_MIN 0x2220 184 #define WINDOW_MAX 0x2224 185 186 #define PATTERN0 0x2280 187 #define PATTERN1 0x2284 188 #define PATTERN2 0x2288 189 #define PATTERN3 0x228c 190 #define USER0 0x2290 191 #define USER1 0x2294 192 #define USER2 0x2298 193 #define USER3 0x229c 194 #define BYTE_CLIP_MIN 0x22a0 195 #define BYTE_CLIP_MAX 0x22a4 196 197 /* coordinate registers */ 198 #define ABS_X0 0x3008 199 #define ABS_Y0 0x3010 200 #define ABS_XY0 0x3018 201 #define REL_X0 0x3028 202 #define REL_Y0 0x3030 203 #define REL_XY0 0x3038 204 205 #define ABS_X1 0x3048 206 #define ABS_Y1 0x3050 207 #define ABS_XY1 0x3058 208 #define REL_X1 0x3068 209 #define REL_Y1 0x3070 210 #define REL_XY1 0x3078 211 212 #define ABS_X2 0x3088 213 #define ABS_Y2 0x3090 214 #define ABS_XY2 0x3098 215 #define REL_X2 0x30a8 216 #define REL_Y2 0x30b0 217 #define REL_XY2 0x30b8 218 219 #define ABS_X3 0x30c8 220 #define ABS_Y3 0x30d0 221 #define ABS_XY3 0x30d8 222 #define REL_X3 0x30e8 223 #define REL_Y3 0x30f0 224 #define REL_XY3 0x30f8 225 226 /* meta-coordinates */ 227 #define POINT_RTW_X 0x3208 228 #define POINT_RTW_Y 0x3210 229 #define POINT_RTW_XY 0x3218 230 #define POINT_RTP_X 0x3228 231 #define POINT_RTP_Y 0x3220 232 #define POINT_RTP_XY 0x3238 233 234 #define LINE_RTW_X 0x3248 235 #define LINE_RTW_Y 0x3250 236 #define LINE_RTW_XY 0x3258 237 #define LINE_RTP_X 0x3268 238 #define LINE_RTP_Y 0x3260 239 #define LINE_RTP_XY 0x3278 240 241 #define TRIANGLE_RTW_X 0x3288 242 #define TRIANGLE_RTW_Y 0x3290 243 #define TRIANGLE_RTW_XY 0x3298 244 #define TRIANGLE_RTP_X 0x32a8 245 #define TRIANGLE_RTP_Y 0x32a0 246 #define TRIANGLE_RTP_XY 0x32b8 247 248 #define QUAD_RTW_X 0x32c8 249 #define QUAD_RTW_Y 0x32d0 250 #define QUAD_RTW_XY 0x32d8 251 #define QUAD_RTP_X 0x32e8 252 #define QUAD_RTP_Y 0x32e0 253 #define QUAD_RTP_XY 0x32f8 254 255 #define RECT_RTW_X 0x3308 256 #define RECT_RTW_Y 0x3310 257 #define RECT_RTW_XY 0x3318 258 #define RECT_RTP_X 0x3328 259 #define RECT_RTP_Y 0x3320 260 #define RECT_RTP_XY 0x3338 261 262 #endif 263
Indexes created Sun Sep 21 20:09:37 GMT 2025