1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone helper functions and enum definitions for 10 // the X86 target useful for the compiler back-end and the MC libraries. 11 // As such, it deliberately does not include references to LLVM core 12 // code gen types, passes, etc.. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 17 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 18 19 #include "X86MCTargetDesc.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/Support/DataTypes.h" 22 #include "llvm/Support/ErrorHandling.h" 23 24 namespace llvm { 25 26 namespace X86 { 27 // Enums for memory operand decoding. Each memory operand is represented with 28 // a 5 operand sequence in the form: 29 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 30 // These enums help decode this. 31 enum { 32 AddrBaseReg = 0, 33 AddrScaleAmt = 1, 34 AddrIndexReg = 2, 35 AddrDisp = 3, 36 37 /// AddrSegmentReg - The operand # of the segment in the memory operand. 38 AddrSegmentReg = 4, 39 40 /// AddrNumOperands - Total number of operands in a memory reference. 41 AddrNumOperands = 5 42 }; 43 44 /// AVX512 static rounding constants. These need to match the values in 45 /// avx512fintrin.h. 46 enum STATIC_ROUNDING { 47 TO_NEAREST_INT = 0, 48 TO_NEG_INF = 1, 49 TO_POS_INF = 2, 50 TO_ZERO = 3, 51 CUR_DIRECTION = 4, 52 NO_EXC = 8 53 }; 54 55 /// The constants to describe instr prefixes if there are 56 enum IPREFIXES { 57 IP_NO_PREFIX = 0, 58 IP_HAS_OP_SIZE = 1U << 0, 59 IP_HAS_AD_SIZE = 1U << 1, 60 IP_HAS_REPEAT_NE = 1U << 2, 61 IP_HAS_REPEAT = 1U << 3, 62 IP_HAS_LOCK = 1U << 4, 63 IP_HAS_NOTRACK = 1U << 5, 64 IP_USE_VEX = 1U << 6, 65 IP_USE_VEX2 = 1U << 7, 66 IP_USE_VEX3 = 1U << 8, 67 IP_USE_EVEX = 1U << 9, 68 IP_USE_DISP8 = 1U << 10, 69 IP_USE_DISP32 = 1U << 11, 70 }; 71 72 enum OperandType : unsigned { 73 /// AVX512 embedded rounding control. This should only have values 0-3. 74 OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET, 75 OPERAND_COND_CODE, 76 }; 77 78 // X86 specific condition code. These correspond to X86_*_COND in 79 // X86InstrInfo.td. They must be kept in synch. 80 enum CondCode { 81 COND_O = 0, 82 COND_NO = 1, 83 COND_B = 2, 84 COND_AE = 3, 85 COND_E = 4, 86 COND_NE = 5, 87 COND_BE = 6, 88 COND_A = 7, 89 COND_S = 8, 90 COND_NS = 9, 91 COND_P = 10, 92 COND_NP = 11, 93 COND_L = 12, 94 COND_GE = 13, 95 COND_LE = 14, 96 COND_G = 15, 97 LAST_VALID_COND = COND_G, 98 99 // Artificial condition codes. These are used by analyzeBranch 100 // to indicate a block terminated with two conditional branches that together 101 // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE, 102 // which can't be represented on x86 with a single condition. These 103 // are never used in MachineInstrs and are inverses of one another. 104 COND_NE_OR_P, 105 COND_E_AND_NP, 106 107 COND_INVALID 108 }; 109 110 // The classification for the first instruction in macro fusion. 111 enum class FirstMacroFusionInstKind { 112 // TEST 113 Test, 114 // CMP 115 Cmp, 116 // AND 117 And, 118 // FIXME: Zen 3 support branch fusion for OR/XOR. 119 // ADD, SUB 120 AddSub, 121 // INC, DEC 122 IncDec, 123 // Not valid as a first macro fusion instruction 124 Invalid 125 }; 126 127 enum class SecondMacroFusionInstKind { 128 // JA, JB and variants. 129 AB, 130 // JE, JL, JG and variants. 131 ELG, 132 // JS, JP, JO and variants 133 SPO, 134 // Not a fusible jump. 135 Invalid, 136 }; 137 138 /// \returns the type of the first instruction in macro-fusion. 139 inline FirstMacroFusionInstKind 140 classifyFirstOpcodeInMacroFusion(unsigned Opcode) { 141 switch (Opcode) { 142 default: 143 return FirstMacroFusionInstKind::Invalid; 144 // TEST 145 case X86::TEST16i16: 146 case X86::TEST16mr: 147 case X86::TEST16ri: 148 case X86::TEST16rr: 149 case X86::TEST32i32: 150 case X86::TEST32mr: 151 case X86::TEST32ri: 152 case X86::TEST32rr: 153 case X86::TEST64i32: 154 case X86::TEST64mr: 155 case X86::TEST64ri32: 156 case X86::TEST64rr: 157 case X86::TEST8i8: 158 case X86::TEST8mr: 159 case X86::TEST8ri: 160 case X86::TEST8rr: 161 return FirstMacroFusionInstKind::Test; 162 case X86::AND16i16: 163 case X86::AND16ri: 164 case X86::AND16ri8: 165 case X86::AND16rm: 166 case X86::AND16rr: 167 case X86::AND16rr_REV: 168 case X86::AND32i32: 169 case X86::AND32ri: 170 case X86::AND32ri8: 171 case X86::AND32rm: 172 case X86::AND32rr: 173 case X86::AND32rr_REV: 174 case X86::AND64i32: 175 case X86::AND64ri32: 176 case X86::AND64ri8: 177 case X86::AND64rm: 178 case X86::AND64rr: 179 case X86::AND64rr_REV: 180 case X86::AND8i8: 181 case X86::AND8ri: 182 case X86::AND8ri8: 183 case X86::AND8rm: 184 case X86::AND8rr: 185 case X86::AND8rr_REV: 186 return FirstMacroFusionInstKind::And; 187 // FIXME: Zen 3 support branch fusion for OR/XOR. 188 // CMP 189 case X86::CMP16i16: 190 case X86::CMP16mr: 191 case X86::CMP16ri: 192 case X86::CMP16ri8: 193 case X86::CMP16rm: 194 case X86::CMP16rr: 195 case X86::CMP16rr_REV: 196 case X86::CMP32i32: 197 case X86::CMP32mr: 198 case X86::CMP32ri: 199 case X86::CMP32ri8: 200 case X86::CMP32rm: 201 case X86::CMP32rr: 202 case X86::CMP32rr_REV: 203 case X86::CMP64i32: 204 case X86::CMP64mr: 205 case X86::CMP64ri32: 206 case X86::CMP64ri8: 207 case X86::CMP64rm: 208 case X86::CMP64rr: 209 case X86::CMP64rr_REV: 210 case X86::CMP8i8: 211 case X86::CMP8mr: 212 case X86::CMP8ri: 213 case X86::CMP8ri8: 214 case X86::CMP8rm: 215 case X86::CMP8rr: 216 case X86::CMP8rr_REV: 217 return FirstMacroFusionInstKind::Cmp; 218 // ADD 219 case X86::ADD16i16: 220 case X86::ADD16ri: 221 case X86::ADD16ri8: 222 case X86::ADD16rm: 223 case X86::ADD16rr: 224 case X86::ADD16rr_REV: 225 case X86::ADD32i32: 226 case X86::ADD32ri: 227 case X86::ADD32ri8: 228 case X86::ADD32rm: 229 case X86::ADD32rr: 230 case X86::ADD32rr_REV: 231 case X86::ADD64i32: 232 case X86::ADD64ri32: 233 case X86::ADD64ri8: 234 case X86::ADD64rm: 235 case X86::ADD64rr: 236 case X86::ADD64rr_REV: 237 case X86::ADD8i8: 238 case X86::ADD8ri: 239 case X86::ADD8ri8: 240 case X86::ADD8rm: 241 case X86::ADD8rr: 242 case X86::ADD8rr_REV: 243 // SUB 244 case X86::SUB16i16: 245 case X86::SUB16ri: 246 case X86::SUB16ri8: 247 case X86::SUB16rm: 248 case X86::SUB16rr: 249 case X86::SUB16rr_REV: 250 case X86::SUB32i32: 251 case X86::SUB32ri: 252 case X86::SUB32ri8: 253 case X86::SUB32rm: 254 case X86::SUB32rr: 255 case X86::SUB32rr_REV: 256 case X86::SUB64i32: 257 case X86::SUB64ri32: 258 case X86::SUB64ri8: 259 case X86::SUB64rm: 260 case X86::SUB64rr: 261 case X86::SUB64rr_REV: 262 case X86::SUB8i8: 263 case X86::SUB8ri: 264 case X86::SUB8ri8: 265 case X86::SUB8rm: 266 case X86::SUB8rr: 267 case X86::SUB8rr_REV: 268 return FirstMacroFusionInstKind::AddSub; 269 // INC 270 case X86::INC16r: 271 case X86::INC16r_alt: 272 case X86::INC32r: 273 case X86::INC32r_alt: 274 case X86::INC64r: 275 case X86::INC8r: 276 // DEC 277 case X86::DEC16r: 278 case X86::DEC16r_alt: 279 case X86::DEC32r: 280 case X86::DEC32r_alt: 281 case X86::DEC64r: 282 case X86::DEC8r: 283 return FirstMacroFusionInstKind::IncDec; 284 } 285 } 286 287 /// \returns the type of the second instruction in macro-fusion. 288 inline SecondMacroFusionInstKind 289 classifySecondCondCodeInMacroFusion(X86::CondCode CC) { 290 if (CC == X86::COND_INVALID) 291 return SecondMacroFusionInstKind::Invalid; 292 293 switch (CC) { 294 default: 295 return SecondMacroFusionInstKind::Invalid; 296 // JE,JZ 297 case X86::COND_E: 298 // JNE,JNZ 299 case X86::COND_NE: 300 // JL,JNGE 301 case X86::COND_L: 302 // JLE,JNG 303 case X86::COND_LE: 304 // JG,JNLE 305 case X86::COND_G: 306 // JGE,JNL 307 case X86::COND_GE: 308 return SecondMacroFusionInstKind::ELG; 309 // JB,JC 310 case X86::COND_B: 311 // JNA,JBE 312 case X86::COND_BE: 313 // JA,JNBE 314 case X86::COND_A: 315 // JAE,JNC,JNB 316 case X86::COND_AE: 317 return SecondMacroFusionInstKind::AB; 318 // JS 319 case X86::COND_S: 320 // JNS 321 case X86::COND_NS: 322 // JP,JPE 323 case X86::COND_P: 324 // JNP,JPO 325 case X86::COND_NP: 326 // JO 327 case X86::COND_O: 328 // JNO 329 case X86::COND_NO: 330 return SecondMacroFusionInstKind::SPO; 331 } 332 } 333 334 /// \param FirstKind kind of the first instruction in macro fusion. 335 /// \param SecondKind kind of the second instruction in macro fusion. 336 /// 337 /// \returns true if the two instruction can be macro fused. 338 inline bool isMacroFused(FirstMacroFusionInstKind FirstKind, 339 SecondMacroFusionInstKind SecondKind) { 340 switch (FirstKind) { 341 case X86::FirstMacroFusionInstKind::Test: 342 case X86::FirstMacroFusionInstKind::And: 343 return true; 344 case X86::FirstMacroFusionInstKind::Cmp: 345 case X86::FirstMacroFusionInstKind::AddSub: 346 return SecondKind == X86::SecondMacroFusionInstKind::AB || 347 SecondKind == X86::SecondMacroFusionInstKind::ELG; 348 case X86::FirstMacroFusionInstKind::IncDec: 349 return SecondKind == X86::SecondMacroFusionInstKind::ELG; 350 case X86::FirstMacroFusionInstKind::Invalid: 351 return false; 352 } 353 llvm_unreachable("unknown fusion type"); 354 } 355 356 /// Defines the possible values of the branch boundary alignment mask. 357 enum AlignBranchBoundaryKind : uint8_t { 358 AlignBranchNone = 0, 359 AlignBranchFused = 1U << 0, 360 AlignBranchJcc = 1U << 1, 361 AlignBranchJmp = 1U << 2, 362 AlignBranchCall = 1U << 3, 363 AlignBranchRet = 1U << 4, 364 AlignBranchIndirect = 1U << 5 365 }; 366 367 /// Defines the encoding values for segment override prefix. 368 enum EncodingOfSegmentOverridePrefix : uint8_t { 369 CS_Encoding = 0x2E, 370 DS_Encoding = 0x3E, 371 ES_Encoding = 0x26, 372 FS_Encoding = 0x64, 373 GS_Encoding = 0x65, 374 SS_Encoding = 0x36 375 }; 376 377 /// Given a segment register, return the encoding of the segment override 378 /// prefix for it. 379 inline EncodingOfSegmentOverridePrefix 380 getSegmentOverridePrefixForReg(unsigned Reg) { 381 switch (Reg) { 382 default: 383 llvm_unreachable("Unknown segment register!"); 384 case X86::CS: 385 return CS_Encoding; 386 case X86::DS: 387 return DS_Encoding; 388 case X86::ES: 389 return ES_Encoding; 390 case X86::FS: 391 return FS_Encoding; 392 case X86::GS: 393 return GS_Encoding; 394 case X86::SS: 395 return SS_Encoding; 396 } 397 } 398 399 } // end namespace X86; 400 401 /// X86II - This namespace holds all of the target specific flags that 402 /// instruction info tracks. 403 /// 404 namespace X86II { 405 /// Target Operand Flag enum. 406 enum TOF { 407 //===------------------------------------------------------------------===// 408 // X86 Specific MachineOperand flags. 409 410 MO_NO_FLAG, 411 412 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 413 /// relocation of: 414 /// SYMBOL_LABEL + [. - PICBASELABEL] 415 MO_GOT_ABSOLUTE_ADDRESS, 416 417 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 418 /// immediate should get the value of the symbol minus the PIC base label: 419 /// SYMBOL_LABEL - PICBASELABEL 420 MO_PIC_BASE_OFFSET, 421 422 /// MO_GOT - On a symbol operand this indicates that the immediate is the 423 /// offset to the GOT entry for the symbol name from the base of the GOT. 424 /// 425 /// See the X86-64 ELF ABI supplement for more details. 426 /// SYMBOL_LABEL @GOT 427 MO_GOT, 428 429 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 430 /// the offset to the location of the symbol name from the base of the GOT. 431 /// 432 /// See the X86-64 ELF ABI supplement for more details. 433 /// SYMBOL_LABEL @GOTOFF 434 MO_GOTOFF, 435 436 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 437 /// offset to the GOT entry for the symbol name from the current code 438 /// location. 439 /// 440 /// See the X86-64 ELF ABI supplement for more details. 441 /// SYMBOL_LABEL @GOTPCREL 442 MO_GOTPCREL, 443 444 /// MO_PLT - On a symbol operand this indicates that the immediate is 445 /// offset to the PLT entry of symbol name from the current code location. 446 /// 447 /// See the X86-64 ELF ABI supplement for more details. 448 /// SYMBOL_LABEL @PLT 449 MO_PLT, 450 451 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 452 /// the offset of the GOT entry with the TLS index structure that contains 453 /// the module number and variable offset for the symbol. Used in the 454 /// general dynamic TLS access model. 455 /// 456 /// See 'ELF Handling for Thread-Local Storage' for more details. 457 /// SYMBOL_LABEL @TLSGD 458 MO_TLSGD, 459 460 /// MO_TLSLD - On a symbol operand this indicates that the immediate is 461 /// the offset of the GOT entry with the TLS index for the module that 462 /// contains the symbol. When this index is passed to a call to 463 /// __tls_get_addr, the function will return the base address of the TLS 464 /// block for the symbol. Used in the x86-64 local dynamic TLS access model. 465 /// 466 /// See 'ELF Handling for Thread-Local Storage' for more details. 467 /// SYMBOL_LABEL @TLSLD 468 MO_TLSLD, 469 470 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is 471 /// the offset of the GOT entry with the TLS index for the module that 472 /// contains the symbol. When this index is passed to a call to 473 /// ___tls_get_addr, the function will return the base address of the TLS 474 /// block for the symbol. Used in the IA32 local dynamic TLS access model. 475 /// 476 /// See 'ELF Handling for Thread-Local Storage' for more details. 477 /// SYMBOL_LABEL @TLSLDM 478 MO_TLSLDM, 479 480 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 481 /// the offset of the GOT entry with the thread-pointer offset for the 482 /// symbol. Used in the x86-64 initial exec TLS access model. 483 /// 484 /// See 'ELF Handling for Thread-Local Storage' for more details. 485 /// SYMBOL_LABEL @GOTTPOFF 486 MO_GOTTPOFF, 487 488 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 489 /// the absolute address of the GOT entry with the negative thread-pointer 490 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access 491 /// model. 492 /// 493 /// See 'ELF Handling for Thread-Local Storage' for more details. 494 /// SYMBOL_LABEL @INDNTPOFF 495 MO_INDNTPOFF, 496 497 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 498 /// the thread-pointer offset for the symbol. Used in the x86-64 local 499 /// exec TLS access model. 500 /// 501 /// See 'ELF Handling for Thread-Local Storage' for more details. 502 /// SYMBOL_LABEL @TPOFF 503 MO_TPOFF, 504 505 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is 506 /// the offset of the GOT entry with the TLS offset of the symbol. Used 507 /// in the local dynamic TLS access model. 508 /// 509 /// See 'ELF Handling for Thread-Local Storage' for more details. 510 /// SYMBOL_LABEL @DTPOFF 511 MO_DTPOFF, 512 513 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 514 /// the negative thread-pointer offset for the symbol. Used in the IA32 515 /// local exec TLS access model. 516 /// 517 /// See 'ELF Handling for Thread-Local Storage' for more details. 518 /// SYMBOL_LABEL @NTPOFF 519 MO_NTPOFF, 520 521 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is 522 /// the offset of the GOT entry with the negative thread-pointer offset for 523 /// the symbol. Used in the PIC IA32 initial exec TLS access model. 524 /// 525 /// See 'ELF Handling for Thread-Local Storage' for more details. 526 /// SYMBOL_LABEL @GOTNTPOFF 527 MO_GOTNTPOFF, 528 529 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 530 /// reference is actually to the "__imp_FOO" symbol. This is used for 531 /// dllimport linkage on windows. 532 MO_DLLIMPORT, 533 534 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 535 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 536 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 537 MO_DARWIN_NONLAZY, 538 539 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 540 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 541 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 542 MO_DARWIN_NONLAZY_PIC_BASE, 543 544 /// MO_TLVP - On a symbol operand this indicates that the immediate is 545 /// some TLS offset. 546 /// 547 /// This is the TLS offset for the Darwin TLS mechanism. 548 MO_TLVP, 549 550 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 551 /// is some TLS offset from the picbase. 552 /// 553 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 554 MO_TLVP_PIC_BASE, 555 556 /// MO_SECREL - On a symbol operand this indicates that the immediate is 557 /// the offset from beginning of section. 558 /// 559 /// This is the TLS offset for the COFF/Windows TLS mechanism. 560 MO_SECREL, 561 562 /// MO_ABS8 - On a symbol operand this indicates that the symbol is known 563 /// to be an absolute symbol in range [0,128), so we can use the @ABS8 564 /// symbol modifier. 565 MO_ABS8, 566 567 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the 568 /// reference is actually to the ".refptr.FOO" symbol. This is used for 569 /// stub symbols on windows. 570 MO_COFFSTUB, 571 }; 572 573 enum : uint64_t { 574 //===------------------------------------------------------------------===// 575 // Instruction encodings. These are the standard/most common forms for X86 576 // instructions. 577 // 578 579 // PseudoFrm - This represents an instruction that is a pseudo instruction 580 // or one that has not been implemented yet. It is illegal to code generate 581 // it, but tolerated for intermediate implementation stages. 582 Pseudo = 0, 583 584 /// Raw - This form is for instructions that don't have any operands, so 585 /// they are just a fixed opcode value, like 'leave'. 586 RawFrm = 1, 587 588 /// AddRegFrm - This form is used for instructions like 'push r32' that have 589 /// their one register operand added to their opcode. 590 AddRegFrm = 2, 591 592 /// RawFrmMemOffs - This form is for instructions that store an absolute 593 /// memory offset as an immediate with a possible segment override. 594 RawFrmMemOffs = 3, 595 596 /// RawFrmSrc - This form is for instructions that use the source index 597 /// register SI/ESI/RSI with a possible segment override. 598 RawFrmSrc = 4, 599 600 /// RawFrmDst - This form is for instructions that use the destination index 601 /// register DI/EDI/RDI. 602 RawFrmDst = 5, 603 604 /// RawFrmDstSrc - This form is for instructions that use the source index 605 /// register SI/ESI/RSI with a possible segment override, and also the 606 /// destination index register DI/EDI/RDI. 607 RawFrmDstSrc = 6, 608 609 /// RawFrmImm8 - This is used for the ENTER instruction, which has two 610 /// immediates, the first of which is a 16-bit immediate (specified by 611 /// the imm encoding) and the second is a 8-bit fixed value. 612 RawFrmImm8 = 7, 613 614 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 615 /// immediates, the first of which is a 16 or 32-bit immediate (specified by 616 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 617 /// manual, this operand is described as pntr16:32 and pntr16:16 618 RawFrmImm16 = 8, 619 620 /// AddCCFrm - This form is used for Jcc that encode the condition code 621 /// in the lower 4 bits of the opcode. 622 AddCCFrm = 9, 623 624 /// PrefixByte - This form is used for instructions that represent a prefix 625 /// byte like data16 or rep. 626 PrefixByte = 10, 627 628 /// MRM[0-7][rm] - These forms are used to represent instructions that use 629 /// a Mod/RM byte, and use the middle field to hold extended opcode 630 /// information. In the intel manual these are represented as /0, /1, ... 631 /// 632 633 // Instructions operate on a register Reg/Opcode operand not the r/m field. 634 MRMr0 = 21, 635 636 /// MRMSrcMem - But force to use the SIB field. 637 MRMSrcMemFSIB = 22, 638 639 /// MRMDestMem - But force to use the SIB field. 640 MRMDestMemFSIB = 23, 641 642 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 643 /// to specify a destination, which in this case is memory. 644 /// 645 MRMDestMem = 24, 646 647 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 648 /// to specify a source, which in this case is memory. 649 /// 650 MRMSrcMem = 25, 651 652 /// MRMSrcMem4VOp3 - This form is used for instructions that encode 653 /// operand 3 with VEX.VVVV and load from memory. 654 /// 655 MRMSrcMem4VOp3 = 26, 656 657 /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM 658 /// byte to specify the fourth source, which in this case is memory. 659 /// 660 MRMSrcMemOp4 = 27, 661 662 /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM 663 /// byte to specify the operands and also encodes a condition code. 664 /// 665 MRMSrcMemCC = 28, 666 667 /// MRMXm - This form is used for instructions that use the Mod/RM byte 668 /// to specify a memory source, but doesn't use the middle field. And has 669 /// a condition code. 670 /// 671 MRMXmCC = 30, 672 673 /// MRMXm - This form is used for instructions that use the Mod/RM byte 674 /// to specify a memory source, but doesn't use the middle field. 675 /// 676 MRMXm = 31, 677 678 // Next, instructions that operate on a memory r/m operand... 679 MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35, // Format /0 /1 /2 /3 680 MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39, // Format /4 /5 /6 /7 681 682 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 683 /// to specify a destination, which in this case is a register. 684 /// 685 MRMDestReg = 40, 686 687 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 688 /// to specify a source, which in this case is a register. 689 /// 690 MRMSrcReg = 41, 691 692 /// MRMSrcReg4VOp3 - This form is used for instructions that encode 693 /// operand 3 with VEX.VVVV and do not load from memory. 694 /// 695 MRMSrcReg4VOp3 = 42, 696 697 /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM 698 /// byte to specify the fourth source, which in this case is a register. 699 /// 700 MRMSrcRegOp4 = 43, 701 702 /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM 703 /// byte to specify the operands and also encodes a condition code 704 /// 705 MRMSrcRegCC = 44, 706 707 /// MRMXCCr - This form is used for instructions that use the Mod/RM byte 708 /// to specify a register source, but doesn't use the middle field. And has 709 /// a condition code. 710 /// 711 MRMXrCC = 46, 712 713 /// MRMXr - This form is used for instructions that use the Mod/RM byte 714 /// to specify a register source, but doesn't use the middle field. 715 /// 716 MRMXr = 47, 717 718 // Instructions that operate on a register r/m operand... 719 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, // Format /0 /1 /2 /3 720 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, // Format /4 /5 /6 /7 721 722 // Instructions that operate that have mod=11 and an opcode but ignore r/m. 723 MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59, // Format /0 /1 /2 /3 724 MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63, // Format /4 /5 /6 /7 725 726 /// MRM_XX - A mod/rm byte of exactly 0xXX. 727 MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67, 728 MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71, 729 MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75, 730 MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79, 731 MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83, 732 MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87, 733 MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91, 734 MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95, 735 MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99, 736 MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103, 737 MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107, 738 MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111, 739 MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115, 740 MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119, 741 MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123, 742 MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127, 743 744 FormMask = 127, 745 746 //===------------------------------------------------------------------===// 747 // Actual flags... 748 749 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix. 750 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in 751 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66 752 // prefix in 16-bit mode. 753 OpSizeShift = 7, 754 OpSizeMask = 0x3 << OpSizeShift, 755 756 OpSizeFixed = 0 << OpSizeShift, 757 OpSize16 = 1 << OpSizeShift, 758 OpSize32 = 2 << OpSizeShift, 759 760 // AsSize - AdSizeX implies this instruction determines its need of 0x67 761 // prefix from a normal ModRM memory operand. The other types indicate that 762 // an operand is encoded with a specific width and a prefix is needed if 763 // it differs from the current mode. 764 AdSizeShift = OpSizeShift + 2, 765 AdSizeMask = 0x3 << AdSizeShift, 766 767 AdSizeX = 0 << AdSizeShift, 768 AdSize16 = 1 << AdSizeShift, 769 AdSize32 = 2 << AdSizeShift, 770 AdSize64 = 3 << AdSizeShift, 771 772 //===------------------------------------------------------------------===// 773 // OpPrefix - There are several prefix bytes that are used as opcode 774 // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is 775 // no prefix. 776 // 777 OpPrefixShift = AdSizeShift + 2, 778 OpPrefixMask = 0x3 << OpPrefixShift, 779 780 // PD - Prefix code for packed double precision vector floating point 781 // operations performed in the SSE registers. 782 PD = 1 << OpPrefixShift, 783 784 // XS, XD - These prefix codes are for single and double precision scalar 785 // floating point operations performed in the SSE registers. 786 XS = 2 << OpPrefixShift, XD = 3 << OpPrefixShift, 787 788 //===------------------------------------------------------------------===// 789 // OpMap - This field determines which opcode map this instruction 790 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc. 791 // 792 OpMapShift = OpPrefixShift + 2, 793 OpMapMask = 0x7 << OpMapShift, 794 795 // OB - OneByte - Set if this instruction has a one byte opcode. 796 OB = 0 << OpMapShift, 797 798 // TB - TwoByte - Set if this instruction has a two byte opcode, which 799 // starts with a 0x0F byte before the real opcode. 800 TB = 1 << OpMapShift, 801 802 // T8, TA - Prefix after the 0x0F prefix. 803 T8 = 2 << OpMapShift, TA = 3 << OpMapShift, 804 805 // XOP8 - Prefix to include use of imm byte. 806 XOP8 = 4 << OpMapShift, 807 808 // XOP9 - Prefix to exclude use of imm byte. 809 XOP9 = 5 << OpMapShift, 810 811 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. 812 XOPA = 6 << OpMapShift, 813 814 /// ThreeDNow - This indicates that the instruction uses the 815 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 816 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 817 /// storing a classifier in the imm8 field. To simplify our implementation, 818 /// we handle this by storeing the classifier in the opcode field and using 819 /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 820 ThreeDNow = 7 << OpMapShift, 821 822 //===------------------------------------------------------------------===// 823 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 824 // They are used to specify GPRs and SSE registers, 64-bit operand size, 825 // etc. We only cares about REX.W and REX.R bits and only the former is 826 // statically determined. 827 // 828 REXShift = OpMapShift + 3, 829 REX_W = 1 << REXShift, 830 831 //===------------------------------------------------------------------===// 832 // This three-bit field describes the size of an immediate operand. Zero is 833 // unused so that we can tell if we forgot to set a value. 834 ImmShift = REXShift + 1, 835 ImmMask = 15 << ImmShift, 836 Imm8 = 1 << ImmShift, 837 Imm8PCRel = 2 << ImmShift, 838 Imm8Reg = 3 << ImmShift, 839 Imm16 = 4 << ImmShift, 840 Imm16PCRel = 5 << ImmShift, 841 Imm32 = 6 << ImmShift, 842 Imm32PCRel = 7 << ImmShift, 843 Imm32S = 8 << ImmShift, 844 Imm64 = 9 << ImmShift, 845 846 //===------------------------------------------------------------------===// 847 // FP Instruction Classification... Zero is non-fp instruction. 848 849 // FPTypeMask - Mask for all of the FP types... 850 FPTypeShift = ImmShift + 4, 851 FPTypeMask = 7 << FPTypeShift, 852 853 // NotFP - The default, set for instructions that do not use FP registers. 854 NotFP = 0 << FPTypeShift, 855 856 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 857 ZeroArgFP = 1 << FPTypeShift, 858 859 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 860 OneArgFP = 2 << FPTypeShift, 861 862 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 863 // result back to ST(0). For example, fcos, fsqrt, etc. 864 // 865 OneArgFPRW = 3 << FPTypeShift, 866 867 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 868 // explicit argument, storing the result to either ST(0) or the implicit 869 // argument. For example: fadd, fsub, fmul, etc... 870 TwoArgFP = 4 << FPTypeShift, 871 872 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 873 // explicit argument, but have no destination. Example: fucom, fucomi, ... 874 CompareFP = 5 << FPTypeShift, 875 876 // CondMovFP - "2 operand" floating point conditional move instructions. 877 CondMovFP = 6 << FPTypeShift, 878 879 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 880 SpecialFP = 7 << FPTypeShift, 881 882 // Lock prefix 883 LOCKShift = FPTypeShift + 3, 884 LOCK = 1 << LOCKShift, 885 886 // REP prefix 887 REPShift = LOCKShift + 1, 888 REP = 1 << REPShift, 889 890 // Execution domain for SSE instructions. 891 // 0 means normal, non-SSE instruction. 892 SSEDomainShift = REPShift + 1, 893 894 // Encoding 895 EncodingShift = SSEDomainShift + 2, 896 EncodingMask = 0x3 << EncodingShift, 897 898 // VEX - encoding using 0xC4/0xC5 899 VEX = 1 << EncodingShift, 900 901 /// XOP - Opcode prefix used by XOP instructions. 902 XOP = 2 << EncodingShift, 903 904 // VEX_EVEX - Specifies that this instruction use EVEX form which provides 905 // syntax support up to 32 512-bit register operands and up to 7 16-bit 906 // mask operands as well as source operand data swizzling/memory operand 907 // conversion, eviction hint, and rounding mode. 908 EVEX = 3 << EncodingShift, 909 910 // Opcode 911 OpcodeShift = EncodingShift + 2, 912 913 /// VEX_W - Has a opcode specific functionality, but is used in the same 914 /// way as REX_W is for regular SSE instructions. 915 VEX_WShift = OpcodeShift + 8, 916 VEX_W = 1ULL << VEX_WShift, 917 918 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 919 /// address instructions in SSE are represented as 3 address ones in AVX 920 /// and the additional register is encoded in VEX_VVVV prefix. 921 VEX_4VShift = VEX_WShift + 1, 922 VEX_4V = 1ULL << VEX_4VShift, 923 924 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 925 /// instruction uses 256-bit wide registers. This is usually auto detected 926 /// if a VR256 register is used, but some AVX instructions also have this 927 /// field marked when using a f256 memory references. 928 VEX_LShift = VEX_4VShift + 1, 929 VEX_L = 1ULL << VEX_LShift, 930 931 // EVEX_K - Set if this instruction requires masking 932 EVEX_KShift = VEX_LShift + 1, 933 EVEX_K = 1ULL << EVEX_KShift, 934 935 // EVEX_Z - Set if this instruction has EVEX.Z field set. 936 EVEX_ZShift = EVEX_KShift + 1, 937 EVEX_Z = 1ULL << EVEX_ZShift, 938 939 // EVEX_L2 - Set if this instruction has EVEX.L' field set. 940 EVEX_L2Shift = EVEX_ZShift + 1, 941 EVEX_L2 = 1ULL << EVEX_L2Shift, 942 943 // EVEX_B - Set if this instruction has EVEX.B field set. 944 EVEX_BShift = EVEX_L2Shift + 1, 945 EVEX_B = 1ULL << EVEX_BShift, 946 947 // The scaling factor for the AVX512's 8-bit compressed displacement. 948 CD8_Scale_Shift = EVEX_BShift + 1, 949 CD8_Scale_Mask = 127ULL << CD8_Scale_Shift, 950 951 /// Explicitly specified rounding control 952 EVEX_RCShift = CD8_Scale_Shift + 7, 953 EVEX_RC = 1ULL << EVEX_RCShift, 954 955 // NOTRACK prefix 956 NoTrackShift = EVEX_RCShift + 1, 957 NOTRACK = 1ULL << NoTrackShift, 958 959 // Force VEX encoding 960 ExplicitVEXShift = NoTrackShift + 1, 961 ExplicitVEXPrefix = 1ULL << ExplicitVEXShift 962 }; 963 964 /// \returns true if the instruction with given opcode is a prefix. 965 inline bool isPrefix(uint64_t TSFlags) { 966 return (TSFlags & X86II::FormMask) == PrefixByte; 967 } 968 969 /// \returns true if the instruction with given opcode is a pseudo. 970 inline bool isPseudo(uint64_t TSFlags) { 971 return (TSFlags & X86II::FormMask) == Pseudo; 972 } 973 974 /// \returns the "base" X86 opcode for the specified machine 975 /// instruction. 976 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { 977 return TSFlags >> X86II::OpcodeShift; 978 } 979 980 inline bool hasImm(uint64_t TSFlags) { 981 return (TSFlags & X86II::ImmMask) != 0; 982 } 983 984 /// Decode the "size of immediate" field from the TSFlags field of the 985 /// specified instruction. 986 inline unsigned getSizeOfImm(uint64_t TSFlags) { 987 switch (TSFlags & X86II::ImmMask) { 988 default: llvm_unreachable("Unknown immediate size"); 989 case X86II::Imm8: 990 case X86II::Imm8PCRel: 991 case X86II::Imm8Reg: return 1; 992 case X86II::Imm16: 993 case X86II::Imm16PCRel: return 2; 994 case X86II::Imm32: 995 case X86II::Imm32S: 996 case X86II::Imm32PCRel: return 4; 997 case X86II::Imm64: return 8; 998 } 999 } 1000 1001 /// \returns true if the immediate of the specified instruction's TSFlags 1002 /// indicates that it is pc relative. 1003 inline bool isImmPCRel(uint64_t TSFlags) { 1004 switch (TSFlags & X86II::ImmMask) { 1005 default: llvm_unreachable("Unknown immediate size"); 1006 case X86II::Imm8PCRel: 1007 case X86II::Imm16PCRel: 1008 case X86II::Imm32PCRel: 1009 return true; 1010 case X86II::Imm8: 1011 case X86II::Imm8Reg: 1012 case X86II::Imm16: 1013 case X86II::Imm32: 1014 case X86II::Imm32S: 1015 case X86II::Imm64: 1016 return false; 1017 } 1018 } 1019 1020 /// \returns true if the immediate of the specified instruction's 1021 /// TSFlags indicates that it is signed. 1022 inline bool isImmSigned(uint64_t TSFlags) { 1023 switch (TSFlags & X86II::ImmMask) { 1024 default: llvm_unreachable("Unknown immediate signedness"); 1025 case X86II::Imm32S: 1026 return true; 1027 case X86II::Imm8: 1028 case X86II::Imm8PCRel: 1029 case X86II::Imm8Reg: 1030 case X86II::Imm16: 1031 case X86II::Imm16PCRel: 1032 case X86II::Imm32: 1033 case X86II::Imm32PCRel: 1034 case X86II::Imm64: 1035 return false; 1036 } 1037 } 1038 1039 /// Compute whether all of the def operands are repeated in the uses and 1040 /// therefore should be skipped. 1041 /// This determines the start of the unique operand list. We need to determine 1042 /// if all of the defs have a corresponding tied operand in the uses. 1043 /// Unfortunately, the tied operand information is encoded in the uses not 1044 /// the defs so we have to use some heuristics to find which operands to 1045 /// query. 1046 inline unsigned getOperandBias(const MCInstrDesc& Desc) { 1047 unsigned NumDefs = Desc.getNumDefs(); 1048 unsigned NumOps = Desc.getNumOperands(); 1049 switch (NumDefs) { 1050 default: llvm_unreachable("Unexpected number of defs"); 1051 case 0: 1052 return 0; 1053 case 1: 1054 // Common two addr case. 1055 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 1056 return 1; 1057 // Check for AVX-512 scatter which has a TIED_TO in the second to last 1058 // operand. 1059 if (NumOps == 8 && 1060 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) 1061 return 1; 1062 return 0; 1063 case 2: 1064 // XCHG/XADD have two destinations and two sources. 1065 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 1066 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) 1067 return 2; 1068 // Check for gather. AVX-512 has the second tied operand early. AVX2 1069 // has it as the last op. 1070 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 1071 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || 1072 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1)) 1073 return 2; 1074 return 0; 1075 } 1076 } 1077 1078 /// The function returns the MCInst operand # for the first field of the 1079 /// memory operand. If the instruction doesn't have a 1080 /// memory operand, this returns -1. 1081 /// 1082 /// Note that this ignores tied operands. If there is a tied register which 1083 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 1084 /// counted as one operand. 1085 /// 1086 inline int getMemoryOperandNo(uint64_t TSFlags) { 1087 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 1088 bool HasEVEX_K = TSFlags & X86II::EVEX_K; 1089 1090 switch (TSFlags & X86II::FormMask) { 1091 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!"); 1092 case X86II::Pseudo: 1093 case X86II::RawFrm: 1094 case X86II::AddRegFrm: 1095 case X86II::RawFrmImm8: 1096 case X86II::RawFrmImm16: 1097 case X86II::RawFrmMemOffs: 1098 case X86II::RawFrmSrc: 1099 case X86II::RawFrmDst: 1100 case X86II::RawFrmDstSrc: 1101 case X86II::AddCCFrm: 1102 case X86II::PrefixByte: 1103 return -1; 1104 case X86II::MRMDestMem: 1105 case X86II::MRMDestMemFSIB: 1106 return 0; 1107 case X86II::MRMSrcMem: 1108 case X86II::MRMSrcMemFSIB: 1109 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a 1110 // mask register. 1111 return 1 + HasVEX_4V + HasEVEX_K; 1112 case X86II::MRMSrcMem4VOp3: 1113 // Skip registers encoded in reg. 1114 return 1 + HasEVEX_K; 1115 case X86II::MRMSrcMemOp4: 1116 // Skip registers encoded in reg, VEX_VVVV, and I8IMM. 1117 return 3; 1118 case X86II::MRMSrcMemCC: 1119 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a 1120 // mask register. 1121 return 1; 1122 case X86II::MRMDestReg: 1123 case X86II::MRMSrcReg: 1124 case X86II::MRMSrcReg4VOp3: 1125 case X86II::MRMSrcRegOp4: 1126 case X86II::MRMSrcRegCC: 1127 case X86II::MRMXrCC: 1128 case X86II::MRMr0: 1129 case X86II::MRMXr: 1130 case X86II::MRM0r: case X86II::MRM1r: 1131 case X86II::MRM2r: case X86II::MRM3r: 1132 case X86II::MRM4r: case X86II::MRM5r: 1133 case X86II::MRM6r: case X86II::MRM7r: 1134 return -1; 1135 case X86II::MRM0X: case X86II::MRM1X: 1136 case X86II::MRM2X: case X86II::MRM3X: 1137 case X86II::MRM4X: case X86II::MRM5X: 1138 case X86II::MRM6X: case X86II::MRM7X: 1139 return -1; 1140 case X86II::MRMXmCC: 1141 case X86II::MRMXm: 1142 case X86II::MRM0m: case X86II::MRM1m: 1143 case X86II::MRM2m: case X86II::MRM3m: 1144 case X86II::MRM4m: case X86II::MRM5m: 1145 case X86II::MRM6m: case X86II::MRM7m: 1146 // Start from 0, skip registers encoded in VEX_VVVV or a mask register. 1147 return 0 + HasVEX_4V + HasEVEX_K; 1148 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: 1149 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5: 1150 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8: 1151 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: 1152 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE: 1153 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1: 1154 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4: 1155 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7: 1156 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA: 1157 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD: 1158 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0: 1159 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3: 1160 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6: 1161 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9: 1162 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: 1163 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF: 1164 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2: 1165 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5: 1166 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8: 1167 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB: 1168 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE: 1169 case X86II::MRM_FF: 1170 return -1; 1171 } 1172 } 1173 1174 /// \returns true if the MachineOperand is a x86-64 extended (r8 or 1175 /// higher) register, e.g. r8, xmm8, xmm13, etc. 1176 inline bool isX86_64ExtendedReg(unsigned RegNo) { 1177 if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || 1178 (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) || 1179 (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31)) 1180 return true; 1181 1182 switch (RegNo) { 1183 default: break; 1184 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 1185 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 1186 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 1187 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 1188 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 1189 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 1190 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 1191 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 1192 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: 1193 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: 1194 case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11: 1195 case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15: 1196 return true; 1197 } 1198 return false; 1199 } 1200 1201 /// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher) 1202 /// registers, e.g. zmm21, etc. 1203 static inline bool is32ExtendedReg(unsigned RegNo) { 1204 return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) || 1205 (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) || 1206 (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31)); 1207 } 1208 1209 1210 inline bool isX86_64NonExtLowByteReg(unsigned reg) { 1211 return (reg == X86::SPL || reg == X86::BPL || 1212 reg == X86::SIL || reg == X86::DIL); 1213 } 1214 1215 /// \returns true if this is a masked instruction. 1216 inline bool isKMasked(uint64_t TSFlags) { 1217 return (TSFlags & X86II::EVEX_K) != 0; 1218 } 1219 1220 /// \returns true if this is a merge masked instruction. 1221 inline bool isKMergeMasked(uint64_t TSFlags) { 1222 return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0; 1223 } 1224 } 1225 1226 } // end namespace llvm; 1227 1228 #endif 1229
Indexes created Mon Jun 08 00:24:58 UTC 2026