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      1 /* $NetBSD: gttwsireg.h,v 1.4 2020/01/12 17:48:42 thorpej Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2008 Eiji Kawauchi.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 #ifndef _GTTWSIREG_H_
     28 #define _GTTWSIREG_H_
     29 
     30 #define GTTWSI_SIZE		0x100
     31 #define	GTTWSI_NREGS		7
     32 
     33 	/* reg map indices */
     34 #define	TWSI_SLAVEADDR			0
     35 #define	TWSI_EXTEND_SLAVEADDR		1
     36 #define	TWSI_DATA			2
     37 #define	TWSI_CONTROL			3
     38 #define	TWSI_STATUS			4
     39 #define	TWSI_BAUDRATE			5
     40 #define	TWSI_SOFTRESET			6
     41 
     42 	/* register offsets for Allwinner implementations */
     43 #define	TWSI_ALLWINNER_SLAVEADDR	0x00
     44 #define	TWSI_ALLWINNER_EXTEND_SLAVEADDR	0x04
     45 #define	TWSI_ALLWINNER_DATA		0x08
     46 #define	TWSI_ALLWINNER_CONTROL		0x0c
     47 #define	TWSI_ALLWINNER_STATUS		0x10
     48 #define	TWSI_ALLWINNER_BAUDRATE		0x14
     49 #define	TWSI_ALLWINNER_SOFTRESET	0x18
     50 #define	TWSI_ALLWINNER_ENH_FEAT		0x1c
     51 #define	TWSI_ALLWINNER_LINE_CTRL	0x20
     52 
     53 	/* register offsets for Marvell implementations */
     54 #define	TWSI_MARVELL_SLAVEADDR		0x00
     55 #define	TWSI_MARVELL_EXTEND_SLAVEADDR	0x10
     56 #define	TWSI_MARVELL_DATA		0x04
     57 #define	TWSI_MARVELL_CONTROL		0x08
     58 #define	TWSI_MARVELL_STATUS		0x0c	/* for read */
     59 #define	TWSI_MARVELL_BAUDRATE		0x0c	/* for write */
     60 #define	TWSI_MARVELL_SOFTRESET		0x1c
     61 
     62 #define	SLAVEADDR_GCE_MASK	0x01
     63 #define	SLAVEADDR_SADDR_MASK	0xfe
     64 
     65 #define	EXTEND_SLAVEADDR_MASK	0xff
     66 
     67 #define	DATA_MASK		0xff
     68 
     69 #define	CONTROL_ACK		(1<<2)
     70 #define	CONTROL_IFLG		(1<<3)
     71 #define	CONTROL_STOP		(1<<4)
     72 #define	CONTROL_START		(1<<5)
     73 #define	CONTROL_TWSIEN		(1<<6)
     74 #define	CONTROL_INTEN		(1<<7)
     75 
     76 #define	STAT_BE		0x00	/* Bus Error */
     77 #define	STAT_SCT	0x08	/* Start condition transmitted */
     78 #define	STAT_RSCT	0x10	/* Repeated start condition transmitted */
     79 #define	STAT_AWBT_AR	0x18	/* Address + write bit transd, ack recvd */
     80 #define	STAT_AWBT_ANR	0x20	/* Address + write bit transd, ack not recvd */
     81 #define	STAT_MTDB_AR	0x28	/* Master transd data byte, ack recvd */
     82 #define	STAT_MTDB_ANR	0x30	/* Master transd data byte, ack not recvd */
     83 #define	STAT_MLADADT	0x38	/* Master lost arbitr during addr or data tx */
     84 #define	STAT_ARBT_AR	0x40	/* Address + read bit transd, ack recvd */
     85 #define	STAT_ARBT_ANR	0x48	/* Address + read bit transd, ack not recvd */
     86 #define	STAT_MRRD_AT	0x50	/* Master received read data, ack transd */
     87 #define	STAT_MRRD_ANT	0x58	/* Master received read data, ack not transd */
     88 #define	STAT_SAWBT_AR	0xd0	/* Second addr + write bit transd, ack recvd */
     89 #define	STAT_SAWBT_ANR	0xd8	/* S addr + write bit transd, ack not recvd */
     90 #define	STAT_SARBT_AR	0xe0	/* Second addr + read bit transd, ack recvd */
     91 #define	STAT_SARBT_ANR	0xe8	/* S addr + read bit transd, ack not recvd */
     92 #define	STAT_NRS	0xf8	/* No relevant status */
     93 
     94 #define	SOFTRESET_VAL		0		/* reset value */
     95 
     96 #define TWSI_RETRY_COUNT	1000		/* retry loop count */
     97 #define TWSI_RETRY_DELAY	1		/* retry delay */
     98 #define	TWSI_STAT_DELAY		1		/* poll status delay */
     99 #define	TWSI_READ_DELAY		2		/* read delay */
    100 #define	TWSI_WRITE_DELAY	2		/* write delay */
    101 
    102 #endif	/* _GTTWSIREG_H_ */
    103