1 /* $NetBSD: qat_c62xreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */ 2 3 /* 4 * Copyright (c) 2019 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright(c) 2014 Intel Corporation. 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 35 * * Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * * Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in 39 * the documentation and/or other materials provided with the 40 * distribution. 41 * * Neither the name of Intel Corporation nor the names of its 42 * contributors may be used to endorse or promote products derived 43 * from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 46 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 47 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 48 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 49 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 55 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58 #ifndef _DEV_PCI_QAT_C62XREG_H_ 59 #define _DEV_PCI_QAT_C62XREG_H_ 60 61 /* Max number of accelerators and engines */ 62 #define MAX_ACCEL_C62X 5 63 #define MAX_AE_C62X 10 64 65 /* PCIe BAR index */ 66 #define BAR_SRAM_ID_C62X 0 67 #define BAR_PMISC_ID_C62X 1 68 #define BAR_ETR_ID_C62X 2 69 70 /* BAR PMISC sub-regions */ 71 #define AE_OFFSET_C62X 0x20000 72 #define AE_LOCAL_OFFSET_C62X 0x20800 73 #define CAP_GLOBAL_OFFSET_C62X 0x30000 74 75 #define SOFTSTRAP_REG_C62X 0x2EC 76 #define SOFTSTRAP_SS_POWERGATE_CY_C62X __BIT(23) 77 #define SOFTSTRAP_SS_POWERGATE_PKE_C62X __BIT(24) 78 79 #define ACCEL_REG_OFFSET_C62X 16 80 #define ACCEL_MASK_C62X 0x1F 81 #define AE_MASK_C62X 0x3FF 82 83 #define SMIAPF0_C62X 0x3A028 84 #define SMIAPF1_C62X 0x3A030 85 #define SMIA0_MASK_C62X 0xFFFF 86 #define SMIA1_MASK_C62X 0x1 87 88 /* Error detection and correction */ 89 #define AE_CTX_ENABLES_C62X(i) ((i) * 0x1000 + 0x20818) 90 #define AE_MISC_CONTROL_C62X(i) ((i) * 0x1000 + 0x20960) 91 #define ENABLE_AE_ECC_ERR_C62X __BIT(28) 92 #define ENABLE_AE_ECC_PARITY_CORR_C62X (__BIT(24) | __BIT(12)) 93 #define ERRSSMSH_EN_C62X __BIT(3) 94 /* BIT(2) enables the logging of push/pull data errors. */ 95 #define PPERR_EN_C62X (__BIT(2)) 96 97 /* Mask for VF2PF interrupts */ 98 #define VF2PF1_16_C62X (0xFFFF << 9) 99 #define ERRSOU3_VF2PF_C62X(errsou3) (((errsou3) & 0x01FFFE00) >> 9) 100 #define ERRMSK3_VF2PF_C62X(vf_mask) (((vf_mask) & 0xFFFF) << 9) 101 102 /* Masks for correctable error interrupts. */ 103 #define ERRMSK0_CERR_C62X (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0)) 104 #define ERRMSK1_CERR_C62X (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0)) 105 #define ERRMSK3_CERR_C62X (__BIT(7)) 106 #define ERRMSK4_CERR_C62X (__BIT(8) | __BIT(0)) 107 #define ERRMSK5_CERR_C62X (0) 108 109 /* Masks for uncorrectable error interrupts. */ 110 #define ERRMSK0_UERR_C62X (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1)) 111 #define ERRMSK1_UERR_C62X (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1)) 112 #define ERRMSK3_UERR_C62X (__BIT(8) | __BIT(6) | __BIT(5) | __BIT(4) | \ 113 __BIT(3) | __BIT(2) | __BIT(0)) 114 #define ERRMSK4_UERR_C62X (__BIT(9) | __BIT(1)) 115 #define ERRMSK5_UERR_C62X (__BIT(18) | __BIT(17) | __BIT(16)) 116 117 /* RI CPP control */ 118 #define RICPPINTCTL_C62X (0x3A000 + 0x110) 119 /* 120 * BIT(2) enables error detection and reporting on the RI Parity Error. 121 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 122 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 123 */ 124 #define RICPP_EN_C62X (__BIT(2) | __BIT(1) | __BIT(0)) 125 126 /* TI CPP control */ 127 #define TICPPINTCTL_C62X (0x3A400 + 0x138) 128 /* 129 * BIT(3) enables error detection and reporting on the ETR Parity Error. 130 * BIT(2) enables error detection and reporting on the TI Parity Error. 131 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 132 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 133 */ 134 #define TICPP_EN_C62X \ 135 (__BIT(4) | __BIT(3) | __BIT(2) | __BIT(1) | __BIT(0)) 136 137 /* CFC Uncorrectable Errors */ 138 #define CPP_CFC_ERR_CTRL_C62X (0x30000 + 0xC00) 139 /* 140 * BIT(1) enables interrupt. 141 * BIT(0) enables detecting and logging of push/pull data errors. 142 */ 143 #define CPP_CFC_UE_C62X (__BIT(1) | __BIT(0)) 144 145 /* Correctable SecureRAM Error Reg */ 146 #define SECRAMCERR_C62X (0x3AC00 + 0x00) 147 /* BIT(3) enables fixing and logging of correctable errors. */ 148 #define SECRAM_CERR_C62X (__BIT(3)) 149 150 /* Uncorrectable SecureRAM Error Reg */ 151 /* 152 * BIT(17) enables interrupt. 153 * BIT(3) enables detecting and logging of uncorrectable errors. 154 */ 155 #define SECRAM_UERR_C62X (__BIT(17) | __BIT(3)) 156 157 /* Miscellaneous Memory Target Errors Register */ 158 /* 159 * BIT(3) enables detecting and logging push/pull data errors. 160 * BIT(2) enables interrupt. 161 */ 162 #define TGT_UERR_C62X (__BIT(3) | __BIT(2)) 163 164 165 #define SLICEPWRDOWN_C62X(i) ((i) * 0x4000 + 0x2C) 166 /* Enabling PKE4-PKE0. */ 167 #define MMP_PWR_UP_MSK_C62X \ 168 (__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16)) 169 170 /* CPM Uncorrectable Errors */ 171 #define INTMASKSSM_C62X(i) ((i) * 0x4000 + 0x0) 172 /* Disabling interrupts for correctable errors. */ 173 #define INTMASKSSM_UERR_C62X \ 174 (__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1)) 175 176 /* MMP */ 177 /* BIT(3) enables correction. */ 178 #define CERRSSMMMP_EN_C62X (__BIT(3)) 179 180 /* BIT(3) enables logging. */ 181 #define UERRSSMMMP_EN_C62X (__BIT(3)) 182 183 /* ETR */ 184 #define ETR_MAX_BANKS_C62X 16 185 #define ETR_TX_RX_GAP_C62X 8 186 #define ETR_TX_RINGS_MASK_C62X 0xFF 187 #define ETR_BUNDLE_SIZE_C62X 0x1000 188 189 /* AE firmware */ 190 #define AE_FW_PROD_TYPE_C62X 0x01000000 191 #define AE_FW_MOF_NAME_C62X "qat_c62x.bin" 192 #define AE_FW_MMP_NAME_C62X "qat_c62x_mmp.bin" 193 #define AE_FW_UOF_NAME_C62X "icp_qat_ae.suof" 194 195 /* Clock frequency */ 196 #define CLOCK_PER_SEC_C62X (685 * 1000000 / 16) 197 198 #endif 199
Indexes created Mon Sep 22 13:09:51 GMT 2025