1 /* $NetBSD: cpuvar.h,v 1.97 2018/01/17 07:38:20 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _sparc_cpuvar_h 33 #define _sparc_cpuvar_h 34 35 #if defined(_KERNEL_OPT) 36 #include "opt_multiprocessor.h" 37 #include "opt_lockdebug.h" 38 #include "opt_ddb.h" 39 #include "opt_sparc_arch.h" 40 #include "opt_modular.h" 41 #endif 42 43 #include <sys/device.h> 44 #include <sys/lock.h> 45 #include <sys/cpu_data.h> 46 47 #include <sparc/include/reg.h> 48 #include <sparc/sparc/cache.h> /* for cacheinfo */ 49 50 /* 51 * CPU/MMU module information. 52 * There is one of these for each "mainline" CPU module we support. 53 * The information contained in the structure is used only during 54 * auto-configuration of the CPUs; some fields are copied into the 55 * per-cpu data structure (cpu_info) for easy access during normal 56 * operation. 57 */ 58 struct cpu_info; 59 struct module_info { 60 int cpu_type; 61 enum vactype vactype; 62 void (*cpu_match)(struct cpu_info *, struct module_info *, int); 63 void (*getcacheinfo)(struct cpu_info *sc, int node); 64 void (*hotfix)(struct cpu_info *); 65 void (*mmu_enable)(void); 66 void (*cache_enable)(void); 67 int (*getmid)(void); /* Get MID of current CPU */ 68 int ncontext; /* max. # of contexts (that we use) */ 69 70 void (*get_syncflt)(void); 71 int (*get_asyncflt)(u_int *, u_int *); 72 void (*cache_flush)(void *, u_int); 73 void (*sp_vcache_flush_page)(int, int); 74 void (*ft_vcache_flush_page)(int, int); 75 void (*sp_vcache_flush_segment)(int, int, int); 76 void (*ft_vcache_flush_segment)(int, int, int); 77 void (*sp_vcache_flush_region)(int, int); 78 void (*ft_vcache_flush_region)(int, int); 79 void (*sp_vcache_flush_context)(int); 80 void (*ft_vcache_flush_context)(int); 81 void (*sp_vcache_flush_range)(int, int, int); 82 void (*ft_vcache_flush_range)(int, int, int); 83 void (*pcache_flush_page)(paddr_t, int); 84 void (*pure_vcache_flush)(void); 85 void (*cache_flush_all)(void); 86 void (*memerr)(unsigned, u_int, u_int, struct trapframe *); 87 void (*zero_page)(paddr_t); 88 void (*copy_page)(paddr_t, paddr_t); 89 }; 90 91 /* 92 * CPU architectures 93 */ 94 #define CPUARCH_UNKNOWN 0 95 #define CPUARCH_SUN4 1 96 #define CPUARCH_SUN4C 2 97 #define CPUARCH_SUN4M 3 98 #define CPUARCH_SUN4D 4 99 #define CPUARCH_SUN4U 5 100 101 /* 102 * CPU classes 103 */ 104 #define CPUCLS_UNKNOWN 0 105 106 #if defined(SUN4) 107 #define CPUCLS_SUN4 1 108 #endif 109 110 #if defined(SUN4C) 111 #define CPUCLS_SUN4C 5 112 #endif 113 114 #if defined(SUN4M) || defined(SUN4D) 115 #define CPUCLS_MICROSPARC 10 /* MicroSPARC-II */ 116 #define CPUCLS_SUPERSPARC 11 /* Generic SuperSPARC */ 117 #define CPUCLS_HYPERSPARC 12 /* Ross HyperSPARC RT620 */ 118 #endif 119 120 /* 121 * CPU types. Each of these should uniquely identify one platform/type of 122 * system, i.e. "MBus-based 75 MHz SuperSPARC-II with ECache" is 123 * CPUTYP_SS2_MBUS_MXCC. The general form is 124 * CPUTYP_proctype_bustype_cachetype_etc_etc 125 * 126 * XXX: This is far from complete/comprehensive 127 * XXX: ADD SUN4, SUN4C TYPES 128 */ 129 #define CPUTYP_UNKNOWN 0 130 131 #define CPUTYP_4_100 1 /* Sun4/100 */ 132 #define CPUTYP_4_200 2 /* Sun4/200 */ 133 #define CPUTYP_4_300 3 /* Sun4/300 */ 134 #define CPUTYP_4_400 4 /* Sun4/400 */ 135 136 #define CPUTYP_SLC 10 /* SPARCstation SLC */ 137 #define CPUTYP_ELC 11 /* SPARCstation ELC */ 138 #define CPUTYP_IPX 12 /* SPARCstation IPX */ 139 #define CPUTYP_IPC 13 /* SPARCstation IPC */ 140 #define CPUTYP_1 14 /* SPARCstation 1 */ 141 #define CPUTYP_1P 15 /* SPARCstation 1+ */ 142 #define CPUTYP_2 16 /* SPARCstation 2 */ 143 144 /* We classify the Sun4m's by feature, not by model (XXX: do same for 4/4c) */ 145 #define CPUTYP_SS2_MBUS_MXCC 20 /* SuperSPARC-II, Mbus, MXCC (SS20) */ 146 #define CPUTYP_SS1_MBUS_MXCC 21 /* SuperSPARC-I, Mbus, MXCC (SS10) */ 147 #define CPUTYP_SS2_MBUS_NOMXCC 22 /* SuperSPARC-II, on MBus w/o MXCC */ 148 #define CPUTYP_SS1_MBUS_NOMXCC 23 /* SuperSPARC-I, on MBus w/o MXCC */ 149 #define CPUTYP_MS2 24 /* MicroSPARC-2 */ 150 #define CPUTYP_MS1 25 /* MicroSPARC-1 */ 151 #define CPUTYP_HS_MBUS 26 /* MBus-based HyperSPARC */ 152 #define CPUTYP_CYPRESS 27 /* MBus-based Cypress */ 153 154 /* 155 * CPU flags 156 */ 157 #define CPUFLG_HATCHED 0x1000 /* CPU is alive */ 158 #define CPUFLG_PAUSED 0x2000 /* CPU is paused */ 159 #define CPUFLG_GOTMSG 0x4000 /* CPU got an lev13 IPI */ 160 161 162 /* 163 * Provide two forms of CPU_INFO_FOREACH. One fast one for non-modular 164 * non-SMP kernels, and the other for everyone else. Both work in the 165 * non-SMP case, just involving an extra indirection through cpus[0] for 166 * the portable version. 167 */ 168 #if defined(MULTIPROCESSOR) || defined(MODULAR) || defined(_MODULE) 169 #define CPU_INFO_FOREACH(cii, cp) cii = 0; (cp = cpus[cii]) && cp->eintstack && cii < sparc_ncpus; cii++ 170 #define CPU_INFO_ITERATOR int 171 #else 172 #define CPU_INFO_FOREACH(cii, cp) cp = curcpu(); cp != NULL; cp = NULL 173 #define CPU_INFO_ITERATOR int __unused 174 #endif 175 176 177 /* 178 * Related function prototypes 179 */ 180 void getcpuinfo (struct cpu_info *sc, int node); 181 void mmu_install_tables (struct cpu_info *); 182 void pmap_alloc_cpu (struct cpu_info *); 183 184 #define CPUSET_ALL 0xffffffffU /* xcall to all configured CPUs */ 185 186 #if defined(MULTIPROCESSOR) 187 void cpu_init_system(void); 188 typedef void (*xcall_func_t)(int, int, int); 189 typedef void (*xcall_trap_t)(int, int, int); 190 void xcall(xcall_func_t, xcall_trap_t, int, int, int, u_int); 191 /* from intr.c */ 192 void xcallintr(void *); 193 /* Shorthand */ 194 #define XCALL0(f,cpuset) \ 195 xcall((xcall_func_t)f, NULL, 0, 0, 0, cpuset) 196 #define XCALL1(f,a1,cpuset) \ 197 xcall((xcall_func_t)f, NULL, (int)a1, 0, 0, cpuset) 198 #define XCALL2(f,a1,a2,cpuset) \ 199 xcall((xcall_func_t)f, NULL, (int)a1, (int)a2, 0, cpuset) 200 #define XCALL3(f,a1,a2,a3,cpuset) \ 201 xcall((xcall_func_t)f, NULL, (int)a1, (int)a2, (int)a3, cpuset) 202 203 #define FXCALL0(f,tf,cpuset) \ 204 xcall((xcall_func_t)f, (xcall_trap_t)tf, 0, 0, 0, cpuset) 205 #define FXCALL1(f,tf,a1,cpuset) \ 206 xcall((xcall_func_t)f, (xcall_trap_t)tf, (int)a1, 0, 0, cpuset) 207 #define FXCALL2(f,tf,a1,a2,cpuset) \ 208 xcall((xcall_func_t)f, (xcall_trap_t)tf, (int)a1, (int)a2, 0, cpuset) 209 #define FXCALL3(f,tf,a1,a2,a3,cpuset) \ 210 xcall((xcall_func_t)f, (xcall_trap_t)tf, (int)a1, (int)a2, (int)a3, cpuset) 211 #else 212 #define XCALL0(f,cpuset) /**/ 213 #define XCALL1(f,a1,cpuset) /**/ 214 #define XCALL2(f,a1,a2,cpuset) /**/ 215 #define XCALL3(f,a1,a2,a3,cpuset) /**/ 216 #define FXCALL0(f,tf,cpuset) /**/ 217 #define FXCALL1(f,tf,a1,cpuset) /**/ 218 #define FXCALL2(f,tf,a1,a2,cpuset) /**/ 219 #define FXCALL3(f,tf,a1,a2,a3,cpuset) /**/ 220 #endif /* MULTIPROCESSOR */ 221 222 extern int bootmid; /* Module ID of boot CPU */ 223 #define CPU_MID2CPUNO(mid) ((mid) != 0 ? (mid) - 8 : 0) 224 225 extern struct cpu_info *cpus[]; 226 #ifdef MULTIPROCESSOR 227 extern u_int cpu_ready_mask; /* the set of CPUs marked as READY */ 228 #endif 229 230 #if defined(DDB) || defined(MULTIPROCESSOR) 231 /* 232 * These are called by ddb mach functions. 233 */ 234 void cpu_debug_dump(void); 235 void cpu_xcall_dump(void); 236 #endif 237 238 #endif /* _sparc_cpuvar_h */ 239
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