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      1 /*      $NetBSD: sa11x0_sspreg.h,v 1.4 2024/02/04 18:52:35 andvar Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
      5  *
      6  * This code is derived from software contributed to The NetBSD Foundation
      7  * by IWAMOTO Toshihiro.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 /* SA11[01]0 integrated SSP (synchronous serial port) interface */
     32 
     33 #define SASSP_FREQ	(3686400 / 2)
     34 #define SASSPSPEED(b)	(SACOM_FREQ / (b) - 1)
     35 
     36 /* size of I/O space */
     37 #define SASSP_NPORTS	30
     38 
     39 #define SASSP_TXFIFOLEN		8
     40 #define SASSP_RXFIFOLEN		12
     41 
     42 /* SSP control register 0 */
     43 #define SASSP_CR0	0x60
     44 #define CR0_DSS_MASK	0x000F	/* Data size select */
     45 #define CR0_FRF_MASK	0x0030	/* Frame format */
     46 #define CR0_SSE		0x0080	/* SSP enable */
     47 #define CR0_SCR_MASK	0xFF00	/* Serial clock rate */
     48 
     49 /* SSP control register 1 */
     50 #define SASSP_CR1	0x64
     51 #define CR1_RIE		0x01	/* Receive FIFO interrupt enable */
     52 #define CR1_TIE		0x02	/* Transmit FIFO interrupt enable */
     53 #define CR1_LBM		0x04	/* Loopback mode */
     54 #define CR1_SPO		0x08	/* Serial clock polarity */
     55 #define CR1_SPH		0x10	/* Serial clock phase */
     56 #define CR1_ECS		0x20	/* External clock select */
     57 
     58 /* SSP data register */
     59 #define SASSP_DR	0x6C
     60 
     61 /* SSP status register */
     62 #define SASSP_SR	0x74
     63 #define SR_TNF		0x02	/* Transmit FIFO not full */
     64 #define SR_RNE		0x04	/* Receive FIFO not empty */
     65 #define SR_BSY		0x08	/* SSP busy flag */
     66 #define SR_TFS		0x10	/* Transmit FIFO service request */
     67 #define SR_RFS		0x20	/* Receive FIFO service request */
     68 #define SR_ROR		0x40	/* Receive FIFO overrun */
     69