| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_ipp.c | 44 #define CTX \
45 ippn10->base.ctx
67 struct dc_context *ctx,
73 ippn10->base.ctx = ctx;
84 struct dc_context *ctx,
90 ippn10->base.ctx = ctx;
|
| dcn10_dwb.c | 42 #define CTX \
43 dwbc10->base.ctx
122 struct dc_context *ctx,
128 dwbc10->base.ctx = ctx;
|
| amdgpu_dcn10_opp.c | 44 #define CTX \
45 oppn10->base.ctx
416 struct dc_context *ctx,
423 oppn10->base.ctx = ctx;
|
| amdgpu_dcn10_cm_common.c | 39 #define CTX \
40 ctx
47 struct dc_context *ctx,
71 struct dc_context *ctx,
332 PERF_TRACE_CTX(output_tf->ctx);
519 PERF_TRACE_CTX(output_tf->ctx);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_vmid.c | 39 #define CTX \
40 vmid->ctx
|
| amdgpu_dcn20_mmhubbub.c | 41 #define CTX \
42 mcif_wb20->base.ctx
314 struct dc_context *ctx,
320 mcif_wb20->base.ctx = ctx;
|
| amdgpu_dcn20_dccg.c | 47 #define CTX \
48 dccg_dcn->base.ctx
50 dccg->ctx->logger
113 struct dc_context *ctx,
127 base->ctx = ctx;
|
| amdgpu_dcn20_dwb.c | 41 #define CTX \
42 dwbc20->base.ctx
45 dwbc20->base.ctx->logger
322 struct dc_context *ctx,
328 dwbc20->base.ctx = ctx;
|
| amdgpu_dcn20_link_encoder.c | 42 #define CTX \
43 enc10->base.ctx
45 enc10->base.ctx->logger
254 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
272 dm_read_reg(CTX, AUX_REG(reg_name))
275 dm_write_reg(CTX, AUX_REG(reg_name), val)
359 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
364 enc10->base.ctx = init_data->ctx;
441 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios
[all...] |
| amdgpu_dcn20_opp.c | 42 #define CTX \
43 oppn20->base.ctx
359 struct dc_context *ctx,
365 oppn20->base.ctx = ctx;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| amdgpu_dmub_dcn21.c | 40 #define CTX dmub
|
| amdgpu_dmub_dcn20.c | 41 #define CTX dmub
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
| amdgpu_bios_parser_helper.c | 53 #define CTX \
54 bios->ctx
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_ipp.c | 44 #define CTX \
45 ipp_dce->base.ctx
253 struct dc_context *ctx,
259 ipp_dce->base.ctx = ctx;
|
| amdgpu_dce_hwseq.c | 36 #define CTX \
37 hws->ctx
|
| amdgpu_dce_opp.c | 47 #define CTX \
48 opp110->base.ctx
550 struct dc_context *ctx,
558 opp110->base.ctx = ctx;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_hw_sequencer.c | 45 #define CTX \
46 hws->ctx
88 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
98 value = dm_read_reg(ctx, addr);
115 dm_write_reg(ctx, addr, value);*/
118 value = dm_read_reg(ctx, addr);
150 dm_write_reg(ctx, addr, value);
165 struct dc_context *ctx = dc->ctx;
167 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hwseq.c | 44 #define CTX \
45 hws->ctx
|
| amdgpu_dcn21_hubbub.c | 39 hubbub1->base.ctx->logger
40 #define CTX \
41 hubbub1->base.ctx
50 #define CTX \
51 hubbub1->base.ctx
556 hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
647 struct dc_context *ctx,
652 hubbub->base.ctx = ctx;
|
| amdgpu_dcn21_link_encoder.c | 44 #define CTX \
45 enc10->base.ctx
47 enc10->base.ctx->logger
294 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
371 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
376 enc10->base.ctx = init_data->ctx;
453 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
470 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| amdgpu_hw_generic.c | 47 #define CTX \
48 generic->base.base.ctx
102 struct dc_context *ctx)
104 dal_hw_gpio_construct(&pin->base, id, en, ctx);
110 struct dc_context *ctx,
125 dal_hw_generic_construct(*hw_generic, id, en, ctx);
|
| amdgpu_hw_gpio.c | 42 #define CTX \
43 gpio->base.ctx
188 struct dc_context *ctx)
190 pin->base.ctx = ctx;
|
| amdgpu_hw_hpd.c | 47 #define CTX \
48 hpd->base.base.ctx
126 struct dc_context *ctx)
128 dal_hw_gpio_construct(&pin->base, id, en, ctx);
134 struct dc_context *ctx,
149 dal_hw_hpd_construct(*hw_hpd, id, en, ctx);
|
| amdgpu_hw_ddc.c | 49 #define CTX \
50 ddc->base.base.ctx
228 struct dc_context *ctx)
230 dal_hw_gpio_construct(&ddc->base, id, en, ctx);
236 struct dc_context *ctx,
251 dal_hw_ddc_construct(*hw_ddc, id, en, ctx);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/ |
| amdgpu_irq_service.c | 55 #define CTX \
56 irq_service->ctx
58 irq_service->ctx->logger
64 if (!init_data || !init_data->ctx) {
69 irq_service->ctx = init_data->ctx;
100 uint32_t value = dm_read_reg(irq_service->ctx, addr);
104 dm_write_reg(irq_service->ctx, addr, value);
137 uint32_t value = dm_read_reg(irq_service->ctx, addr);
141 dm_write_reg(irq_service->ctx, addr, value)
[all...] |
