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      1 /*	$NetBSD: intel_lrc_reg.h,v 1.2 2021/12/18 23:45:30 riastradh Exp $	*/
      2 
      3 /*
      4  * SPDX-License-Identifier: MIT
      5  *
      6  * Copyright  2014-2018 Intel Corporation
      7  */
      8 
      9 #ifndef _INTEL_LRC_REG_H_
     10 #define _INTEL_LRC_REG_H_
     11 
     12 #include <linux/types.h>
     13 
     14 /* GEN8 to GEN11 Reg State Context */
     15 #define CTX_CONTEXT_CONTROL		(0x02 + 1)
     16 #define CTX_RING_HEAD			(0x04 + 1)
     17 #define CTX_RING_TAIL			(0x06 + 1)
     18 #define CTX_RING_START			(0x08 + 1)
     19 #define CTX_RING_CTL			(0x0a + 1)
     20 #define CTX_BB_STATE			(0x10 + 1)
     21 #define CTX_BB_PER_CTX_PTR		(0x18 + 1)
     22 #define CTX_PDP3_UDW			(0x24 + 1)
     23 #define CTX_PDP3_LDW			(0x26 + 1)
     24 #define CTX_PDP2_UDW			(0x28 + 1)
     25 #define CTX_PDP2_LDW			(0x2a + 1)
     26 #define CTX_PDP1_UDW			(0x2c + 1)
     27 #define CTX_PDP1_LDW			(0x2e + 1)
     28 #define CTX_PDP0_UDW			(0x30 + 1)
     29 #define CTX_PDP0_LDW			(0x32 + 1)
     30 #define CTX_R_PWR_CLK_STATE		(0x42 + 1)
     31 
     32 #define GEN9_CTX_RING_MI_MODE		0x54
     33 
     34 /* GEN12+ Reg State Context */
     35 #define GEN12_CTX_BB_PER_CTX_PTR		(0x12 + 1)
     36 
     37 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
     38 	u32 *reg_state__ = (reg_state); \
     39 	const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \
     40 	(reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \
     41 	(reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \
     42 } while (0)
     43 
     44 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
     45 	u32 *reg_state__ = (reg_state); \
     46 	const u64 addr__ = px_dma(ppgtt->pd); \
     47 	(reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \
     48 	(reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \
     49 } while (0)
     50 
     51 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
     52 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
     53 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x19
     54 #define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x1A
     55 #define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0xD
     56 
     57 #endif /* _INTEL_LRC_REG_H_ */
     58