1 /* $NetBSD: ct65550reg.h,v 1.3 2017/02/02 19:55:05 macallan Exp $ */ 2 3 /* 4 * Copyright 2006 by Michael Lorenz. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #ifndef CHIPSFB_H 29 #define CHIPSFB_H 30 31 /* VGA */ 32 #define CRTC_INDEX 0x3d4 33 #define CRTC_DATA 0x3d5 34 #define SEQ_INDEX 0x3c4 35 #define SEQ_DATA 0x3c5 36 #define MISC_W 0x3c2 37 #define GRA_INDEX 0x3ce 38 #define GRA_DATA 0x3cf 39 #define ATT_IW 0x3c0 40 41 /* palette */ 42 #define CT_DACMASK 0x3c6 43 #define CT_DACSTATE 0x3c7 /* read only */ 44 #define CT_READINDEX 0x3c7 /* write only */ 45 #define CT_WRITEINDEX 0x3c8 46 #define CT_DACDATA 0x3c9 47 48 /* extended VGA */ 49 #define CT_FP_INDEX 0x3d0 50 #define CT_FP_DATA 0x3d1 51 #define CT_MM_INDEX 0x3d2 52 #define CT_MM_DATA 0x3d3 53 #define CT_CONF_INDEX 0x3d6 54 #define CT_CONF_DATA 0x3d7 55 56 /* offsets in aperture */ 57 #define CT_OFF_FB 0x00000000 58 #define CT_OFF_BITBLT 0x00400000 59 #define CT_OFF_DRAW 0x00400040 60 #define CT_OFF_DATA 0x00410000 61 62 #define CT_OFF_BE 0x00800000 63 64 /* blitter registers */ 65 #define CT_BLT_STRIDE 0x00000000 66 /* 67 * upper 16 bit are destination stride in bytes 68 * lower 16 bit are source stride in bytes 69 */ 70 71 #define CT_BLT_BG 0x04 72 #define CT_BLT_FG 0x08 73 #define CT_BLT_EXPCTL 0x0c /* expansion control */ 74 #define LEFT_CLIPPING_MSK 0x0000003f 75 #define MONO_RIGHT_CLIPPING_MSK 0x00003f00 76 #define MONO_INITIAL_DISCARD 0x003f0000 77 #define MONO_SRC_ALIGN_MASK 0x07000000 78 #define MONO_SRC_ALIGN_BIT 0x01000000 79 #define MONO_SRC_ALIGN_BYTE 0x02000000 80 #define MONO_SRC_ALIGN_WORD 0x03000000 81 #define MONO_SRC_ALIGN_LONG 0x04000000 82 #define MONO_SRC_ALIGN_LONGLONG 0x05000000 83 #define MONO_SELECT_ALT_FG_BG 0x08000000 /* use CT_SRC_EXP_* */ 84 85 #define CT_BLT_CONTROL 0x10 86 #define BLT_ROP_MASK 0x000000ff 87 #define BLT_START_RIGHT 0x00000100 /* 0 for start left */ 88 #define BLT_START_BOTTOM 0x00000200 /* 0 for start top */ 89 #define BLT_SRC_IS_CPU 0x00000400 /* 0 for vram source */ 90 #define BLT_SRC_IS_MONO 0x00001000 91 #define BLT_MONO_TRANSPARENCY 0x00002000 92 #define BLT_COLOR_COMPARE_MASK 0x0001c000 /* 0 for no color keying */ 93 #define BLT_PAT_TRANSPARENCY 0x00020000 /* pattern is transparent */ 94 #define BLT_PAT_IS_MONO 0x00040000 95 #define BLT_PAT_IS_SOLID 0x00080000 /* ignore pattern */ 96 #define BLT_PAT_VERT_ALIGN_MASK 0x00700000 97 #define BLT_IS_BUSY 0x80000000 98 99 #define ROP_COPY 0xcc 100 #define ROP_NOT_SRC 0x33 101 #define ROP_NOT_DST 0x55 102 #define ROP_PAT 0xf0 103 104 #define CT_BLT_PATTERN 0x14 /* address in vram */ 105 #define CT_BLT_SRCADDR 0x18 106 #define CT_BLT_DSTADDR 0x1c 107 108 #define CT_BLT_SIZE 0x20 /* width and height */ 109 /* 110 * upper 16 bit are destination height 111 * lower 16 bit are destination width in bytes 112 */ 113 114 #define CT_SRC_EXP_BG 0x24 115 #define CT_SRC_EXP_FG 0x28 116 117 /* extension registers ( via CT_CONF */ 118 #define XR_VENDOR_LO 0x00 119 #define XR_VENDOR_HI 0x01 120 #define XR_DEVICE_LO 0x02 121 #define XR_DEVICE_HI 0x03 122 #define XR_REVISION 0x04 123 #define XR_LINEAR_BASE_LO 0x05 124 #define XR_LINEAR_BASE_HI 0x06 125 126 #define XR_CONFIGURATION 0x08 127 #define BUS_PCI 0x01 128 #define BUS_VL 0x00 129 #define ENABLE_PCI 0x02 130 131 #define XR_IO_CONTROL 0x09 132 #define ENABLE_CRTC_EXT 0x01 133 #define ENABLE_ATTR_EXT 0x02 134 135 #define XR_ADDR_MAPPING 0x0a 136 #define ENABLE_MAPPING 0x01 /* in VGA window */ 137 #define ENABLE_LINEAR 0x02 138 #define ENABLE_PACKED 0x04 139 #define FB_SWAP_NONE 0x00 140 #define FB_SWAP_16 0x10 141 #define FB_SWAP_32 0x20 142 143 #define XR_BURST_WRITE_MODE 0x0b 144 145 #define XR_PAGE_SELECT 0x0e 146 147 #define XR_BITBLT_CONTROL0 0x20 148 #define BLITTER_BUSY 0x01 149 #define BLITTER_RESET 0x02 150 #define BLITTER_8BIT 0x00 151 #define BLITTER_16BIT 0x10 152 #define BLITTER_24BIT 0x20 153 #define BLITTER_32BIT 0x30 /* reserved */ 154 155 #define XR_DRAM_ACCESS_CONTROL 0x40 156 #define ENABLE_64BIT 0x01 157 #define DISABLE_WRAP 0x02 /* otherwise only 256kB */ 158 #define EXTENDED_TEXT 0x10 159 160 #define XR_DRAM_TYPE 0x41 161 #define DRAM_FASTPAGE 0x00 162 #define DRAM_EDO 0x01 163 164 #define XR_DRAM_CONFIG 0x42 165 #define DRAM_8BIT_COL 0x00 166 #define DRAM_9BIT_COL 0x01 167 168 #define XR_DRAM_INTERFACE 0x43 169 #define XR_DRAM_TIMING 0x44 170 171 #define XR_VIDEO_PIN_CONTROL 0x60 172 #define XR_DDC_SYNC_SELECT 0x61 173 #define DDC_HSYNC_DATA 0x01 174 #define DDC_HSYNC_OUT 0x02 /* hsync is controlled by above */ 175 #define DDC_VSYNC_DATA 0x04 176 #define DDC_VSYNC_OUT 0x08 /* vsync is controlled by above */ 177 #define DDC_HV_POWERDOWN 0x10 178 #define DDC_ENABLE_HSYNC 0x20 179 #define DDC_ENABLE_VSYNC 0x40 180 181 /* 182 * upper 6 bit define if corresponding bits in DATA are input or output 183 * 1 selects output 184 */ 185 #define XR_GPIO_CONTROL 0x62 186 #define XR_GPIO_DATA 0x63 187 188 #define XR_PIN_TRISTATE_CONTROL 0x67 189 190 #define XR_CONFIG_PINS_0 0x70 191 #define XR_CONFIG_PINS_1 0x71 192 193 #define XR_PIXEL_PIPELINE_CTL_0 0x80 194 #define ENABLE_EXTENDED_PALETTE 0x01 195 #define ENABLE_CRT_OVERSCAN 0x02 196 #define ENABLE_PANEL_OVERSCAN 0x04 197 #define ENABLE_EXTENDED_STATUS 0x08 198 #define ENABLE_CURSOR_1 0x10 199 #define ENABLE_PIXEL_AVERAGING 0x20 200 #define SELECT_PIXEL_STREAM 0x40 /* 1 for P1 */ 201 #define ENABLE_8BIT_DAC 0x80 /* 6 bit otherwise */ 202 203 #define XR_PIXEL_PIPELINE_CTL_1 0x81 204 #define COLOR_VGA 0x00 205 #define COLOR_8BIT_EXTENDED 0x02 206 #define COLOR_15BIT 0x04 207 #define COLOR_16BIT 0x05 208 #define COLOR_24BIT 0x06 209 #define COLOR_32BIT 0x07 210 211 #define XR_PIXEL_PIPELINE_CTL_2 0x82 212 #define ENABLE_BLANK_PEDESTAL 0x01 213 #define ENABLE_SYNC_ON_GREEN 0x02 214 #define ENABLE_VIDEO_GAMMA 0x04 215 #define ENABLE_GRAPHICS_GAMMA 0x08 216 217 #define XR_CURSOR_1_CTL 0xa0 218 #define XR_CURSOR_1_VERT_EXT 0xa1 219 #define XR_CURSOR_1_BASEADDR_LO 0xa2 220 #define XR_CURSOR_1_BASEADDR_HI 0xa3 221 #define XR_CURSOR_1_X_LO 0xa4 222 #define XR_CURSOR_1_X_HI 0xa5 223 #define XR_CURSOR_1_Y_LO 0xa6 224 #define XR_CURSOR_1_Y_HI 0xa7 225 226 #define XR_CURSOR_2_CTL 0xa8 227 #define XR_CURSOR_2_VERT_EXT 0xa9 228 #define XR_CURSOR_2_BASEADDR_LO 0xaa 229 #define XR_CURSOR_2_BASEADDR_HI 0xab 230 #define XR_CURSOR_2_X_LO 0xac 231 #define XR_CURSOR_2_X_HI 0xad 232 #define XR_CURSOR_2_Y_LO 0xae 233 #define XR_CURSOR_2_Y_HI 0xaf 234 235 /* reference clock is 14.31818MHz */ 236 #define CHIPS_REFCLOCK 14318180 237 238 #define XR_VCLOCK_0_M 0xc0 239 #define XR_VCLOCK_0_N 0xc1 240 #define XR_VCLOCK_0_MN_MSBS 0xc2 241 #define XR_VCLOCK_0_DIV_SELECT 0xc3 242 243 #define XR_VCLOCK_1_M 0xc4 244 #define XR_VCLOCK_1_N 0xc5 245 #define XR_VCLOCK_1_MN_MSBS 0xc6 246 #define XR_VCLOCK_1_DIV_SELECT 0xc7 247 248 #define XR_VCLOCK_2_M 0xc8 249 #define XR_VCLOCK_2_N 0xc9 250 #define XR_VCLOCK_2_MN_MSBS 0xca 251 #define XR_VCLOCK_2_DIV_SELECT 0xcb 252 253 #define XR_MEMCLOCK_M 0xcc 254 #define XR_MEMCLOCK_N 0xcd 255 #define XR_MEMCLOCK_DIV_SELECT 0xce 256 #define XR_CLOCK_CONFIG 0xcf 257 258 #define XR_MODULE_POWER_DOWN 0xd0 259 #define XR_DOWN_COUNTER 0xd2 260 261 #define XR_SOFTWARE_FLAG_0 0xe0 262 #define XR_SOFTWARE_FLAG_1 0xe1 263 #define XR_SOFTWARE_FLAG_2 0xe2 264 #define XR_SOFTWARE_FLAG_3 0xe3 265 #define XR_SOFTWARE_FLAG_4 0xe4 266 #define XR_SOFTWARE_FLAG_5 0xe5 267 #define XR_SOFTWARE_FLAG_6 0xe6 268 #define XR_SOFTWARE_FLAG_7 0xe7 269 270 #define XR_TEST_BLOCK_SELECT 0xf8 271 #define XR_TEST_CONTROL_PORT 0xf9 272 #define XR_TEST_DATA_PORT 0xfa 273 #define XR_SCAN_TEST_CONTROL_0 0xfb 274 #define XR_SCAN_TEST_CONTROL_1 0xfc 275 276 /* flat panel control registers, via CT_FP_* */ 277 #define FP_FEATURE 0x00 278 #define PANEL_EXISTS 0x01 279 #define POPUP_EXISTS 0x04 280 281 #define FP_CRT_FP_CONTROL 0x01 282 #define ENABLE_CRT 0x01 283 #define ENABLE_PANEL 0x02 284 285 #define FP_MODE_CONTROL 0x02 286 #define FP_DOT_CLOCK_SOURCE 0x03 287 #define FP_CLOCK_0 0x00 288 #define FP_CLOCK_1 0x04 289 #define FP_CLOCK_2 0x08 290 #define USE_VIDEO_CLOCK 0x00 291 #define USE_MEM_CLOCK 0x10 292 293 #define FP_POWER_SEQ_DELAY 0x04 294 /* 295 * upper 4 bits select power up delay in 3.4ms increments 296 * lower 4 bits select power down delay in 29ms increments 297 */ 298 299 #define FP_POWER_DOWN_CTL_1 0x05 300 /* the lower 3 bits select how many refresh cycles per scanline are preformed */ 301 #define PANEL_POWER_OFF 0x08 302 #define HOST_STANDBY 0x10 303 #define PANEL_TRISTATE 0x20 304 #define NO_SEFL_REFRESH 0x40 305 #define PANEL_INACTIVE 0x80 306 307 /* these bits are effective when the panel is powered down */ 308 #define FP_POWER_DOWN_CTL_0 0x06 309 #define FP_VGA_PALETTE_POWERDOWN 0x01 310 #define FP_VGA_PALETTE_ENABLE 0x02 311 #define FP_ENABLE_SYNC 0x04 312 313 #define FP_PIN_POLARITY 0x08 314 #define FP_DISPLAY_NEGATIVE 0x02 315 #define FP_HSYNC_NEGATIVE 0x04 316 #define FP_VSYNC_NEGATIVE 0x08 317 #define FP_TEXT_VIDEO_INVERT 0x10 318 #define FP_GRAPHICS_INVERT 0x20 319 #define CRT_HSYNC_NEGATIVE 0x40 320 #define CRT_VSYNC_NEGATIVE 0x80 321 322 #define FP_OUTPUT_DRIVE 0x0a 323 #define VL_THRESHOLD_5V 0x02 /* 3.3v otherwise */ 324 #define FP_DRIVE_HIGH 0x04 /* req. with 3.3v */ 325 #define BUS_INTERFACE_LOW 0x08 /* req. with 3.3v */ 326 #define MEM_DRIVE_HIGHER 0x10 327 #define MEM_C_DRIVE_HIGHER 0x20 328 #define SYNC_DRIVE_HIGHER 0x40 329 330 #define FP_PIN_CONTROL_1 0x0b 331 #define DISPLAY_ENABLE_ON_69 0x01 /* M signal otherwise */ 332 #define DISPLAY_ENABLE_ON_68 0x02 /* FP Hsync otherwise */ 333 #define COMPOSITE_SYNC_ON_65 0x04 /* separate otherwise */ 334 #define BACKLIGHT_ON_61 0x08 /* on 54 otherwise */ 335 #define GPIO_ON_154 0x10 336 #define SIMPLE_COMPOSITE_SYNC 0x20 337 #define MEM_C_TRISTATE 0x80 338 339 #define FP_PIN_CONTROL_2 0x0c 340 #define ACTI_ON_53 0x00 341 #define COMPOSITE_SYNC_ON_53 0x08 342 #define GPIO_IN_ON_53 0x10 343 #define GPIO_OUT_ON_53 0x18 344 #define ENABKL_ON_54 0x00 345 #define COMPOSITE_SYNC_ON_54 0x40 346 #define GPIO_IN_ON_54 0x80 347 #define GPIO_OUT_ON_54 0xc0 348 349 #define FP_ACTIVITY_CONTROL 0x0f 350 /* the lower 5 bits select a timeout in 28.1s increments */ 351 #define PANEL_OFF_ON_TIMEOUT 0x40 /* backlight off otherwise */ 352 #define ENABLE_ACTIVITY_TIMER 0x80 353 354 #define FP_PANEL_FORMAT_0 0x10 355 #define SINGLE_PANEL_SINGLE_DRIVE 0x00 356 #define DUAL_PANEL_DUAL_DRIVE 0x03 357 #define MONO_NTSC 0x00 358 #define MONO_EQUIV_WEIGHT 0x04 359 #define MONO_GREEN_ONLY 0x08 360 #define COLOUR_PANEL 0x0c 361 #define SHIFT_CLOCK_DIVIDER_MASK 0x70 362 363 #define FP_PANEL_FORMAT_1 0x11 364 365 #define FP_PANEL_FORMAT_2 0x12 366 #define FP_PANEL_FORMAT_3 0x13 367 368 #define FP_FRC_OPTION_SELECT 0x16 369 #define FP_POLYNOMIAL_FRC_CTL 0x17 370 371 #define FP_TEXTMODE_CONTROL 0x18 372 #define FP_BLINK_RATE_CONTROL 0x19 373 #define FP_FB_CONTROL 0x1a 374 375 #define FP_ACDCLK_CONTROL 0x1e 376 #define FP_DIAGNOSTIC 0x1f 377 378 #define FP_HSIZE_LSB 0x20 /* panel size - 1 */ 379 #define FP_HSYNC_START 0x21 /* value - 1 */ 380 #define FP_HSYNC_END 0x22 381 #define FP_HTOTAL_LSB 0x23 /* value - 5 */ 382 #define FP_HSYNC_DELAY_LSB 0x24 383 #define FP_HORZ_OVERFLOW_1 0x25 384 /* 385 * upper 4 bits are upper 4 bits of FP_HSYNC_START 386 * lower 4 bits are upper 4 bits of FP_HSIZE_LSB 387 */ 388 389 #define FP_HORZ_OVERFLOW_2 0x26 390 /* 391 * upper 4 bits are upper 4 bits of FP_HSYNC_DELAY_LSB 392 * lower 4 bits are upper 4 bits of FP_HTOTAL_LSB 393 */ 394 395 #define FP_HSYNC_WIDTH_DISABLE 0x27 396 /* lower 7 bits are HSYNC width - 1 */ 397 #define DELAY_DISABLE 0x80 398 399 #define FP_VSIZE_LSB 0x30 /* panel size - 1 */ 400 #define FP_VSYNC_START 0x31 /* value - 1 */ 401 #define FP_VSYNC_END 0x32 /* value - 1 */ 402 #define FP_VTOTAL_LSB 0x33 /* value - 2 */ 403 #define FP_VSYNC_DELAY_LSB 0x34 /* value - 1 */ 404 #define FP_VERT_OVERFLOW_1 0x35 405 /* 406 * upper 4 bits are upper 4 bits of FP_VSYNC_START 407 * lower 4 bits are upper 4 bits of FP_VSIZE_LSB 408 */ 409 410 #define FP_VERT_OVERFLOW_2 0x36 411 /* 412 * upper 4 bits are upper 4 bits of FP_VSYNC_DELAY_LSB 413 * lower 4 bits are upper 4 bits of FP_VTOTAL_LSB 414 */ 415 416 #define FP_VSYNC_DISABLE 0x37 417 #define FP_VSYNC_WIDTH_MASK 0x38 /* value - 1 */ 418 #define FP_VSYNC_IS_CRT_VSYNC 0x40 419 #define FP_VSYNC_DELAY_DISABLE 0x80 420 421 #define FP_HORZ_COMPENSATION 0x40 422 #define FP_VERT_COMPENSATION 0x41 423 #define FP_VERT_COMPENSATION2 0x48 424 425 #define FP_TEXT_VSTRETCH_0_MSB 0x49 426 #define FP_TEXT_VSTRETCH_0_LSB 0x4a 427 #define FP_TEXT_VSTRETCH_1_MSB 0x4b 428 #define FP_TEXT_VSTRETCH_1_LSB 0x4c 429 #define FP_TEXT_LINE_REPL 0x4d 430 #define FP_SEL_VSTRETCH_DISABLE 0x4e 431 432 433 434 #endif 435
Indexes created Sat Sep 20 22:09:52 GMT 2025