1 /* $NetBSD: dce_ipp.h,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef _DCE_IPP_H_ 29 #define _DCE_IPP_H_ 30 31 #include "ipp.h" 32 33 #define TO_DCE_IPP(ipp)\ 34 container_of(ipp, struct dce_ipp, base) 35 36 #define IPP_COMMON_REG_LIST_DCE_BASE(id) \ 37 SRI(CUR_UPDATE, DCP, id), \ 38 SRI(CUR_CONTROL, DCP, id), \ 39 SRI(CUR_POSITION, DCP, id), \ 40 SRI(CUR_HOT_SPOT, DCP, id), \ 41 SRI(CUR_COLOR1, DCP, id), \ 42 SRI(CUR_COLOR2, DCP, id), \ 43 SRI(CUR_SIZE, DCP, id), \ 44 SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \ 45 SRI(CUR_SURFACE_ADDRESS, DCP, id), \ 46 SRI(PRESCALE_GRPH_CONTROL, DCP, id), \ 47 SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \ 48 SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \ 49 SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \ 50 SRI(INPUT_GAMMA_CONTROL, DCP, id), \ 51 SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \ 52 SRI(DC_LUT_RW_MODE, DCP, id), \ 53 SRI(DC_LUT_CONTROL, DCP, id), \ 54 SRI(DC_LUT_RW_INDEX, DCP, id), \ 55 SRI(DC_LUT_SEQ_COLOR, DCP, id), \ 56 SRI(DEGAMMA_CONTROL, DCP, id) 57 58 #define IPP_DCE100_REG_LIST_DCE_BASE(id) \ 59 IPP_COMMON_REG_LIST_DCE_BASE(id), \ 60 SRI(DCFE_MEM_PWR_CTRL, CRTC, id) 61 62 #define IPP_DCE110_REG_LIST_DCE_BASE(id) \ 63 IPP_COMMON_REG_LIST_DCE_BASE(id), \ 64 SRI(DCFE_MEM_PWR_CTRL, DCFE, id) 65 66 #define IPP_SF(reg_name, field_name, post_fix)\ 67 .field_name = reg_name ## __ ## field_name ## post_fix 68 69 #define IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 70 IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ 71 IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \ 72 IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \ 73 IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ 74 IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ 75 IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \ 76 IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \ 77 IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ 78 IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ 79 IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \ 80 IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \ 81 IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \ 82 IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \ 83 IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \ 84 IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \ 85 IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \ 86 IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \ 87 IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ 88 IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ 89 IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ 90 IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \ 91 IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \ 92 IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \ 93 IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \ 94 IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ 95 IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ 96 IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ 97 IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ 98 IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ 99 IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ 100 IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \ 101 IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \ 102 IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \ 103 IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \ 104 IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ 105 IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ 106 IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) 107 108 #define IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 109 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 110 IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh) 111 112 #define IPP_DCE120_MASK_SH_LIST_SOC_BASE(mask_sh) \ 113 IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ 114 IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \ 115 IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \ 116 IPP_SF(DCP0_CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ 117 IPP_SF(DCP0_CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ 118 IPP_SF(DCP0_CUR_POSITION, CURSOR_X_POSITION, mask_sh), \ 119 IPP_SF(DCP0_CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \ 120 IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ 121 IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ 122 IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \ 123 IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \ 124 IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \ 125 IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \ 126 IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \ 127 IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \ 128 IPP_SF(DCP0_CUR_SIZE, CURSOR_WIDTH, mask_sh), \ 129 IPP_SF(DCP0_CUR_SIZE, CURSOR_HEIGHT, mask_sh), \ 130 IPP_SF(DCP0_CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ 131 IPP_SF(DCP0_CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ 132 IPP_SF(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ 133 IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \ 134 IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \ 135 IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \ 136 IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \ 137 IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ 138 IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ 139 IPP_SF(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ 140 IPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \ 141 IPP_SF(DCP0_DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ 142 IPP_SF(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ 143 IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ 144 IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \ 145 IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \ 146 IPP_SF(DCP0_DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \ 147 IPP_SF(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \ 148 IPP_SF(DCP0_DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ 149 IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ 150 IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) 151 152 #define IPP_REG_FIELD_LIST(type) \ 153 type CURSOR_UPDATE_LOCK; \ 154 type CURSOR_EN; \ 155 type CURSOR_X_POSITION; \ 156 type CURSOR_Y_POSITION; \ 157 type CURSOR_HOT_SPOT_X; \ 158 type CURSOR_HOT_SPOT_Y; \ 159 type CURSOR_MODE; \ 160 type CURSOR_2X_MAGNIFY; \ 161 type CUR_INV_TRANS_CLAMP; \ 162 type CUR_COLOR1_BLUE; \ 163 type CUR_COLOR1_GREEN; \ 164 type CUR_COLOR1_RED; \ 165 type CUR_COLOR2_BLUE; \ 166 type CUR_COLOR2_GREEN; \ 167 type CUR_COLOR2_RED; \ 168 type CURSOR_WIDTH; \ 169 type CURSOR_HEIGHT; \ 170 type CURSOR_SURFACE_ADDRESS_HIGH; \ 171 type CURSOR_SURFACE_ADDRESS; \ 172 type GRPH_PRESCALE_BYPASS; \ 173 type GRPH_PRESCALE_SCALE_R; \ 174 type GRPH_PRESCALE_BIAS_R; \ 175 type GRPH_PRESCALE_SCALE_G; \ 176 type GRPH_PRESCALE_BIAS_G; \ 177 type GRPH_PRESCALE_SCALE_B; \ 178 type GRPH_PRESCALE_BIAS_B; \ 179 type GRPH_INPUT_GAMMA_MODE; \ 180 type DCP_LUT_MEM_PWR_DIS; \ 181 type DC_LUT_WRITE_EN_MASK; \ 182 type DC_LUT_RW_MODE; \ 183 type DC_LUT_DATA_R_FORMAT; \ 184 type DC_LUT_DATA_G_FORMAT; \ 185 type DC_LUT_DATA_B_FORMAT; \ 186 type DC_LUT_RW_INDEX; \ 187 type DC_LUT_SEQ_COLOR; \ 188 type GRPH_DEGAMMA_MODE; \ 189 type CURSOR_DEGAMMA_MODE; \ 190 type CURSOR2_DEGAMMA_MODE 191 192 struct dce_ipp_shift { 193 IPP_REG_FIELD_LIST(uint8_t); 194 }; 195 196 struct dce_ipp_mask { 197 IPP_REG_FIELD_LIST(uint32_t); 198 }; 199 200 struct dce_ipp_registers { 201 uint32_t CUR_UPDATE; 202 uint32_t CUR_CONTROL; 203 uint32_t CUR_POSITION; 204 uint32_t CUR_HOT_SPOT; 205 uint32_t CUR_COLOR1; 206 uint32_t CUR_COLOR2; 207 uint32_t CUR_SIZE; 208 uint32_t CUR_SURFACE_ADDRESS_HIGH; 209 uint32_t CUR_SURFACE_ADDRESS; 210 uint32_t PRESCALE_GRPH_CONTROL; 211 uint32_t PRESCALE_VALUES_GRPH_R; 212 uint32_t PRESCALE_VALUES_GRPH_G; 213 uint32_t PRESCALE_VALUES_GRPH_B; 214 uint32_t INPUT_GAMMA_CONTROL; 215 uint32_t DCFE_MEM_PWR_CTRL; 216 uint32_t DC_LUT_WRITE_EN_MASK; 217 uint32_t DC_LUT_RW_MODE; 218 uint32_t DC_LUT_CONTROL; 219 uint32_t DC_LUT_RW_INDEX; 220 uint32_t DC_LUT_SEQ_COLOR; 221 uint32_t DEGAMMA_CONTROL; 222 }; 223 224 struct dce_ipp { 225 struct input_pixel_processor base; 226 const struct dce_ipp_registers *regs; 227 const struct dce_ipp_shift *ipp_shift; 228 const struct dce_ipp_mask *ipp_mask; 229 }; 230 231 void dce_ipp_construct(struct dce_ipp *ipp_dce, 232 struct dc_context *ctx, 233 int inst, 234 const struct dce_ipp_registers *regs, 235 const struct dce_ipp_shift *ipp_shift, 236 const struct dce_ipp_mask *ipp_mask); 237 238 void dce_ipp_destroy(struct input_pixel_processor **ipp); 239 240 #endif /* _DCE_IPP_H_ */ 241
Indexes created Sat Sep 20 22:09:52 GMT 2025