1 /* $NetBSD: rs600d.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __RS600D_H__ 31 #define __RS600D_H__ 32 33 /* Registers */ 34 #define R_000040_GEN_INT_CNTL 0x000040 35 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) 36 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) 37 #define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF 38 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) 39 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) 40 #define C_000040_GUI_IDLE_MASK 0xFFF7FFFF 41 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 42 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 43 #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF 44 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 45 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 46 #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF 47 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 48 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) 49 #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF 50 #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) 51 #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) 52 #define C_000040_I2C_INT_EN 0xFFFDFFFF 53 #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) 54 #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) 55 #define C_000040_GUI_IDLE 0xFFF7FFFF 56 #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) 57 #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) 58 #define C_000040_VIPH_INT_EN 0xFEFFFFFF 59 #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) 60 #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) 61 #define C_000040_SW_INT_EN 0xFDFFFFFF 62 #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) 63 #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) 64 #define C_000040_GEYSERVILLE 0xF7FFFFFF 65 #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) 66 #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) 67 #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF 68 #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) 69 #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) 70 #define C_000040_DVI_I2C_INT 0xDFFFFFFF 71 #define S_000040_GUIDMA(x) (((x) & 0x1) << 30) 72 #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) 73 #define C_000040_GUIDMA 0xBFFFFFFF 74 #define S_000040_VIDDMA(x) (((x) & 0x1) << 31) 75 #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) 76 #define C_000040_VIDDMA 0x7FFFFFFF 77 #define R_000044_GEN_INT_STATUS 0x000044 78 #define S_000044_DISPLAY_INT_STAT(x) (((x) & 0x1) << 0) 79 #define G_000044_DISPLAY_INT_STAT(x) (((x) >> 0) & 0x1) 80 #define C_000044_DISPLAY_INT_STAT 0xFFFFFFFE 81 #define S_000044_VGA_INT_STAT(x) (((x) & 0x1) << 1) 82 #define G_000044_VGA_INT_STAT(x) (((x) >> 1) & 0x1) 83 #define C_000044_VGA_INT_STAT 0xFFFFFFFD 84 #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) 85 #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) 86 #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF 87 #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) 88 #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) 89 #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF 90 #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) 91 #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) 92 #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF 93 #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) 94 #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) 95 #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF 96 #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) 97 #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) 98 #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF 99 #define S_000044_MC_PROBE_FAULT_STAT(x) (((x) & 0x1) << 16) 100 #define G_000044_MC_PROBE_FAULT_STAT(x) (((x) >> 16) & 0x1) 101 #define C_000044_MC_PROBE_FAULT_STAT 0xFFFEFFFF 102 #define S_000044_I2C_INT(x) (((x) & 0x1) << 17) 103 #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) 104 #define C_000044_I2C_INT 0xFFFDFFFF 105 #define S_000044_SCRATCH_INT_STAT(x) (((x) & 0x1) << 18) 106 #define G_000044_SCRATCH_INT_STAT(x) (((x) >> 18) & 0x1) 107 #define C_000044_SCRATCH_INT_STAT 0xFFFBFFFF 108 #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) 109 #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) 110 #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF 111 #define S_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) & 0x1) << 20) 112 #define G_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) >> 20) & 0x1) 113 #define C_000044_ATI_OVERDRIVE_INT_STAT 0xFFEFFFFF 114 #define S_000044_MC_PROTECTION_FAULT_STAT(x) (((x) & 0x1) << 21) 115 #define G_000044_MC_PROTECTION_FAULT_STAT(x) (((x) >> 21) & 0x1) 116 #define C_000044_MC_PROTECTION_FAULT_STAT 0xFFDFFFFF 117 #define S_000044_RBBM_READ_INT_STAT(x) (((x) & 0x1) << 22) 118 #define G_000044_RBBM_READ_INT_STAT(x) (((x) >> 22) & 0x1) 119 #define C_000044_RBBM_READ_INT_STAT 0xFFBFFFFF 120 #define S_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) & 0x1) << 23) 121 #define G_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) >> 23) & 0x1) 122 #define C_000044_CB_CONTEXT_SWITCH_STAT 0xFF7FFFFF 123 #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) 124 #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) 125 #define C_000044_VIPH_INT 0xFEFFFFFF 126 #define S_000044_SW_INT(x) (((x) & 0x1) << 25) 127 #define G_000044_SW_INT(x) (((x) >> 25) & 0x1) 128 #define C_000044_SW_INT 0xFDFFFFFF 129 #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) 130 #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) 131 #define C_000044_SW_INT_SET 0xFBFFFFFF 132 #define S_000044_IDCT_INT_STAT(x) (((x) & 0x1) << 27) 133 #define G_000044_IDCT_INT_STAT(x) (((x) >> 27) & 0x1) 134 #define C_000044_IDCT_INT_STAT 0xF7FFFFFF 135 #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) 136 #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) 137 #define C_000044_GUIDMA_STAT 0xBFFFFFFF 138 #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) 139 #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) 140 #define C_000044_VIDDMA_STAT 0x7FFFFFFF 141 #define R_00004C_BUS_CNTL 0x00004C 142 #define S_00004C_BUS_MASTER_DIS(x) (((x) & 0x1) << 14) 143 #define G_00004C_BUS_MASTER_DIS(x) (((x) >> 14) & 0x1) 144 #define C_00004C_BUS_MASTER_DIS 0xFFFFBFFF 145 #define S_00004C_BUS_MSI_REARM(x) (((x) & 0x1) << 20) 146 #define G_00004C_BUS_MSI_REARM(x) (((x) >> 20) & 0x1) 147 #define C_00004C_BUS_MSI_REARM 0xFFEFFFFF 148 #define R_000070_MC_IND_INDEX 0x000070 149 #define S_000070_MC_IND_ADDR(x) (((x) & 0xFFFF) << 0) 150 #define G_000070_MC_IND_ADDR(x) (((x) >> 0) & 0xFFFF) 151 #define C_000070_MC_IND_ADDR 0xFFFF0000 152 #define S_000070_MC_IND_SEQ_RBS_0(x) (((x) & 0x1) << 16) 153 #define G_000070_MC_IND_SEQ_RBS_0(x) (((x) >> 16) & 0x1) 154 #define C_000070_MC_IND_SEQ_RBS_0 0xFFFEFFFF 155 #define S_000070_MC_IND_SEQ_RBS_1(x) (((x) & 0x1) << 17) 156 #define G_000070_MC_IND_SEQ_RBS_1(x) (((x) >> 17) & 0x1) 157 #define C_000070_MC_IND_SEQ_RBS_1 0xFFFDFFFF 158 #define S_000070_MC_IND_SEQ_RBS_2(x) (((x) & 0x1) << 18) 159 #define G_000070_MC_IND_SEQ_RBS_2(x) (((x) >> 18) & 0x1) 160 #define C_000070_MC_IND_SEQ_RBS_2 0xFFFBFFFF 161 #define S_000070_MC_IND_SEQ_RBS_3(x) (((x) & 0x1) << 19) 162 #define G_000070_MC_IND_SEQ_RBS_3(x) (((x) >> 19) & 0x1) 163 #define C_000070_MC_IND_SEQ_RBS_3 0xFFF7FFFF 164 #define S_000070_MC_IND_AIC_RBS(x) (((x) & 0x1) << 20) 165 #define G_000070_MC_IND_AIC_RBS(x) (((x) >> 20) & 0x1) 166 #define C_000070_MC_IND_AIC_RBS 0xFFEFFFFF 167 #define S_000070_MC_IND_CITF_ARB0(x) (((x) & 0x1) << 21) 168 #define G_000070_MC_IND_CITF_ARB0(x) (((x) >> 21) & 0x1) 169 #define C_000070_MC_IND_CITF_ARB0 0xFFDFFFFF 170 #define S_000070_MC_IND_CITF_ARB1(x) (((x) & 0x1) << 22) 171 #define G_000070_MC_IND_CITF_ARB1(x) (((x) >> 22) & 0x1) 172 #define C_000070_MC_IND_CITF_ARB1 0xFFBFFFFF 173 #define S_000070_MC_IND_WR_EN(x) (((x) & 0x1) << 23) 174 #define G_000070_MC_IND_WR_EN(x) (((x) >> 23) & 0x1) 175 #define C_000070_MC_IND_WR_EN 0xFF7FFFFF 176 #define S_000070_MC_IND_RD_INV(x) (((x) & 0x1) << 24) 177 #define G_000070_MC_IND_RD_INV(x) (((x) >> 24) & 0x1) 178 #define C_000070_MC_IND_RD_INV 0xFEFFFFFF 179 #define R_000074_MC_IND_DATA 0x000074 180 #define S_000074_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) 181 #define G_000074_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) 182 #define C_000074_MC_IND_DATA 0x00000000 183 #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 184 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 185 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 186 #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 187 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 188 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 189 #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 190 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) 191 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) 192 #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB 193 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 194 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 195 #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 196 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 197 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 198 #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 199 #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 200 #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 201 #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 202 #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 203 #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 204 #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 205 #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 206 #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 207 #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 208 #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 209 #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 210 #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 211 #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 212 #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 213 #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 214 #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 215 #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 216 #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 217 #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 218 #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 219 #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 220 #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 221 #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 222 #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 223 #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) 224 #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) 225 #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF 226 #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) 227 #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) 228 #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF 229 #define R_000134_HDP_FB_LOCATION 0x000134 230 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) 231 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) 232 #define C_000134_HDP_FB_START 0xFFFF0000 233 #define R_0007C0_CP_STAT 0x0007C0 234 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 235 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 236 #define C_0007C0_MRU_BUSY 0xFFFFFFFE 237 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 238 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 239 #define C_0007C0_MWU_BUSY 0xFFFFFFFD 240 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 241 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 242 #define C_0007C0_RSIU_BUSY 0xFFFFFFFB 243 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 244 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 245 #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 246 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 247 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 248 #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 249 #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 250 #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 251 #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 252 #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 253 #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 254 #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 255 #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 256 #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 257 #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 258 #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 259 #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 260 #define C_0007C0_CSI_BUSY 0xFFFFDFFF 261 #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) 262 #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) 263 #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF 264 #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) 265 #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) 266 #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF 267 #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 268 #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 269 #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 270 #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 271 #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 272 #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 273 #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 274 #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 275 #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 276 #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 277 #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 278 #define C_0007C0_CP_BUSY 0x7FFFFFFF 279 #define R_000E40_RBBM_STATUS 0x000E40 280 #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 281 #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 282 #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 283 #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 284 #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 285 #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 286 #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 287 #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 288 #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 289 #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 290 #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 291 #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 292 #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 293 #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 294 #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 295 #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 296 #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 297 #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 298 #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 299 #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 300 #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 301 #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 302 #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 303 #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 304 #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 305 #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 306 #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 307 #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 308 #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 309 #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 310 #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 311 #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 312 #define C_000E40_E2_BUSY 0xFFFDFFFF 313 #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 314 #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 315 #define C_000E40_RB2D_BUSY 0xFFFBFFFF 316 #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 317 #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 318 #define C_000E40_RB3D_BUSY 0xFFF7FFFF 319 #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) 320 #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) 321 #define C_000E40_VAP_BUSY 0xFFEFFFFF 322 #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 323 #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 324 #define C_000E40_RE_BUSY 0xFFDFFFFF 325 #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 326 #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 327 #define C_000E40_TAM_BUSY 0xFFBFFFFF 328 #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 329 #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 330 #define C_000E40_TDM_BUSY 0xFF7FFFFF 331 #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 332 #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 333 #define C_000E40_PB_BUSY 0xFEFFFFFF 334 #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) 335 #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) 336 #define C_000E40_TIM_BUSY 0xFDFFFFFF 337 #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) 338 #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) 339 #define C_000E40_GA_BUSY 0xFBFFFFFF 340 #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) 341 #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) 342 #define C_000E40_CBA2D_BUSY 0xF7FFFFFF 343 #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 344 #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 345 #define C_000E40_GUI_ACTIVE 0x7FFFFFFF 346 #define R_0060A4_D1CRTC_STATUS_FRAME_COUNT 0x0060A4 347 #define S_0060A4_D1CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) 348 #define G_0060A4_D1CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) 349 #define C_0060A4_D1CRTC_FRAME_COUNT 0xFF000000 350 #define R_006534_D1MODE_VBLANK_STATUS 0x006534 351 #define S_006534_D1MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) 352 #define G_006534_D1MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) 353 #define C_006534_D1MODE_VBLANK_OCCURRED 0xFFFFFFFE 354 #define S_006534_D1MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) 355 #define G_006534_D1MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) 356 #define C_006534_D1MODE_VBLANK_ACK 0xFFFFFFEF 357 #define S_006534_D1MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) 358 #define G_006534_D1MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) 359 #define C_006534_D1MODE_VBLANK_STAT 0xFFFFEFFF 360 #define S_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) 361 #define G_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) 362 #define C_006534_D1MODE_VBLANK_INTERRUPT 0xFFFEFFFF 363 #define R_006540_DxMODE_INT_MASK 0x006540 364 #define S_006540_D1MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 0) 365 #define G_006540_D1MODE_VBLANK_INT_MASK(x) (((x) >> 0) & 0x1) 366 #define C_006540_D1MODE_VBLANK_INT_MASK 0xFFFFFFFE 367 #define S_006540_D1MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 4) 368 #define G_006540_D1MODE_VLINE_INT_MASK(x) (((x) >> 4) & 0x1) 369 #define C_006540_D1MODE_VLINE_INT_MASK 0xFFFFFFEF 370 #define S_006540_D2MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 8) 371 #define G_006540_D2MODE_VBLANK_INT_MASK(x) (((x) >> 8) & 0x1) 372 #define C_006540_D2MODE_VBLANK_INT_MASK 0xFFFFFEFF 373 #define S_006540_D2MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 12) 374 #define G_006540_D2MODE_VLINE_INT_MASK(x) (((x) >> 12) & 0x1) 375 #define C_006540_D2MODE_VLINE_INT_MASK 0xFFFFEFFF 376 #define S_006540_D1MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 30) 377 #define G_006540_D1MODE_VBLANK_CP_SEL(x) (((x) >> 30) & 0x1) 378 #define C_006540_D1MODE_VBLANK_CP_SEL 0xBFFFFFFF 379 #define S_006540_D2MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 31) 380 #define G_006540_D2MODE_VBLANK_CP_SEL(x) (((x) >> 31) & 0x1) 381 #define C_006540_D2MODE_VBLANK_CP_SEL 0x7FFFFFFF 382 #define R_0068A4_D2CRTC_STATUS_FRAME_COUNT 0x0068A4 383 #define S_0068A4_D2CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) 384 #define G_0068A4_D2CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) 385 #define C_0068A4_D2CRTC_FRAME_COUNT 0xFF000000 386 #define R_006D34_D2MODE_VBLANK_STATUS 0x006D34 387 #define S_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) 388 #define G_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) 389 #define C_006D34_D2MODE_VBLANK_OCCURRED 0xFFFFFFFE 390 #define S_006D34_D2MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) 391 #define G_006D34_D2MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) 392 #define C_006D34_D2MODE_VBLANK_ACK 0xFFFFFFEF 393 #define S_006D34_D2MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) 394 #define G_006D34_D2MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) 395 #define C_006D34_D2MODE_VBLANK_STAT 0xFFFFEFFF 396 #define S_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) 397 #define G_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) 398 #define C_006D34_D2MODE_VBLANK_INTERRUPT 0xFFFEFFFF 399 #define R_007EDC_DISP_INTERRUPT_STATUS 0x007EDC 400 #define S_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) & 0x1) << 4) 401 #define G_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) >> 4) & 0x1) 402 #define C_007EDC_LB_D1_VBLANK_INTERRUPT 0xFFFFFFEF 403 #define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5) 404 #define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1) 405 #define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF 406 #define S_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 16) 407 #define G_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) >> 16) & 0x1) 408 #define C_007EDC_DACA_AUTODETECT_INTERRUPT 0xFFFEFFFF 409 #define S_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 17) 410 #define G_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) >> 17) & 0x1) 411 #define C_007EDC_DACB_AUTODETECT_INTERRUPT 0xFFFDFFFF 412 #define S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) & 0x1) << 18) 413 #define G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) >> 18) & 0x1) 414 #define C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT 0xFFFBFFFF 415 #define S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) & 0x1) << 19) 416 #define G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) >> 19) & 0x1) 417 #define C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT 0xFFF7FFFF 418 #define R_007828_DACA_AUTODETECT_CONTROL 0x007828 419 #define S_007828_DACA_AUTODETECT_MODE(x) (((x) & 0x3) << 0) 420 #define G_007828_DACA_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) 421 #define C_007828_DACA_AUTODETECT_MODE 0xFFFFFFFC 422 #define S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) 423 #define G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) 424 #define C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF 425 #define S_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) 426 #define G_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) 427 #define C_007828_DACA_AUTODETECT_CHECK_MASK 0xFFFCFFFF 428 #define R_007838_DACA_AUTODETECT_INT_CONTROL 0x007838 429 #define S_007838_DACA_AUTODETECT_ACK(x) (((x) & 0x1) << 0) 430 #define C_007838_DACA_DACA_AUTODETECT_ACK 0xFFFFFFFE 431 #define S_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) 432 #define G_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) 433 #define C_007838_DACA_AUTODETECT_INT_ENABLE 0xFFFCFFFF 434 #define R_007A28_DACB_AUTODETECT_CONTROL 0x007A28 435 #define S_007A28_DACB_AUTODETECT_MODE(x) (((x) & 0x3) << 0) 436 #define G_007A28_DACB_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) 437 #define C_007A28_DACB_AUTODETECT_MODE 0xFFFFFFFC 438 #define S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) 439 #define G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) 440 #define C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF 441 #define S_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) 442 #define G_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) 443 #define C_007A28_DACB_AUTODETECT_CHECK_MASK 0xFFFCFFFF 444 #define R_007A38_DACB_AUTODETECT_INT_CONTROL 0x007A38 445 #define S_007A38_DACB_AUTODETECT_ACK(x) (((x) & 0x1) << 0) 446 #define C_007A38_DACB_DACA_AUTODETECT_ACK 0xFFFFFFFE 447 #define S_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) 448 #define G_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) 449 #define C_007A38_DACB_AUTODETECT_INT_ENABLE 0xFFFCFFFF 450 #define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL 0x007D00 451 #define S_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) & 0x1) << 0) 452 #define G_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) >> 0) & 0x1) 453 #define C_007D00_DC_HOT_PLUG_DETECT1_EN 0xFFFFFFFE 454 #define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0x007D04 455 #define S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) & 0x1) << 0) 456 #define G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) >> 0) & 0x1) 457 #define C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0xFFFFFFFE 458 #define S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) & 0x1) << 1) 459 #define G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) >> 1) & 0x1) 460 #define C_007D04_DC_HOT_PLUG_DETECT1_SENSE 0xFFFFFFFD 461 #define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL 0x007D08 462 #define S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x) (((x) & 0x1) << 0) 463 #define C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK 0xFFFFFFFE 464 #define S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8) 465 #define G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1) 466 #define C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY 0xFFFFFEFF 467 #define S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) & 0x1) << 16) 468 #define G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) >> 16) & 0x1) 469 #define C_007D08_DC_HOT_PLUG_DETECT1_INT_EN 0xFFFEFFFF 470 #define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL 0x007D10 471 #define S_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) & 0x1) << 0) 472 #define G_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) >> 0) & 0x1) 473 #define C_007D10_DC_HOT_PLUG_DETECT2_EN 0xFFFFFFFE 474 #define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0x007D14 475 #define S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) & 0x1) << 0) 476 #define G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) >> 0) & 0x1) 477 #define C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0xFFFFFFFE 478 #define S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) & 0x1) << 1) 479 #define G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) >> 1) & 0x1) 480 #define C_007D14_DC_HOT_PLUG_DETECT2_SENSE 0xFFFFFFFD 481 #define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL 0x007D18 482 #define S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x) (((x) & 0x1) << 0) 483 #define C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK 0xFFFFFFFE 484 #define S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8) 485 #define G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1) 486 #define C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY 0xFFFFFEFF 487 #define S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) & 0x1) << 16) 488 #define G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) >> 16) & 0x1) 489 #define C_007D18_DC_HOT_PLUG_DETECT2_INT_EN 0xFFFEFFFF 490 #define R_007404_HDMI0_STATUS 0x007404 491 #define S_007404_HDMI0_AZ_FORMAT_WTRIG(x) (((x) & 0x1) << 28) 492 #define G_007404_HDMI0_AZ_FORMAT_WTRIG(x) (((x) >> 28) & 0x1) 493 #define C_007404_HDMI0_AZ_FORMAT_WTRIG 0xEFFFFFFF 494 #define S_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x) (((x) & 0x1) << 29) 495 #define G_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x) (((x) >> 29) & 0x1) 496 #define C_007404_HDMI0_AZ_FORMAT_WTRIG_INT 0xDFFFFFFF 497 #define R_007408_HDMI0_AUDIO_PACKET_CONTROL 0x007408 498 #define S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x) (((x) & 0x1) << 28) 499 #define G_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x) (((x) >> 28) & 0x1) 500 #define C_007408_HDMI0_AZ_FORMAT_WTRIG_MASK 0xEFFFFFFF 501 #define S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x) (((x) & 0x1) << 29) 502 #define G_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x) (((x) >> 29) & 0x1) 503 #define C_007408_HDMI0_AZ_FORMAT_WTRIG_ACK 0xDFFFFFFF 504 505 /* MC registers */ 506 #define R_000000_MC_STATUS 0x000000 507 #define S_000000_MC_IDLE(x) (((x) & 0x1) << 0) 508 #define G_000000_MC_IDLE(x) (((x) >> 0) & 0x1) 509 #define C_000000_MC_IDLE 0xFFFFFFFE 510 #define R_000004_MC_FB_LOCATION 0x000004 511 #define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0) 512 #define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 513 #define C_000004_MC_FB_START 0xFFFF0000 514 #define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 515 #define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 516 #define C_000004_MC_FB_TOP 0x0000FFFF 517 #define R_000005_MC_AGP_LOCATION 0x000005 518 #define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 519 #define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 520 #define C_000005_MC_AGP_START 0xFFFF0000 521 #define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 522 #define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 523 #define C_000005_MC_AGP_TOP 0x0000FFFF 524 #define R_000006_AGP_BASE 0x000006 525 #define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 526 #define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 527 #define C_000006_AGP_BASE_ADDR 0x00000000 528 #define R_000007_AGP_BASE_2 0x000007 529 #define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) 530 #define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) 531 #define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0 532 #define R_000009_MC_CNTL1 0x000009 533 #define S_000009_ENABLE_PAGE_TABLES(x) (((x) & 0x1) << 26) 534 #define G_000009_ENABLE_PAGE_TABLES(x) (((x) >> 26) & 0x1) 535 #define C_000009_ENABLE_PAGE_TABLES 0xFBFFFFFF 536 /* FIXME don't know the various field size need feedback from AMD */ 537 #define R_000100_MC_PT0_CNTL 0x000100 538 #define S_000100_ENABLE_PT(x) (((x) & 0x1) << 0) 539 #define G_000100_ENABLE_PT(x) (((x) >> 0) & 0x1) 540 #define C_000100_ENABLE_PT 0xFFFFFFFE 541 #define S_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) & 0x7) << 15) 542 #define G_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) >> 15) & 0x7) 543 #define C_000100_EFFECTIVE_L2_CACHE_SIZE 0xFFFC7FFF 544 #define S_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 0x7) << 21) 545 #define G_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) >> 21) & 0x7) 546 #define C_000100_EFFECTIVE_L2_QUEUE_SIZE 0xFF1FFFFF 547 #define S_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) & 0x1) << 28) 548 #define G_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) >> 28) & 0x1) 549 #define C_000100_INVALIDATE_ALL_L1_TLBS 0xEFFFFFFF 550 #define S_000100_INVALIDATE_L2_CACHE(x) (((x) & 0x1) << 29) 551 #define G_000100_INVALIDATE_L2_CACHE(x) (((x) >> 29) & 0x1) 552 #define C_000100_INVALIDATE_L2_CACHE 0xDFFFFFFF 553 #define R_000102_MC_PT0_CONTEXT0_CNTL 0x000102 554 #define S_000102_ENABLE_PAGE_TABLE(x) (((x) & 0x1) << 0) 555 #define G_000102_ENABLE_PAGE_TABLE(x) (((x) >> 0) & 0x1) 556 #define C_000102_ENABLE_PAGE_TABLE 0xFFFFFFFE 557 #define S_000102_PAGE_TABLE_DEPTH(x) (((x) & 0x3) << 1) 558 #define G_000102_PAGE_TABLE_DEPTH(x) (((x) >> 1) & 0x3) 559 #define C_000102_PAGE_TABLE_DEPTH 0xFFFFFFF9 560 #define V_000102_PAGE_TABLE_FLAT 0 561 /* R600 documentation suggest that this should be a number of pages */ 562 #define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x000112 563 #define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x000114 564 #define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x00011C 565 #define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x00012C 566 #define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x00013C 567 #define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x00014C 568 #define R_00016C_MC_PT0_CLIENT0_CNTL 0x00016C 569 #define S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0) 570 #define G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1) 571 #define C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFE 572 #define S_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 1) 573 #define G_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 1) & 0x1) 574 #define C_00016C_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFD 575 #define S_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) & 0x3) << 8) 576 #define G_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) >> 8) & 0x3) 577 #define C_00016C_SYSTEM_ACCESS_MODE_MASK 0xFFFFFCFF 578 #define V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY 0 579 #define V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP 1 580 #define V_00016C_SYSTEM_ACCESS_MODE_IN_SYS 2 581 #define V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS 3 582 #define S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) & 0x1) << 10) 583 #define G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) >> 10) & 0x1) 584 #define C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS 0xFFFFFBFF 585 #define V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH 0 586 #define V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1 587 #define S_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) & 0x7) << 11) 588 #define G_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) >> 11) & 0x7) 589 #define C_00016C_EFFECTIVE_L1_CACHE_SIZE 0xFFFFC7FF 590 #define S_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) & 0x1) << 14) 591 #define G_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) >> 14) & 0x1) 592 #define C_00016C_ENABLE_FRAGMENT_PROCESSING 0xFFFFBFFF 593 #define S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 0x7) << 15) 594 #define G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) >> 15) & 0x7) 595 #define C_00016C_EFFECTIVE_L1_QUEUE_SIZE 0xFFFC7FFF 596 #define S_00016C_INVALIDATE_L1_TLB(x) (((x) & 0x1) << 20) 597 #define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1) 598 #define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF 599 600 #define R_006548_D1MODE_PRIORITY_A_CNT 0x006548 601 #define S_006548_D1MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0) 602 #define G_006548_D1MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF) 603 #define C_006548_D1MODE_PRIORITY_MARK_A 0xFFFF8000 604 #define S_006548_D1MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) 605 #define G_006548_D1MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) 606 #define C_006548_D1MODE_PRIORITY_A_OFF 0xFFFEFFFF 607 #define S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20) 608 #define G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1) 609 #define C_006548_D1MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF 610 #define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) 611 #define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) 612 #define C_006548_D1MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF 613 #define R_00654C_D1MODE_PRIORITY_B_CNT 0x00654C 614 #define S_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0) 615 #define G_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF) 616 #define C_00654C_D1MODE_PRIORITY_MARK_B 0xFFFF8000 617 #define S_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16) 618 #define G_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1) 619 #define C_00654C_D1MODE_PRIORITY_B_OFF 0xFFFEFFFF 620 #define S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20) 621 #define G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1) 622 #define C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF 623 #define S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24) 624 #define G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) 625 #define C_00654C_D1MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF 626 #define R_006D48_D2MODE_PRIORITY_A_CNT 0x006D48 627 #define S_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0) 628 #define G_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF) 629 #define C_006D48_D2MODE_PRIORITY_MARK_A 0xFFFF8000 630 #define S_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) 631 #define G_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) 632 #define C_006D48_D2MODE_PRIORITY_A_OFF 0xFFFEFFFF 633 #define S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20) 634 #define G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1) 635 #define C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF 636 #define S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) 637 #define G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) 638 #define C_006D48_D2MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF 639 #define R_006D4C_D2MODE_PRIORITY_B_CNT 0x006D4C 640 #define S_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0) 641 #define G_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF) 642 #define C_006D4C_D2MODE_PRIORITY_MARK_B 0xFFFF8000 643 #define S_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16) 644 #define G_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1) 645 #define C_006D4C_D2MODE_PRIORITY_B_OFF 0xFFFEFFFF 646 #define S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20) 647 #define G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1) 648 #define C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF 649 #define S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24) 650 #define G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) 651 #define C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF 652 653 /* PLL regs */ 654 #define GENERAL_PWRMGT 0x8 655 #define GLOBAL_PWRMGT_EN (1 << 0) 656 #define MOBILE_SU (1 << 2) 657 #define DYN_PWRMGT_SCLK_LENGTH 0xc 658 #define NORMAL_POWER_SCLK_HILEN(x) ((x) << 0) 659 #define NORMAL_POWER_SCLK_LOLEN(x) ((x) << 4) 660 #define REDUCED_POWER_SCLK_HILEN(x) ((x) << 8) 661 #define REDUCED_POWER_SCLK_LOLEN(x) ((x) << 12) 662 #define POWER_D1_SCLK_HILEN(x) ((x) << 16) 663 #define POWER_D1_SCLK_LOLEN(x) ((x) << 20) 664 #define STATIC_SCREEN_HILEN(x) ((x) << 24) 665 #define STATIC_SCREEN_LOLEN(x) ((x) << 28) 666 #define DYN_SCLK_VOL_CNTL 0xe 667 #define IO_CG_VOLTAGE_DROP (1 << 0) 668 #define VOLTAGE_DROP_SYNC (1 << 2) 669 #define VOLTAGE_DELAY_SEL(x) ((x) << 3) 670 #define HDP_DYN_CNTL 0x10 671 #define HDP_FORCEON (1 << 0) 672 #define MC_HOST_DYN_CNTL 0x1e 673 #define MC_HOST_FORCEON (1 << 0) 674 #define DYN_BACKBIAS_CNTL 0x29 675 #define IO_CG_BACKBIAS_EN (1 << 0) 676 677 /* mmreg */ 678 #define DOUT_POWER_MANAGEMENT_CNTL 0x7ee0 679 #define PWRDN_WAIT_BUSY_OFF (1 << 0) 680 #define PWRDN_WAIT_PWRSEQ_OFF (1 << 4) 681 #define PWRDN_WAIT_PPLL_OFF (1 << 8) 682 #define PWRUP_WAIT_PPLL_ON (1 << 12) 683 #define PWRUP_WAIT_MEM_INIT_DONE (1 << 16) 684 #define PM_ASSERT_RESET (1 << 20) 685 #define PM_PWRDN_PPLL (1 << 24) 686 687 #endif 688
Indexes created Sat Sep 20 22:09:52 GMT 2025