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    Searched defs:Cand (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNMinRegStrategy.cpp 123 auto &Cand = *I++;
124 RQ.remove(Cand);
125 RQ.push_front(Cand);
GCNSchedStrategy.cpp 57 void GCNMaxOccupancySchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,
63 Cand.SU = SU;
64 Cand.AtTop = AtTop;
108 Cand.RPDelta.Excess = PressureChange(AMDGPU::RegisterPressureSets::VGPR_32);
109 Cand.RPDelta.Excess.setUnitInc(NewVGPRPressure - VGPRExcessLimit);
114 Cand.RPDelta.Excess = PressureChange(AMDGPU::RegisterPressureSets::SReg_32);
115 Cand.RPDelta.Excess.setUnitInc(NewSGPRPressure - SGPRExcessLimit);
129 Cand.RPDelta.CriticalMax =
131 Cand.RPDelta.CriticalMax.setUnitInc(SGPRDelta);
133 Cand.RPDelta.CriticalMax
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SIMachineScheduler.cpp 142 SISchedulerCandidate &Cand,
149 if (Cand.Reason > Reason)
150 Cand.Reason = Reason;
153 Cand.setRepeat(Reason);
159 SISchedulerCandidate &Cand,
166 if (Cand.Reason > Reason)
167 Cand.Reason = Reason;
170 Cand.setRepeat(Reason);
184 void SIScheduleBlock::traceCandidate(const SISchedCandidate &Cand) {
186 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason)
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  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
ConstantHoisting.cpp 384 ConstPtrUnionType Cand = ConstInt;
385 std::tie(Itr, Inserted) = ConstCandMap.insert(std::make_pair(Cand, 0));
434 ConstPtrUnionType Cand = ConstExpr;
435 std::tie(Itr, Inserted) = ConstCandMap.insert(std::make_pair(Cand, 0));
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/
PartialInlining.cpp 688 BasicBlock *Cand = OutliningInfo->NonReturnBlock;
689 if (succ_size(Cand) != 2)
692 if (HasNonEntryPred(Cand))
695 BasicBlock *Succ1 = *succ_begin(Cand);
696 BasicBlock *Succ2 = *(succ_begin(Cand) + 1);
703 if (NonReturnBlock->getSinglePredecessor() != Cand)
707 OutliningInfo->Entries.push_back(Cand);
709 OutliningInfo->ReturnBlockPreds.push_back(Cand);
710 Entries.insert(Cand);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegAllocGreedy.cpp 458 bool growRegion(GlobalSplitCandidate &Cand);
459 bool splitCanCauseEvictionChain(Register Evictee, GlobalSplitCandidate &Cand,
463 GlobalSplitCandidate &Cand, unsigned BBNumber,
1355 bool RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
1358 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
1388 if (Cand.PhysReg) {
1389 if (!addThroughConstraints(Cand.Intf, NewBlocks))
1411 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
1417 Cand.reset(IntfCache, MCRegister::NoRegister);
1423 SpillPlacer->prepare(Cand.LiveBundles)
    [all...]
MachineScheduler.cpp 2766 void GenericSchedulerBase::traceCandidate(const SchedCandidate &Cand) {
2770 switch (Cand.Reason) {
2774 P = Cand.RPDelta.Excess;
2777 P = Cand.RPDelta.CriticalMax;
2780 P = Cand.RPDelta.CurrentMax;
2783 ResIdx = Cand.Policy.ReduceResIdx;
2786 ResIdx = Cand.Policy.DemandResIdx;
2789 Latency = Cand.SU->getDepth();
2792 Latency = Cand.SU->getHeight();
2795 Latency = Cand.SU->getHeight()
    [all...]
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.cpp 479 CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]);
481 if (Cand == this || getSubRegIndex(Cand))
483 // Check if each component of Cand is already a sub-register.
484 assert(!Cand->ExplicitSubRegs.empty() &&
486 if (Cand->ExplicitSubRegs.size() == 1)
491 assert(Cand->ExplicitSubRegs[0] == SubReg && "LeadingSuperRegs correct");
493 for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) {
505 // There is nothing to do if some Cand sub-register is not part of this
510 // Each part of Cand is a sub-register of this. Make the full Cand als
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