| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64GlobalISelUtils.cpp | 99 const CmpInst::Predicate P, AArch64CC::CondCode &CondCode,
100 AArch64CC::CondCode &CondCode2) {
106 CondCode = AArch64CC::EQ;
109 CondCode = AArch64CC::GT;
112 CondCode = AArch64CC::GE;
115 CondCode = AArch64CC::MI;
118 CondCode = AArch64CC::LS;
121 CondCode = AArch64CC::MI;
125 CondCode = AArch64CC::VC
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiCondCode.h | 10 enum CondCode {
34 inline static StringRef lanaiCondCodeToString(LPCC::CondCode CC) {
73 inline static CondCode suffixToLanaiCondCode(StringRef S) {
74 return StringSwitch<CondCode>(S)
|
| LanaiInstrInfo.cpp | 123 static LPCC::CondCode getOppositeCondition(LPCC::CondCode CC) {
351 SmallVector<std::pair<MachineOperand *, LPCC::CondCode>, 4>
371 LPCC::CondCode CC;
372 CC = (LPCC::CondCode)Instr.getOperand(IO - 1).getImm();
375 LPCC::CondCode NewCC = getOppositeCondition(CC);
522 unsigned CondCode = MI.getOperand(3).getImm();
524 NewMI.addImm(getOppositeCondition(LPCC::CondCode(CondCode)));
526 NewMI.addImm(CondCode);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/MCTargetDesc/ |
| ARCInfo.h | 24 enum CondCode {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kInstrInfo.h | 34 enum CondCode {
58 static inline M68k::CondCode GetOppositeBranchCondition(M68k::CondCode CC) {
97 static inline unsigned GetCondBranchFromCond(M68k::CondCode CC) {
132 static inline M68k::CondCode GetCondFromBranchOpc(unsigned Opcode) {
|
| M68kISelLowering.cpp | 1411 static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC,
1427 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ;
1433 static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC, const SDLoc &DL,
1481 static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode) {
1508 /// Do a one-to-one translation of a ISD::CondCode to the M68k-specific
1511 static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
1562 llvm_unreachable("Condcode should be pre-legalized away");
1592 static SDValue LowerTruncateToBT(SDValue Op, ISD::CondCode CC, const SDLoc &DL,
1890 SDValue M68kTargetLowering::LowerToBT(SDValue Op, ISD::CondCode CC
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64SpeculationHardening.cpp | 154 AArch64CC::CondCode &CondCode) const;
156 AArch64CC::CondCode &CondCode, DebugLoc DL) const;
188 AArch64CC::CondCode &CondCode) const {
211 // translate analyzeBranchCondCode to CondCode.
213 CondCode = AArch64CC::CondCode(analyzeBranchCondCode[0].getImm());
226 MachineBasicBlock &SplitEdgeBB, AArch64CC::CondCode &CondCode
[all...] |
| AArch64ISelLowering.cpp | 2129 unsigned CondCode = MI.getOperand(3).getImm();
2142 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
2223 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
2251 static void changeFPCCToAArch64CC(ISD::CondCode CC,
2252 AArch64CC::CondCode &CondCode,
2253 AArch64CC::CondCode &CondCode2) {
2260 CondCode = AArch64CC::EQ;
2264 CondCode = AArch64CC::GT
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsInstPrinter.h | 32 enum CondCode {
72 const char *MipsFCCToString(Mips::CondCode CC);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VE.h | 42 enum CondCode {
85 inline static const char *VECondCodeToString(VECC::CondCode CC) {
114 inline static VECC::CondCode stringToVEICondCode(StringRef S) {
115 return StringSwitch<VECC::CondCode>(S)
128 inline static VECC::CondCode stringToVEFCondCode(StringRef S) {
129 return StringSwitch<VECC::CondCode>(S)
150 inline static unsigned VECondCodeToVal(VECC::CondCode CC) {
201 inline static VECC::CondCode VEValToCondCode(unsigned Val, bool IsInteger) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 37 enum CondCode {
133 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
146 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
157 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
212 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
233 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
289 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
298 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
406 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/AsmParser/ |
| MSP430AsmParser.cpp | 334 unsigned CondCode;
336 CondCode = MSP430CC::COND_NE;
338 CondCode = MSP430CC::COND_E;
340 CondCode = MSP430CC::COND_LO;
342 CondCode = MSP430CC::COND_HS;
344 CondCode = MSP430CC::COND_N;
346 CondCode = MSP430CC::COND_GE;
348 CondCode = MSP430CC::COND_L;
350 CondCode = MSP430CC::COND_NONE;
354 if (CondCode == (unsigned)MSP430CC::COND_NONE
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 80 enum CondCode {
289 classifySecondCondCodeInMacroFusion(X86::CondCode CC) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 235 enum CondCode { // Meaning (integer) Meaning (floating-point)
262 inline static const char *getCondCodeName(CondCode Code) {
284 inline static CondCode getInvertedCondCode(CondCode Code) {
287 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
294 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/ |
| LanaiAsmParser.cpp | 1077 LPCC::CondCode CondCode =
1079 if (CondCode != LPCC::UNKNOWN) {
1083 MCConstantExpr::create(CondCode, getContext()), NameLoc, NameLoc));
1097 LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic);
1098 if (CondCode != LPCC::UNKNOWN) {
1112 MCConstantExpr::create(CondCode, getContext()), NameLoc, NameLoc));
|
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| decode.h | 33 typedef enum CondCode
53 } CondCode;
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| decode.h | 33 typedef enum CondCode
53 } CondCode;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/ |
| VEAsmParser.cpp | 856 VECC::CondCode CondCode =
860 if (CondCode != VECC::UNKNOWN &&
861 (!OmitCC || (CondCode != VECC::CC_AT && CondCode != VECC::CC_AF))) {
869 Operands->push_back(VEOperand::CreateCCOp(CondCode, CondLoc, SuffixLoc));
914 // Adjust position of CondCode.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 170 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
234 bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
254 X86::CondCode TmpCC;
1524 X86::CondCode CC;
1654 X86::CondCode CC;
2045 X86::CondCode CC = X86::COND_NE;
2296 X86::CondCode CC = X86::COND_NE;
2880 unsigned BaseOpc, CondCode;
2884 BaseOpc = ISD::ADD; CondCode = X86::COND_O; break;
2886 BaseOpc = ISD::ADD; CondCode = X86::COND_B; break
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 66 CONDCODE,
1328 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
1341 enum CondCode {
1374 inline bool isSignedIntSetCC(CondCode Code) {
1380 inline bool isUnsignedIntSetCC(CondCode Code) {
1386 inline bool isIntEqualitySetCC(CondCode Code) {
1393 inline bool isTrueWhenEqual(CondCode Cond) { return ((int)Cond & 1) != 0; }
1398 inline unsigned getUnorderedFlavor(CondCode Cond) {
1404 CondCode getSetCCInverse(CondCode Operation, EVT Type)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 2360 unsigned CondCode = MI.getOperand(3).getImm();
2362 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
2364 NewMI.addImm(CondCode);
|
| ARMISelLowering.cpp | 480 const ISD::CondCode Cond;
556 const ISD::CondCode Cond;
653 const ISD::CondCode Cond;
1935 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1952 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1958 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1960 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1962 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1963 case ISD::SETOLT: CondCode = ARMCC::MI; break
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 155 AArch64CC::CondCode parseCondCodeString(StringRef Cond);
395 AArch64CC::CondCode Code;
447 struct CondCodeOp CondCode;
480 CondCode = o.CondCode;
548 AArch64CC::CondCode getCondCode() const {
550 return CondCode.Code;
1960 CreateCondCode(AArch64CC::CondCode Code, SMLoc S, SMLoc E, MCContext &Ctx) {
1962 Op->CondCode.Code = Code;
2099 OS << "<condcode " << getCondCode() << ">"
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 4680 unsigned CondCode = CD->getZExtValue();
4681 if (!ICmpInst::isIntPredicate(static_cast<ICmpInst::Predicate>(CondCode)))
4684 ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
4699 ISD::CondCode CCOpcode = getICmpCondCode(IcInput);
4716 unsigned CondCode = CD->getZExtValue();
4717 if (!FCmpInst::isFPPredicate(static_cast<FCmpInst::Predicate>(CondCode)))
4730 FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode);
4731 ISD::CondCode CCOpcode = getFCmpCondCode(IcInput);
9079 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
9080 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get()
[all...] |
