HomeSort by: relevance | last modified time | path
    Searched defs:Cst (Results 1 - 16 of 16) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCValue.h 39 int64_t Cst = 0;
44 int64_t getConstant() const { return Cst; }
64 R.Cst = Val;
73 R.Cst = Val;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
Utils.h 308 int64_t Cst;
314 explicit RegOrConstant(int64_t Cst) : Cst(Cst), IsReg(false) {}
323 return Cst;
359 /// %cst = G_CONSTANT iN 4
360 /// %constant_splat = G_BUILD_VECTOR %cst, %cst, ..., %cst
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.h 458 SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
459 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
462 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerCombiner.cpp 57 auto Cst = getConstantVRegValWithLookThrough(Src2, MRI);
58 if (!Cst || Cst->Value != 0)
AArch64PostLegalizerLowering.cpp 410 auto Cst =
413 {MatchInfo.SrcOps[0], MatchInfo.SrcOps[1], Cst});
480 auto Cst = getAArch64VectorSplatScalar(*MI, MRI);
481 if (!Cst)
483 Cnt = *Cst;
635 auto Cst = MIB.buildConstant(MRI.cloneVirtualRegister(RHS.getReg()),
638 RHS.setReg(Cst->getOperand(0).getReg());
731 int64_t Cst = Splat->getCst();
732 return (Cst != 0 && Cst != -1)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64StackTagging.cpp 149 uint64_t Cst = 0x0101010101010101UL;
152 Cst = (Cst >> LowBits) << LowBits;
155 Cst = (Cst << HighBits) >> HighBits;
157 ConstantInt::get(IRB.getInt64Ty(), Cst * V->getZExtValue());
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
MachineIRBuilder.cpp 204 auto Cst = buildConstant(ValueTy, Value);
205 return buildPtrAdd(Res, Op0, Cst.getReg(0));
IRTranslator.cpp 283 // Unless the value is a Constant => loadimm cst?
792 auto Cst = getOrCreateVReg(
794 Cst = MIB.buildZExtOrTrunc(PtrScalarTy, Cst).getReg(0);
795 auto Cmp = MIB.buildICmp(CmpInst::ICMP_UGT, LLT::scalar(1), Sub, Cst);
2088 ConstantInt *Cst = cast<ConstantInt>(CI.getArgOperand(1));
2091 ? Cst->isZero() ? TargetOpcode::G_CTTZ
2093 : Cst->isZero() ? TargetOpcode::G_CTLZ
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 829 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
830 return Cst->isNullValue();
2038 ConstantSDNode *Cst
2040 Consts.push_back(Cst->getZExtValue());
2045 ConstantSDNode *Cst = cast<ConstantSDNode>(CstOffset);
2046 Consts.push_back(Cst->getZExtValue());
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineCasts.cpp 886 // Transform "trunc (shl X, cst)" -> "shl (trunc X), cst" so long as the
887 // dest type is native and cst < dest size.
913 ConstantInt *Cst;
914 if (match(Src, m_OneUse(m_ExtractElt(m_Value(VecOp), m_ConstantInt(Cst))))) {
922 uint64_t VecOpIdx = Cst->getZExtValue();
1123 // We can promote shl(x, cst) if we can promote x. Since shl overwrites the
1136 // We can promote lshr(x, cst) if we can promote x. This requires the
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 2136 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
2137 if (!foldOffsetIntoAddress(Cst->getSExtValue(), AM))
3935 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
3936 if (!Cst)
3939 int64_t Val = Cst->getSExtValue();
4008 unsigned ZExtWidth = Cst->getAPIntValue().getActiveBits();
4014 NeededMask &= ~Cst->getAPIntValue();
4866 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
4867 if (!Cst)
4870 int64_t Val = Cst->getSExtValue()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeIntegerTypes.cpp 2919 const APInt &Cst = Constant->getAPIntValue();
2923 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
2924 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
4267 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
4268 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
4269 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
DAGCombiner.cpp 6857 ConstantSDNode *Cst = isConstOrConstSplat(Op.getOperand(1));
6858 return Cst && (Cst->getAPIntValue() == Imm);
8960 if (ConstantSDNode *Cst = isConstOrConstSplat(N2)) {
8964 if (Cst->getAPIntValue().uge(BitWidth)) {
8965 uint64_t RotAmt = Cst->getAPIntValue().urem(BitWidth);
8970 unsigned ShAmt = Cst->getZExtValue();
10515 // fold (zext (and/or/xor (shl/shr (load x), cst), cst)) ->
10516 // (and/or/xor (shl/shr (zextload x), (zext cst)), (zext cst)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
SimplifyCFG.cpp 4088 ConstantInt *Cst = cast<ConstantInt>(ICI->getOperand(1));
4120 if (SI->findCaseValue(Cst) != SI->case_default()) {
4168 SIW.addCase(Cst, NewBB, NewW);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CodeGenPrepare.cpp 4177 // ext(and(opnd, cst)) --> and(ext(opnd), ext(cst))
4182 // ext(xor(opnd, cst)) --> xor(ext(opnd), ext(cst))
4184 const ConstantInt *Cst = dyn_cast<ConstantInt>(Inst->getOperand(1));
4186 if (Cst && !Cst->getValue().isAllOnesValue())
4190 // zext(shrl(opnd, cst)) --> shrl(zext(opnd), zext(cst))
4198 // and(ext(shl(opnd, cst)), cst) --> and(shl(ext(opnd), ext(cst)), cst
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 8091 SDValue Cst = DAG.getConstantFP(APF, dl, SrcVT);
8103 SDValue Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT,
8108 dl, SrcVT, Sel, DAG.getConstantFP(0.0, dl, SrcVT), Cst);
8126 SDValue True = DAG.getNode(ISD::FSUB, dl, MVT::ppcf128, Src, Cst);
8130 return DAG.getSelectCC(dl, Src, Cst, True, False, ISD::SETGE);
15749 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
15750 if (!CST) return; // Must be an immediate to match.
15752 int64_t Value = CST->getSExtValue();

Completed in 87 milliseconds