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      1 /* $NetBSD: sun20i_d1_ccu.h,v 1.1 2024/08/13 07:20:23 skrll Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2024 Rui-Xiang Guo
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef __CCU_D1_H__
     30 #define __CCU_D1_H__
     31 
     32 #define D1_CLK_PLL_CPU		0
     33 #define D1_CLK_PLL_DDR		1
     34 #define D1_CLK_PLL_PERIPH_4X	2
     35 #define D1_CLK_PLL_PERIPH_2X	3
     36 #define D1_CLK_PLL_PERIPH_800M	4
     37 #define D1_CLK_PLL_PERIPH	5
     38 #define D1_CLK_PLL_PERIPH_DIV3	6
     39 #define D1_CLK_PLL_VIDEO0_4X	7
     40 #define D1_CLK_PLL_VIDEO0_2X	8
     41 #define D1_CLK_PLL_VIDEO0	9
     42 #define D1_CLK_PLL_VIDEO1_4X	10
     43 #define D1_CLK_PLL_VIDEO1_2X	11
     44 #define D1_CLK_PLL_VIDEO1	12
     45 #define D1_CLK_PLL_VE		13
     46 #define D1_CLK_PLL_AUDIO0_4X	14
     47 #define D1_CLK_PLL_AUDIO0_2X	15
     48 #define D1_CLK_PLL_AUDIO0	16
     49 #define D1_CLK_PLL_AUDIO1	17
     50 #define D1_CLK_PLL_AUDIO1_DIV2	18
     51 #define D1_CLK_PLL_AUDIO1_DIV5	19
     52 #define D1_CLK_CPU		20
     53 #define D1_CLK_CPU_AXI		21
     54 #define D1_CLK_CPU_APB		22
     55 #define D1_CLK_PSI		23
     56 #define D1_CLK_APB0		24
     57 #define D1_CLK_APB1		25
     58 #define D1_CLK_MBUS		26
     59 #define D1_CLK_DE		27
     60 #define D1_CLK_BUS_DE		28
     61 #define D1_CLK_DI		29
     62 #define D1_CLK_BUS_DI		30
     63 #define D1_CLK_G2D		31
     64 #define D1_CLK_BUS_G2D		32
     65 #define D1_CLK_CE		33
     66 #define D1_CLK_BUS_CE		34
     67 #define D1_CLK_VE		35
     68 #define D1_CLK_BUS_VE		36
     69 #define D1_CLK_BUS_DMA		37
     70 #define D1_CLK_BUS_MSGBOX0	38
     71 #define D1_CLK_BUS_MSGBOX1	39
     72 #define D1_CLK_BUS_MSGBOX2	40
     73 #define D1_CLK_BUS_SPINLOCK	41
     74 #define D1_CLK_BUS_HSTIMER	42
     75 #define D1_CLK_AVS		43
     76 #define D1_CLK_BUS_DBGSYS	44
     77 #define D1_CLK_BUS_PWM		45
     78 #define D1_CLK_BUS_IOMMU	46
     79 #define D1_CLK_DRAM		47
     80 #define D1_CLK_MBUS_DMA		48
     81 #define D1_CLK_MBUS_VE		49
     82 #define D1_CLK_MBUS_CE		50
     83 #define D1_CLK_MBUS_TVIN	51
     84 #define D1_CLK_MBUS_CSI		52
     85 #define D1_CLK_MBUS_G2D		53
     86 #define D1_CLK_MBUS_RISCV	54
     87 #define D1_CLK_BUS_DRAM		55
     88 #define D1_CLK_MMC0		56
     89 #define D1_CLK_MMC1		57
     90 #define D1_CLK_MMC2		58
     91 #define D1_CLK_BUS_MMC0		59
     92 #define D1_CLK_BUS_MMC1		60
     93 #define D1_CLK_BUS_MMC2		61
     94 #define D1_CLK_BUS_UART0	62
     95 #define D1_CLK_BUS_UART1	63
     96 #define D1_CLK_BUS_UART2	64
     97 #define D1_CLK_BUS_UART3	65
     98 #define D1_CLK_BUS_UART4	66
     99 #define D1_CLK_BUS_UART5	67
    100 #define D1_CLK_BUS_I2C0		68
    101 #define D1_CLK_BUS_I2C1		69
    102 #define D1_CLK_BUS_I2C2		70
    103 #define D1_CLK_BUS_I2C3		71
    104 #define D1_CLK_SPI0		72
    105 #define D1_CLK_SPI1		73
    106 #define D1_CLK_BUS_SPI0		74
    107 #define D1_CLK_BUS_SPI1		75
    108 #define D1_CLK_EMAC_25M		76
    109 #define D1_CLK_BUS_EMAC		77
    110 #define D1_CLK_IRTX		78
    111 #define D1_CLK_BUS_IRTX		79
    112 #define D1_CLK_BUS_GPADC	80
    113 #define D1_CLK_BUS_THS		81
    114 #define D1_CLK_I2S0		82
    115 #define D1_CLK_I2S1		83
    116 #define D1_CLK_I2S2		84
    117 #define D1_CLK_I2S2_ASRC	85
    118 #define D1_CLK_BUS_I2S0		86
    119 #define D1_CLK_BUS_I2S1		87
    120 #define D1_CLK_BUS_I2S2		88
    121 #define D1_CLK_SPDIF_TX		89
    122 #define D1_CLK_SPDIF_RX		90
    123 #define D1_CLK_BUS_SPDIF	91
    124 #define D1_CLK_DMIC		92
    125 #define D1_CLK_BUS_DMIC		93
    126 #define D1_CLK_AUDIO_DAC	94
    127 #define D1_CLK_AUDIO_ADC	95
    128 #define D1_CLK_BUS_AUDIO	96
    129 #define D1_CLK_USB_PHY0		97
    130 #define D1_CLK_USB_PHY1		98
    131 #define D1_CLK_BUS_OHCI0	99
    132 #define D1_CLK_BUS_OHCI1	100
    133 #define D1_CLK_BUS_EHCI0	101
    134 #define D1_CLK_BUS_EHCI1	102
    135 #define D1_CLK_BUS_OTG		103
    136 #define D1_CLK_BUS_LRADC	104
    137 #define D1_CLK_BUS_DPSS_TOP	105
    138 #define D1_CLK_HDMI_24M		106
    139 #define D1_CLK_HDMI_CEC_32K	107
    140 #define D1_CLK_HDMI_CEC		108
    141 #define D1_CLK_BUS_HDMI		109
    142 #define D1_CLK_DSI		110
    143 #define D1_CLK_BUS_DSI		111
    144 #define D1_CLK_TCONLCD		112
    145 #define D1_CLK_BUS_TCONLCD	113
    146 #define D1_CLK_TCONTV		114
    147 #define D1_CLK_BUS_TCONTV	115
    148 #define D1_CLK_TVE		116
    149 #define D1_CLK_BUS_TVE_TOP	117
    150 #define D1_CLK_BUS_TVE		118
    151 #define D1_CLK_TVD		119
    152 #define D1_CLK_BUS_TVD_TOP	120
    153 #define D1_CLK_BUS_TVD		121
    154 #define D1_CLK_LEDC		122
    155 #define D1_CLK_BUS_LEDC		123
    156 #define D1_CLK_CSI_TOP		124
    157 #define D1_CLK_CSI_MCLK		125
    158 #define D1_CLK_BUS_CSI		126
    159 #define D1_CLK_TPADC		127
    160 #define D1_CLK_BUS_TPADC	128
    161 #define D1_CLK_BUS_TZMA		129
    162 #define D1_CLK_DSP		130
    163 #define D1_CLK_BUS_DSP_CFG	131
    164 #define D1_CLK_RISCV		132
    165 #define D1_CLK_RISCV_AXI	133
    166 #define D1_CLK_BUS_RISCV_CFG	134
    167 #define D1_CLK_FANOUT_24M	135
    168 #define D1_CLK_FANOUT_12M	136
    169 #define D1_CLK_FANOUT_16M	137
    170 #define D1_CLK_FANOUT_25M	138
    171 #define D1_CLK_FANOUT_32K	139
    172 #define D1_CLK_FANOUT_27M	140
    173 #define D1_CLK_FANOUT_PCLK	141
    174 #define D1_CLK_FANOUT0		142
    175 #define D1_CLK_FANOUT1		143
    176 #define D1_CLK_FANOUT2		144
    177 #define D1_CLK_BUS_CAN0		145
    178 #define D1_CLK_BUS_CAN1		146
    179 
    180 #define D1_RST_MBUS		0
    181 #define D1_RST_BUS_DE		1
    182 #define D1_RST_BUS_DI		2
    183 #define D1_RST_BUS_G2D		3
    184 #define D1_RST_BUS_CE		4
    185 #define D1_RST_BUS_VE		5
    186 #define D1_RST_BUS_DMA		6
    187 #define D1_RST_BUS_MSGBOX0	7
    188 #define D1_RST_BUS_MSGBOX1	8
    189 #define D1_RST_BUS_MSGBOX2	9
    190 #define D1_RST_BUS_SPINLOCK	10
    191 #define D1_RST_BUS_HSTIMER	11
    192 #define D1_RST_BUS_DBGSYS	12
    193 #define D1_RST_BUS_PWM		13
    194 #define D1_RST_BUS_DRAM		14
    195 #define D1_RST_BUS_MMC0		15
    196 #define D1_RST_BUS_MMC1		16
    197 #define D1_RST_BUS_MMC2		17
    198 #define D1_RST_BUS_UART0	18
    199 #define D1_RST_BUS_UART1	19
    200 #define D1_RST_BUS_UART2	20
    201 #define D1_RST_BUS_UART3	21
    202 #define D1_RST_BUS_UART4	22
    203 #define D1_RST_BUS_UART5	23
    204 #define D1_RST_BUS_I2C0		24
    205 #define D1_RST_BUS_I2C1		25
    206 #define D1_RST_BUS_I2C2		26
    207 #define D1_RST_BUS_I2C3		27
    208 #define D1_RST_BUS_SPI0		28
    209 #define D1_RST_BUS_SPI1		29
    210 #define D1_RST_BUS_EMAC		30
    211 #define D1_RST_BUS_IRTX		31
    212 #define D1_RST_BUS_GPADC	32
    213 #define D1_RST_BUS_THS		33
    214 #define D1_RST_BUS_I2S0		34
    215 #define D1_RST_BUS_I2S1		35
    216 #define D1_RST_BUS_I2S2		36
    217 #define D1_RST_BUS_SPDIF	37
    218 #define D1_RST_BUS_DMIC		38
    219 #define D1_RST_BUS_AUDIO	39
    220 #define D1_RST_USB_PHY0		40
    221 #define D1_RST_USB_PHY1		41
    222 #define D1_RST_BUS_OHCI0	42
    223 #define D1_RST_BUS_OHCI1	43
    224 #define D1_RST_BUS_EHCI0	44
    225 #define D1_RST_BUS_EHCI1	45
    226 #define D1_RST_BUS_OTG		46
    227 #define D1_RST_BUS_LRADC	47
    228 #define D1_RST_BUS_DPSS_TOP	48
    229 #define D1_RST_BUS_HDMI_SUB	49
    230 #define D1_RST_BUS_HDMI_MAIN	50
    231 #define D1_RST_BUS_DSI		51
    232 #define D1_RST_BUS_TCONLCD	52
    233 #define D1_RST_BUS_TCONTV	53
    234 #define D1_RST_BUS_LVDS		54
    235 #define D1_RST_BUS_TVE		55
    236 #define D1_RST_BUS_TVE_TOP	56
    237 #define D1_RST_BUS_TVD		57
    238 #define D1_RST_BUS_TVD_TOP	58
    239 #define D1_RST_BUS_LEDC		59
    240 #define D1_RST_BUS_CSI		60
    241 #define D1_RST_BUS_TPADC	61
    242 #define D1_RST_BUS_DSP		62
    243 #define D1_RST_BUS_DSP_CFG	63
    244 #define D1_RST_BUS_DSP_DBG	64
    245 #define D1_RST_BUS_RISCV_CFG	65
    246 #define D1_RST_BUS_CAN0		66
    247 #define D1_RST_BUS_CAN1		67
    248 
    249 #endif /* __CCU_D1_H__ */
    250