1 /* $NetBSD: dm9000reg.h,v 1.12 2024/07/05 20:19:42 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Paul Fleischer 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _DEV_IC_DM9000REG_H_ 30 #define _DEV_IC_DM9000REG_H_ 31 32 /* 33 * Registers accessible on the DM9000, extracted from pp. 11-12 from 34 * the data sheet 35 */ 36 37 /* 38 * There are two interesting addresses for the DM9000 (at least in 39 * the context of the FriendlyARM MINI2440) The I/O or register select 40 * address, which is the base address. The DATA address, which is 41 * located at offset 4 from the base address. 42 * 43 * Chances are that this will not work generally, as it really depends 44 * on how the address lines are mapped from the CPU to the DM9000. 45 * But for now it is a good starting point. 46 */ 47 48 #define DM9000_IOSIZE 4 49 50 #define DM9000_NCR 0x00 /* "network" control */ 51 #define DM9000_NCR_RST (1<<0) /* reset chip, self clear */ 52 #define DM9000_NCR_LBK_MASK (0x06) /* loopback test selection */ 53 #define DM9000_NCR_LBK_SHIFT (1) 54 #define DM9000_NCR_LBK_NORMAL (0<<1) /* normal operation */ 55 #define DM9000_NCR_LBK_MAC_INTERNAL (1<<1) /* MAC loopback */ 56 #define DM9000_NCR_LBK_INT_PHY (2<<1) /* PHY loopback */ 57 #define DM9000_NCR_FDX (1<<3) /* use full-duplex, RO when int PHY */ 58 #define DM9000_NCR_FCOL (1<<4) /* force coll. mode. test only */ 59 #define DM9000_NCR_WAKEEN (1<<6) /* wakeup event enable */ 60 #define DM9000_NCR_EXY_PHY (1<<7) /* select ext. PHY, immune SW reset */ 61 #define DM9000_NSR 0x01 /* "network" status */ 62 #define DM9000_NSR_RXOV (1<<1) /* receive overflow detected */ 63 #define DM9000_NSR_TX1END (1<<2) /* transmit 1 completed, W1C */ 64 #define DM9000_NSR_TX2END (1<<3) /* transmit 2 completed, W1C */ 65 #define DM9000_NSR_WAKEST (1<<5) /* wakeup event, W1C */ 66 #define DM9000_NSR_LINKST (1<<6) /* link is up */ 67 #define DM9000_NSR_SPEED (1<<7) /* 1: 100Mbps, 0: 10Mbps */ 68 #define DM9000_TCR 0x02 /* Tx control */ 69 #define DM9000_TCR_TXREQ (1<<0) /* request to start Tx, self clear */ 70 #define DM9000_TCR_CRC_DIS1 (1<<1) /* disable PAD op on Tx1 */ 71 #define DM9000_TCR_PAD_DIS1 (1<<2) /* disable CRC append on Tx1 */ 72 #define DM9000_TCR_CRC_DIS2 (1<<3) /* disable PAD op on Tx2 */ 73 #define DM9000_TCR_PAD_DIS2 (1<<4) /* disable CRC append on Tx2 */ 74 #define DM9000_TCR_EXCECM (1<<5) /* allow infinite colli. retries */ 75 #define DM9000_TCR_TJDIS (1<<6) /* disable xmit jabber, otherwise on */ 76 #define DM9000_TSR1 0x03 /* transmit completion status 1 */ 77 #define DM9000_TSR2 0x04 /* transmit completion status 2 */ 78 #define DM9000_TSR_EC (1<<2) /* aborted after 16 collision */ 79 #define DM9000_TSR_COL (1<<3) /* collision detected while xmit */ 80 #define DM9000_TSR_LCOL (1<<4) /* out of window "late" collision */ 81 #define DM9000_TSR_NC (1<<5) /* no carrier signal found */ 82 #define DM9000_TSR_CLOSS (1<<6) /* loss of carrier */ 83 #define DM9000_TSR_TJTO (1<<7) /* Tx jabber time out */ 84 #define DM9000_RCR 0x05 /* Rx control */ 85 #define DM9000_RCR_RXEN (1<<0) /* activate Rx */ 86 #define DM9000_RCR_PRMSC (1<<1) /* enable promisc mode */ 87 #define DM9000_RCR_RUNT (1<<2) /* accept damaged runt frame */ 88 #define DM9000_RCR_ALL (1<<3) /* accept all multicast */ 89 #define DM9000_RCR_DIS_CRC (1<<4) /* drop bad CRC frame */ 90 #define DM9000_RCR_DIS_LONG (1<<5) /* drop too long frame >1522 */ 91 #define DM9000_RCR_WTDIS (1<<6) /* disable >2048 Rx detect timer */ 92 #define DM9000_RSR 0x06 /* Rx status */ 93 #define DM9000_RSR_FOE (1<<0) /* Rx FIFO overflow detected */ 94 #define DM9000_RSR_CE (1<<1) /* CRC error found */ 95 #define DM9000_RSR_AE (1<<2) /* tail not ended in byte boundary */ 96 #define DM9000_RSR_PLE (1<<3) /* physical layer error */ 97 #define DM9000_RSR_RWTO (1<<4) /* >2048 condition detected */ 98 #define DM9000_RSR_LCS (1<<5) /* late colli. detected */ 99 #define DM9000_RSR_MF (1<<6) /* mcast/bcast frame received */ 100 #define DM9000_RSR_RF (1<<7) /* damaged runt frame received <64 */ 101 #define DM9000_ROCR 0x07 /* receive overflow counter */ 102 /* 7: OVF detected, 6:0 statistic counter */ 103 #define DM9000_BPTR 0x08 /* back pressure threshold */ 104 /* 7:4 back pressure high watermark (3 def), 3:0 jam pattern time (7 def) */ 105 #define DM9000_FCTR 0x09 /* flow control threshold */ 106 /* 7:4 Rx FIFO high w.m. (3 def), low w.m. (8 def) */ 107 #define DM9000_FCR 0x0A /* Rx flow control */ 108 #define DM9000_FCR_FLCE (1<<0) /* flow control enable */ 109 #define DM9000_FCR_RXPCS (1<<1) /* Rx PAUSE current status */ 110 #define DM9000_FCR_RXPS (1<<2) /* Rx PAUSE status, latched R2C */ 111 #define DM9000_FCR_BKPM (1<<3) /* HDX back pressure for my frames */ 112 #define DM9000_FCR_BKPA (1<<4) /* HDX back pressure for any frames */ 113 #define DM9000_FCR_TXPEN (1<<5) /* activate auto PAUSE operation */ 114 #define DM9000_FCR_TXPF (1<<6) /* Tx PAUSE packet (when full) */ 115 #define DM9000_FCR_TXP0 (1<<7) /* Tx PAUSE packet (when empty) */ 116 #define DM9000_EPCR 0x0B /* EEPROM / PHY control */ 117 #define DM9000_EPCR_ERRE (1<<0) /* operation in progress, busy bit */ 118 #define DM9000_EPCR_ERPRW (1<<1) /* instruct to write, not SC */ 119 #define DM9000_EPCR_ERPRR (1<<2) /* instruct to read, not SC */ 120 #define DM9000_EPCR_EPOS_EEPROM (0<<3) /* EEPROM operation */ 121 #define DM9000_EPCR_EPOS_PHY (1<<3) /* PHY operation */ 122 #define DM9000_EPCR_WEP (1<<4) /* EEPROM write enable */ 123 #define DM9000_EPCR_REEP (1<<5) /* reload EEPROM contents, not SC */ 124 #define DM9000_EPAR 0x0C /* EEPROM / PHY address */ 125 #define DM9000_EPAR_EROA_MASK 0x3F /* 7:6 (!!) PHY id, 5:0 addr/reg */ 126 #define DM9000_EPAR_INT_PHY 0x40 /* EPAR[7:6] = 01 for internal PHY */ 127 #define DM9000_EPDRL 0x0D /* EEPROM / PHY data 7:0 */ 128 #define DM9000_EPDRH 0x0E /* EEPROM / PHY data 15:8 */ 129 #define DM9000_WCR 0x0F /* wakeup control and status */ 130 #define DM9000_MAGIC (1<<0) /* magic frame arrived */ 131 #define DM9000_SAMPLE (1<<1) /* sample frame arrived */ 132 #define DM9000_LINK (1<<2) /* link change / status change found */ 133 #define DM9000_MAGICEN (1<<3) /* enable magic frame event detect */ 134 #define DM9000_SMAPLEEN (1<<4) /* enable sample frame event detect */ 135 #define DM9000_LINKEN (1<<5) /* enable link change event detect */ 136 137 #define DM9000_PAB0 0x10 /* my station address 7:0 */ 138 #define DM9000_PAB1 0x11 139 #define DM9000_PAB2 0x12 140 #define DM9000_PAB3 0x13 141 #define DM9000_PAB4 0x14 142 #define DM9000_PAB5 0x15 /* my station address 47:40 */ 143 144 #define DM9000_MAB0 0x16 /* 64bit mcast hash filter 7:0 */ 145 #define DM9000_MAB1 0x17 146 #define DM9000_MAB2 0x18 147 #define DM9000_MAB3 0x19 148 #define DM9000_MAB4 0x1A 149 #define DM9000_MAB5 0x1B 150 #define DM9000_MAB6 0x1C 151 #define DM9000_MAB7 0x1D /* 63:56, needs 0x80 to catch bcast */ 152 153 #define DM9000_GPCR 0x1E /* GPIO control */ 154 #define DM9000_GPCR_GPIO0_OUT (1<<0) /* bit-0 to control PHY */ 155 /* 3:0 select pin I/O direction (0001 def) */ 156 #define DM9000_GPR 0x1F /* GPIO value to read / write */ 157 #define DM9000_GPR_PHY_PWROFF (1<<0) /* power down internal PHY */ 158 #define DM9000_TRPAL 0x22 /* Tx SRAM read pointer 7:0 */ 159 #define DM9000_TRPAH 0x23 /* Tx SRAM read pointer 15:8 */ 160 #define DM9000_RWPAL 0x24 /* Rx SRAM read pointer 7:0 */ 161 #define DM9000_RWPAH 0x25 /* Rx SRAM read pointer 15:8 */ 162 163 /* VID 0x0a46, PID 0x9000 */ 164 #define DM9000_VID0 0x28 /* vendor ID 7:0 */ 165 #define DM9000_VID1 0x29 /* vendor ID 15:8 */ 166 #define DM9000_PID0 0x2A /* product ID 7:0 */ 167 #define DM9000_PID1 0x2B /* product ID 15:8 */ 168 #define DM9000_CHIPR 0x2C /* chip revision */ 169 170 #define DM9000_TCR2 0x2D /* Tx control 2 */ 171 #define DM9000_OTCR 0x2E /* operation test control */ 172 #define DM9000_SMCR 0x2F /* special mode control */ 173 #define DM9000_FB0 (1<<0) /* force shortest back-off time */ 174 #define DM9000_FB1 (1<<1) /* force longest back-off time */ 175 #define DM9000_FLC (1<<2) /* force late collision */ 176 #define DM9000_SM_EN (1<<7) /* serial mode enable */ 177 #define DM9000_ETXCSR 0x30 /* early xmit control and status */ 178 #define DM9000_TCSCR 0x31 /* xmit checksum control */ 179 #define DM9000_RCSCSR 0x32 /* recv checksum control and status */ 180 #define DM9000_MPAR 0x33 /* MII PHY address */ 181 #define DM9000_LEDCR 0x34 /* LED pin control */ 182 #define DM9000_BUSCR 0x38 /* processor bus control */ 183 #define DM9000_INTCR 0x39 /* INT pin control */ 184 #define DM9000_SCCR 0x50 /* system clock turn on control */ 185 #define DM9000_RSCCR 0x51 /* resume system clock control */ 186 #define DM9000_MRCMDX 0xF0 /* "no increment" pre-fetch read */ 187 #define DM9000_MRCMDX1 0xF1 /* "no increment" read */ 188 #define DM9000_MRCMD 0xF2 /* "auto increment" read */ 189 #define DM9000_MRRL 0xF4 /* memory read address 7:0 */ 190 #define DM9000_MRRH 0xF5 /* memory read address 15:8 */ 191 #define DM9000_MWCMDX 0xF6 /* "no increment" write */ 192 #define DM9000_MWCMD 0xF8 /* "auto increment" write */ 193 #define DM9000_MWRL 0xFA /* memory write address 7:0 */ 194 #define DM9000_MWRH 0xFB /* memory write address 15:8 */ 195 #define DM9000_TXPLL 0xFC /* frame len 7:0 to transmit */ 196 #define DM9000_TXPLH 0xFD /* frame len 15:8 to transmit */ 197 #define DM9000_ISR 0xFE /* interrupt status report */ 198 #define DM9000_IOMODE_MASK 0xC0 199 #define DM9000_IOMODE_SHIFT 6 200 /* 7:6 I/O size (hard wired) 10b: 8-bit, 00b: 16-bit, 01b: 32-bit */ 201 #define DM9000_ISR_PRS (1<<0) /* receive completed, W1C */ 202 #define DM9000_ISR_PTS (1<<1) /* transmit completed, W1C */ 203 #define DM9000_ISR_ROS (1<<2) /* Rx overflow latch, W1C */ 204 #define DM9000_ISR_ROOS (1<<3) /* Rx overflow cntr overflowed, W1C */ 205 #define DM9000_ISR_UNDERRUN (1<<4) /* Tx underrun detected */ 206 #define DM9000_ISR_LNKCHNG (1<<5) /* link status change detected */ 207 #define DM9000_IMR 0xFF /* interrupt mask */ 208 #define DM9000_IMR_PRM (1<<0) /* enable receive event report */ 209 #define DM9000_IMR_PTM (1<<1) /* enable xmit done event report */ 210 #define DM9000_IMR_ROM (1<<2) /* enable Rx overflow event report */ 211 #define DM9000_IMR_ROOM (1<<3) /* enable Rx overflow cntr ov report */ 212 #define DM9000_IMR_PAR (1<<7) /* use 3/13K SRAM w/ auto wrap */ 213 214 #endif 215
Indexes created Wed Sep 24 15:09:51 GMT 2025