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      1 /*	$NetBSD: nextdmareg.h,v 1.10 2023/02/03 23:06:42 tsutsui Exp $	*/
      2 /*
      3  * Copyright (c) 1998 Darrin B. Jewell
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  */
     26 
     27 /* I think the chip can handle 64k per chain, but I don't
     28  * know how much per segment for sure.  We might try
     29  * experimenting with this value.  Can we cross page boundaries?
     30  */
     31 #define MAX_DMASIZE 8192
     32 
     33 /* from nextdev/dma.h */
     34 
     35 #if 0
     36 #define	DMA_BEGINALIGNMENT	4	/* initial buffer must be on long */
     37 #else
     38 /* But to make cache handling easier, we put it on a cache line anyway. */
     39 #define	DMA_BEGINALIGNMENT 16
     40 #endif
     41 #define	DMA_ENDALIGNMENT	16	/* DMA must end on quad longword */
     42 
     43 #define	DMA_ALIGN(type, addr)	\
     44 	((type)(((unsigned int)(addr) + DMA_BEGINALIGNMENT - 1) \
     45 	    & ~(DMA_BEGINALIGNMENT - 1)))
     46 
     47 #define	DMA_ENDALIGN(type, addr)	\
     48 	((type)(((unsigned int)(addr) + DMA_ENDALIGNMENT - 1) \
     49 	    & ~(DMA_ENDALIGNMENT - 1)))
     50 
     51 #define	DMA_BEGINALIGNED(addr)	\
     52 	(((unsigned int)(addr) & (DMA_BEGINALIGNMENT - 1)) == 0)
     53 #define	DMA_ENDALIGNED(addr)	\
     54 	(((unsigned int)(addr) & (DMA_ENDALIGNMENT - 1))==0)
     55 
     56 #if 0
     57 struct dma_dev {		/* format of dma device registers */
     58 	int dd_csr;		/* control & status register */
     59 	char dd_pad[0x3fec];	/* csr not contiguous with next */
     60 	char *dd_saved_next;	/* saved pointers for HW restart */
     61 	char *dd_saved_limit;
     62 	char *dd_saved_start;
     63 	char *dd_saved_stop;
     64 	char *dd_next;		/* next word to dma */
     65 	char *dd_limit;		/* dma complete when next == limit */
     66 	char *dd_start;		/* start of 2nd buf to dma */
     67 	char *dd_stop;		/* end of 2nd buf to dma */
     68 	char dd_pad2[0x1f0];
     69 	char *dd_next_initbuf;	/* next register that inits dma buffering */
     70 };
     71 #endif
     72 
     73 #define DD_CSR          0
     74 #define DD_SAVED_NEXT   (DD_CSR         + sizeof(int) + 0x3fec)
     75 #define DD_SAVED_LIMIT  (DD_SAVED_NEXT  + sizeof(char *))
     76 #define DD_SAVED_START  (DD_SAVED_LIMIT + sizeof(char *))
     77 #define DD_SAVED_STOP   (DD_SAVED_START + sizeof(char *))
     78 #define DD_NEXT         (DD_SAVED_STOP  + sizeof(char *))
     79 #define DD_LIMIT        (DD_NEXT        + sizeof(char *))
     80 #define DD_START        (DD_LIMIT       + sizeof(char *))
     81 #define DD_STOP         (DD_START       + sizeof(char *))
     82 #define DD_NEXT_INITBUF (DD_STOP        + sizeof(char *) + 0x1f0)
     83 
     84 #define DD_SIZE         (DD_NEXT_INITBUF + sizeof(char *))
     85 /*
     86  * bits in dd_csr
     87  */
     88 /* read bits */
     89 #define	DMACSR_ENABLE		0x01000000	/* enable dma transfer */
     90 #define	DMACSR_SUPDATE		0x02000000	/* single update */
     91 #define	DMACSR_READ		0x04000000	/* dma is ina read operation */
     92 #define	DMACSR_COMPLETE		0x08000000	/* current dma has completed */
     93 #define	DMACSR_BUSEXC		0x10000000	/* bus exception occurred */
     94 /* write bits */
     95 #define	DMACSR_SETENABLE	0x00010000 	/* set enable */
     96 #define	DMACSR_SETSUPDATE	0x00020000	/* set single update */
     97 #define	DMACSR_SETREAD		0x00040000	/* dma from dev to mem */
     98 #define	DMACSR_SETWRITE		0x00000000	/* dma from mem to dev */
     99 #define	DMACSR_CLRCOMPLETE	0x00080000	/* clear complete conditional */
    100 #define	DMACSR_RESET		0x00100000	/* clr cmplt, sup, enable */
    101 #define	DMACSR_INITBUF		0x00200000	/* initialize DMA buffers */
    102 #define DMACSR_INITBUFTURBO	0x00800000
    103 
    104 #define DMACSR_BITS \
    105 "\20\35BUSEXC\34COMPLETE\33READ\32SUPDATE\31ENABLE\26INITBUF\25RESET\24CLRCOMPLETE\23SETREAD\22SETSUPDATE\21SETENABLE"
    106