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      1 /*-
      2  * Copyright (c) 2012 The NetBSD Foundation, Inc.
      3  * All rights reserved.
      4  *
      5  * This code is derived from software contributed to The NetBSD Foundation
      6  * by Paul Fleischer <paul (at) xpg.dk>
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     19  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     20  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     21  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     27  * POSSIBILITY OF SUCH DAMAGE.
     28  */
     29 /* This file implements a simple interface towards the S3C2440 DMA controller.
     30    At this point queueing of transfers is not supported. In other words, one
     31    has to be very careful that noone else is using a DMA channel when trying to use it.
     32 
     33    Only device<->memory transfers are supported at this time.
     34 
     35    Currently, the only usage of S3C2440 DMA is in the S3C2440 SD-Interface driver
     36    (s3c2440_sdi.c).
     37  */
     38 
     39 #ifndef __S3C2440_DMA_H__
     40 #define __S3C2440_DMA_H__
     41 
     42 #include <sys/types.h>
     43 
     44 void s3c2440_dma_init(void);
     45 int  s3c2440_dma_intr(void *arg);
     46 
     47 typedef enum {
     48 	DMAC_BUS_TYPE_SYSTEM = 0,
     49 	DMAC_BUS_TYPE_PERIPHERAL
     50 } dmac_bus_type_t;
     51 
     52 typedef enum {
     53 	DMAC_SYNC_BUS_AUTO = 0,
     54 	DMAC_SYNC_BUS_SYSTEM,
     55 	DMAC_SYNC_BUS_PERIPHERAL
     56 } dmac_sync_bus_t;
     57 
     58 typedef enum {
     59 	DMAC_XFER_WIDTH_8BIT = 0,
     60 	DMAC_XFER_WIDTH_16BIT = 1,
     61 	DMAC_XFER_WIDTH_32BIT = 2
     62 } dmac_xfer_width_t;
     63 
     64 typedef enum {
     65 	DMAC_XFER_MODE_DEMAND = 0,
     66 	DMAC_XFER_MODE_HANDSHAKE = 1
     67 } dmac_xfer_mode_t;
     68 
     69 typedef struct dmac_xfer_desc*	dmac_xfer_desc_t;
     70 struct dmac_xfer_desc {
     71 	dmac_bus_type_t		xd_bus_type;
     72 	bool			xd_increment;
     73 	u_int			xd_nsegs;
     74 	bus_dma_segment_t	*xd_dma_segs;
     75 };
     76 
     77 typedef u_int	dmac_peripheral_t;
     78 #define	DMAC_PERIPH_NONE	0	/* Software triggered transfer */
     79 #define DMAC_PERIPH_XDREQ0	1
     80 #define DMAC_PERIPH_XDREQ1	2
     81 #define DMAC_PERIPH_UART0	3
     82 #define DMAC_PERIPH_UART1	4
     83 #define DMAC_PERIPH_UART2	5
     84 #define DMAC_PERIPH_I2SSDO	6
     85 #define DMAC_PERIPH_I2SSDI	7
     86 #define DMAC_PERIPH_SDI		8
     87 #define DMAC_PERIPH_SPI0	9
     88 #define DMAC_PERIPH_SPI1	10
     89 #define DMAC_PERIPH_PCMIN	11
     90 #define DMAC_PERIPH_PCMOUT	12
     91 #define DMAC_PERIPH_MICIN	13
     92 #define DMAC_PERIPH_MICOUT	14
     93 #define DMAC_PERIPH_TIMER	15
     94 #define DMAC_PERIPH_USBEP1	16
     95 #define DMAC_PERIPH_USBEP2	17
     96 #define DMAC_PERIPH_USBEP3	18
     97 #define DMAC_PERIPH_USBEP4	19
     98 #define DMAC_N_PERIPH		20
     99 
    100 typedef struct dmac_xfer*	dmac_xfer_t;
    101 struct dmac_xfer {
    102 	void			(*dx_done)(dmac_xfer_t, void*);
    103 	void			*dx_cookie;
    104 	dmac_peripheral_t	dx_peripheral; /* Controls trigger mechanism
    105 						  and DMA channel to use */
    106 	struct dmac_xfer_desc	dx_desc[2];
    107 #define DMAC_DESC_SRC	0
    108 #define DMAC_DESC_DST	1
    109 
    110 	dmac_sync_bus_t		dx_sync_bus;
    111 
    112 	dmac_xfer_width_t	dx_xfer_width;
    113 
    114 	dmac_xfer_mode_t	dx_xfer_mode;
    115 };
    116 
    117 /* DMA API, inspired by pxa2x0_dmac.h */
    118 dmac_xfer_t s3c2440_dmac_allocate_xfer(void);
    119 void s3c2440_dmac_free_xfer(dmac_xfer_t);
    120 int s3c2440_dmac_start_xfer(dmac_xfer_t);
    121 void s3c2440_dmac_abort_xfer(dmac_xfer_t);
    122 int s3c2440_dmac_wait_xfer(dmac_xfer_t, int);
    123 
    124 #endif
    125