1 /* $NetBSD: dovereg.h,v 1.2 2022/10/31 20:30:22 andvar Exp $ */ 2 /* 3 * Copyright (c) 2016 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _DOVEREG_H_ 29 #define _DOVEREG_H_ 30 31 #include <arm/marvell/mvsocreg.h> 32 33 #define DOVE_UNITID_DDR MVSOC_UNITID_DDR 34 #define DOVE_UNITID_DEVBUS MVSOC_UNITID_DEVBUS 35 #define DOVE_UNITID_DB 0x2 /* Downstream Bridge reg */ 36 #define DOVE_UNITID_SA 0x3 /* Security Accelerator reg */ 37 #define DOVE_UNITID_PEX MVSOC_UNITID_PEX 38 #define DOVE_UNITID_USB 0x5 39 #define DOVE_UNITID_XOR 0x6 40 #define DOVE_UNITID_GBE 0x7 41 #define DOVE_UNITID_PEX1 0x8 42 #define DOVE_UNITID_SDIO 0x9 43 #define DOVE_UNITID_SATA 0xa 44 #define DOVE_UNITID_I2S 0xb 45 #define DOVE_UNITID_NAND 0xc 46 #define DOVE_UNITID_PMU 0xd 47 #define DOVE_UNITID_AC97 0xe 48 49 #define DOVE_ATTR_PEX_MEM 0xe8 50 #define DOVE_ATTR_PEX_IO 0xe0 51 #define DOVE_ATTR_SA 0x00 52 #define DOVE_ATTR_SPI0 0xfe 53 #define DOVE_ATTR_SPI1 0xfb 54 #define DOVE_ATTR_BOOTROM 0xfd 55 #define DOVE_ATTR_NAND 0x00 56 #define DOVE_ATTR_PMU 0x00 57 58 #define DOVE_IRQ_BRIDGE 0 /* Downstream Bridge intr */ 59 #define DOVE_IRQ_H2CPUDB 1 /* Doorbell Interrupt */ 60 #define DOVE_IRQ_CPU2HDB 2 /* Doorbell Interrupt */ 61 #define DOVE_IRQ_NF 3 /* NandFlash Interrupt */ 62 #define DOVE_IRQ_PDMA 4 /* Peripheral DMA Interrupt */ 63 #define DOVE_IRQ_SPI1 5 /* SPI1 Ready Interrupt */ 64 #define DOVE_IRQ_SPI0 6 /* SPI9 Ready Interrupt */ 65 #define DOVE_IRQ_UART0 7 /* UART0 Interrupt */ 66 #define DOVE_IRQ_UART1 8 /* UART1 Interrupt */ 67 #define DOVE_IRQ_UART2 9 /* UART2 Interrupt */ 68 #define DOVE_IRQ_UART3 10 /* UART3 Interrupt */ 69 #define DOVE_IRQ_TWSI 11 /* TWSI Interrupt */ 70 #define DOVE_IRQ_GPIO7_0 12 /* GPIO[7:0] Interrupt */ 71 #define DOVE_IRQ_GPIO15_8 13 /* GPIO[15:8] Interrupt */ 72 #define DOVE_IRQ_GPIO23_16 14 /* GPIO[23:16] Interrupt */ 73 #define DOVE_IRQ_PEX0_ERR 15 /* PCI Express0 Error */ 74 #define DOVE_IRQ_PEX0_INT 16 /*PCI Express0 INT [A-D] mesg*/ 75 #define DOVE_IRQ_PEX1_ERR 17 /* PCI Express1 Error */ 76 #define DOVE_IRQ_PEX1_INT 18 /*PCI Express1 INT [A-D] mesg*/ 77 #define DOVE_IRQ_AUDIO0_INT 19 /* Audio0 Interrupt */ 78 #define DOVE_IRQ_AUDIO0_ERR 20 /* Audio0 Error */ 79 #define DOVE_IRQ_AUDIO1_INT 21 /* Audio1 Interrupt */ 80 #define DOVE_IRQ_AUDIO1_ERR 22 /* Audio1 Error */ 81 #define DOVE_IRQ_USBBR 23 /* USB Bridge Error */ 82 #define DOVE_IRQ_USB0CNT 24 /* USB0 Controller Interrupt */ 83 #define DOVE_IRQ_USB1CNT 25 /* USB1 Controller Interrupt */ 84 #define DOVE_IRQ_GBERX 26 /* GbE Receive Interrupt */ 85 #define DOVE_IRQ_GBETX 27 /* GbE Transmit Interrupt */ 86 #define DOVE_IRQ_GBEMISC 28 /* GbE Miscellaneous intr */ 87 #define DOVE_IRQ_GBESUM 29 /* GbE Summary */ 88 #define DOVE_IRQ_GBEERR 30 /* GbE Error */ 89 #define DOVE_IRQ_SECURITYINT 31 /* Security Interrupt */ 90 #define DOVE_IRQ_AC97 32 /* AC97 Interrupt */ 91 #define DOVE_IRQ_PMU 33 /* Power Management Unit intr */ 92 #define DOVE_IRQ_CAM 34 /* Cafe Camera Interrupt */ 93 #define DOVE_IRQ_SD0 35 /* SD0 IRQ Interrupt */ 94 #define DOVE_IRQ_SD1 36 /* SD1 IRQ Interrupt */ 95 #define DOVE_IRQ_XOR0_DMA0 39 /* XOR Unit DMA0 Completion */ 96 #define DOVE_IRQ_XOR0_DMA1 40 /* XOR Unit DMA1 Completion */ 97 #define DOVE_IRQ_XOR0ERR 41 /* XOR Unit Error Interrupt */ 98 #define DOVE_IRQ_XOR1_DMA0 42 /* XOR Unit DMA0 Completion */ 99 #define DOVE_IRQ_XOR1_DMA1 43 /* XOR Unit DMA1 Completion */ 100 #define DOVE_IRQ_XOR1ERR 44 /* XOR Unit Error Interrupt */ 101 #define DOVE_IRQ_IRE_DCON 45 /* IRE OR DCON Interrupt */ 102 #define DOVE_IRQ_LCD1 46 /* LCD1 Interrupt */ 103 #define DOVE_IRQ_LCD0 47 /* LCD0 Interrupt */ 104 #define DOVE_IRQ_GPU 48 /* GPU Interrupt */ 105 #define DOVE_IRQ_VMETA 51 /*Video dec Unit Semaphore intr*/ 106 #define DOVE_IRQ_SSPTIMER 54 /* SSP Timer Interrupt */ 107 #define DOVE_IRQ_SSPINT 55 /* SSP Interrupt */ 108 #define DOVE_IRQ_MEMORYERR 56 /*mem Controller or L2 ECC err*/ 109 #define DOVE_IRQ_DWNSTRMEXCLTM 57 110 #define DOVE_IRQ_UPSTRMADDERR 58 111 #define DOVE_IRQ_SECURITYERR 59 /* Security Error */ 112 #define DOVE_IRQ_GPIO_31_24 60 /* Interrupt from GPIO[31:24] */ 113 #define DOVE_IRQ_HIGHGPIO 61 /* intr from High GPIO[31:0] */ 114 #define DOVE_IRQ_SATAINT 62 /* SATA Interrupt */ 115 116 117 /* 118 * Physical address of integrated peripherals 119 */ 120 121 #define DOVE_UNITID2PHYS(uid) ((DOVE_UNITID_ ## uid) << 16) 122 123 /* 124 * SPI Registers 125 */ 126 #define DOVE_SPI0_BASE (MVSOC_DEVBUS_BASE + 0x0600) /* 0x10600 */ 127 #define DOVE_SPI1_BASE (MVSOC_DEVBUS_BASE + 0x4600) /* 0x14600 */ 128 129 /* 130 * UART Interface Registers 131 */ 132 /* NS16550 compatible */ 133 #define DOVE_COM2_BASE (MVSOC_DEVBUS_BASE + 0x2200) 134 #define DOVE_COM3_BASE (MVSOC_DEVBUS_BASE + 0x2300) 135 136 /* 137 * Downstream Bridge Registers 138 */ 139 #define DOVE_DB_BASE (DOVE_UNITID2PHYS(DB)) 140 141 /* CPU Address Map Registers */ 142 #define DOVE_DB_NWINDOW 8 143 #define DOVE_DB_NREMAP 4 144 145 /* Main Interrupt Controller Registers */ 146 #define DOVE_DB_MICR 0x200 /* Main Interrupt Cause reg */ 147 #define DOVE_DB_MIRQIMR 0x204 /* Main IRQ Interrupt Mask */ 148 #define DOVE_DB_MFIQIMR 0x208 /* Main FIQ Interrupt Mask */ 149 #define DOVE_DB_EIMR 0x20c /* Endpoint Interrupt Mask */ 150 #define DOVE_DB_SMICR 0x210 /* Second Main Intr Cause reg */ 151 #define DOVE_DB_SMIRQIMR 0x214 /* Second Main IRQ intr Mask */ 152 #define DOVE_DB_SMFIQIMR 0x218 /* Second Main FIQ intr Mask */ 153 #define DOVE_DB_SEIMR 0x21c /* Second Endpoint intr Mask */ 154 #define DOVE_DB_PCIEIMR 0x220 /* PCIe0/PCIe1 intr Mask reg */ 155 156 157 /* 158 * Cryptographic Engine and Security Accelerator (CESA) Registers 159 */ /* 0x3d000 */ 160 #define DOVE_CESA_BASE (DOVE_UNITID2PHYS(SA) + 0xd000) 161 162 /* 163 * USB 2.0 Interface Registers 164 */ 165 #define DOVE_USB0_BASE (DOVE_UNITID2PHYS(USB)) /* 0x50000 */ 166 #define DOVE_USB1_BASE (DOVE_UNITID2PHYS(USB) + 0x1000) 167 168 /* 169 * XOR DMA Engine Registers 170 */ 171 #define DOVE_XORE_BASE (DOVE_UNITID2PHYS(XOR)) /* 0x60000 */ 172 173 /* 174 * Gigabit Ethernet Controller (GbE) Registers 175 */ 176 #define DOVE_GBE_BASE (DOVE_UNITID2PHYS(GBE)) /* 0x70000 */ 177 178 /* 179 * PCI Express (PCIe) Registers 180 */ 181 #define DOVE_PEX1_BASE (DOVE_UNITID2PHYS(PEX1)) /* 0x80000 */ 182 183 /* 184 * Camera and SDIO Registers 185 */ 186 #define DOVE_SDHC_SIZE 0x2000 187 #define DOVE_SDHC1_BASE (DOVE_UNITID2PHYS(SDIO)) /* 0x90000 */ 188 #define DOVE_SDHC0_BASE (DOVE_SDHC1_BASE + DOVE_SDHC_SIZE) 189 #define DOVE_CAMERA_BASE (DOVE_SDHC0_BASE + DOVE_SDHC_SIZE) 190 191 /* 192 * Serial-ATA Host Controller Registers 193 */ 194 #define DOVE_SATAHC_BASE (DOVE_UNITID2PHYS(SATA)) /* 0xa0000 */ 195 196 /* 197 * Audio (I2S/S/PDIF) Interface Registers 198 */ 199 #define DOVE_AUDIO0_BASE (DOVE_UNITID2PHYS(I2S)) /* 0xb0000 */ 200 #define DOVE_AUDIO1_BASE (DOVE_UNITID2PHYS(I2S) + 0x4000) 201 202 /* 203 * NAND Flash Registers 204 */ 205 #define DOVE_NAND_BASE (DOVE_UNITID2PHYS(NAND)) /* 0xc0000 */ 206 207 /* 208 * Power Management Registers 209 */ 210 #define DOVE_PMU_BASE (DOVE_UNITID2PHYS(PMU)) /* 0xd0000 */ 211 #define DOVE_MISC_BASE (DOVE_UNITID2PHYS(PMU) + 0x0200) 212 #define DOVE_GPIO_BASE (DOVE_UNITID2PHYS(PMU) + 0x0400) 213 #define DOVE_PMU_BASE2 (DOVE_UNITID2PHYS(PMU) + 0x8000) 214 #define DOVE_RTC_BASE (DOVE_UNITID2PHYS(PMU) + 0x8500) 215 #define DOVE_PMU_SRAM_BASE (DOVE_UNITID2PHYS(PMU) + 0xc000) 216 #define DOVE_PMU_SRAM_SIZE 0x800 217 218 #define DOVE_PMU_SIZE 0x200 219 #define DOVE_PMU_CPUSDFSCR 0x00 220 #define DOVE_PMU_CPUSDFSCR_DFSEN (1 << 0) 221 #define DOVE_PMU_CPUSDFSCR_CPUSLOWEN (1 << 1) 222 #define DOVE_PMU_CPUSDFSCR_DDRLRATIO(x) (((x) & 0x3f) << 3) 223 #define DOVE_PMU_CPUSDFSCR_CPUL2CR(x) (((x) & 0x3f) << 9) 224 #define DOVE_PMU_CPUSDFSCR_CHNGPLLEN (1 << 16) 225 #define DOVE_PMU_CPUSDFSSR 0x04 226 #define DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_MASK (1 << 1) 227 #define DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_TURBO (0 << 1) 228 #define DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_SLOW (1 << 1) 229 #define DOVE_PMU_TM_BASE 0x1c 230 #define DOVE_PMU_CGCR 0x38 /* Clock Gating Control reg */ 231 #define DOVE_PMU_CPUCDC0R 0x44 /* CPU Clock Divider Control */ 232 #define DOVE_PMU_CPUCDC0R_DPRATIO(x) (((x) >> 24) & 0x3f) /* DRAM */ 233 #define DOVE_PMU_CPUCDC0R_XPRATIO(x) (((x) >> 16) & 0x3f) /* L2C */ 234 #define DOVE_PMU_CPUCDC0R_BPRATIO(x) (((x) >> 8) & 0x3f) /* AXI DS */ 235 #define DOVE_PMU_CPUCDC0R_PPRATIO(x) (((x) >> 0) & 0x3f) /* CPU */ 236 #define DOVE_PMU_PMUICR 0x50 /* PMU Interrupts Cause reg */ 237 #define DOVE_PMU_PMUIMR 0x54 /* PMU Interrupts Mask reg */ 238 #define DOVE_PMU_PMUI_DFSDONE (1 << 0) /* DFS Done */ 239 #define DOVE_PMU_PMUI_DVSDONE (1 << 1) /* DVS Done */ 240 #define DOVE_PMU_PMUI_THERMCOOLING (1 << 3) /* Thermal Cooling */ 241 #define DOVE_PMU_PMUI_THERMOVERHEAT (1 << 4) /*Thermal Overheating*/ 242 #define DOVE_PMU_PMUI_RTCALARM (1 << 5) 243 #define DOVE_PMU_PMUI_BATTFAULT (1 << 6) /* Battery Fault */ 244 #define DOVE_PMU_TDC0R 0x5c /* Thermal Diode Control 0 */ 245 #define DOVE_PMU_TDC0R_THERMSLEEP (1 << 30) /* sleep mode */ 246 #define DOVE_PMU_TDC0R_THERMOTFCALB (1 << 29) /* On-The-Fly calb */ 247 #define DOVE_PMU_TDC0R_THERMDOUBLESLOPE (1 << 28) 248 #define DOVE_PMU_TDC0R_THERMAVGNUM_MASK (0x7 << 25) 249 #define DOVE_PMU_TDC0R_THERMAVGNUM_NO (0x0 << 25) 250 #define DOVE_PMU_TDC0R_THERMAVGNUM_2 (0x1 << 25) 251 #define DOVE_PMU_TDC0R_THERMAVGNUM_4 (0x2 << 25) 252 #define DOVE_PMU_TDC0R_THERMAVGNUM_8 (0x3 << 25) 253 #define DOVE_PMU_TDC0R_THERMAVGNUM_16 (0x4 << 25) 254 #define DOVE_PMU_TDC0R_THERMAVGNUM_32 (0x5 << 25) /* ? */ 255 #define DOVE_PMU_TDC0R_THERMSELCALCAPSRC_MASK (0x7 << 20) 256 #define DOVE_PMU_TDC0R_THERMREFCALCOUNT_MASK (0x1ff << 11) 257 #define DOVE_PMU_TDC0R_THERMREFCALCOUNT(x) ((x) << 11) 258 #define DOVE_PMU_TDC0R_THERMATEST (0x3 << 10) 259 #define DOVE_PMU_TDC0R_THERMSELIREF (1 << 8) 260 #define DOVE_PMU_TDC0R_THERMVBEBYPASS (1 << 7) 261 #define DOVE_PMU_TDC0R_THERMSELVCAL_MASK (0x3 << 5) 262 #define DOVE_PMU_TDC0R_THERMSELVCAL(x) ((x) << 5) 263 #define DOVE_PMU_TDC0R_THERMTCTRIP (0x7 << 2) 264 #define DOVE_PMU_TDC0R_THERMSOFTRESET (1 << 1) 265 #define DOVE_PMU_TDC0R_THERMPOWERDOWN (1 << 0) 266 #define DOVE_PMU_TDC1R 0x60 /* Thermal Diode Control 1 */ 267 268 #define DOVE_PMU_PMUCR 0x00 /* PMU Control Register */ 269 #define DOVE_PMU_PMUCR_MASKFIQ (1 << 28) 270 #define DOVE_PMU_PMUCR_MASKIRQ (1 << 24) 271 #define DOVE_PMU_PMUCR_MCSLEEPREQACK (1 << 19) 272 #define DOVE_PMU_PMUCR_MCSLEEPREQ (1 << 18) 273 #define DOVE_PMU_PMUCR_MCHALTREQACK (1 << 17) 274 #define DOVE_PMU_PMUCR_MCHALTREQ (1 << 16) 275 #define DOVE_PMU_PMUCR_DDRSELFREFEN (1 << 5) 276 #define DOVE_PMU_PMUCR_STDBYPWREN (1 << 4) 277 #define DOVE_PMU_PMUCR_DEEPIDLEPWREN (1 << 3) 278 #define DOVE_PMU_PMUCR_EBOOKMODE (1 << 2) 279 #define DOVE_PMU_PMUCR_MEMRETENTIONEN (1 << 0) 280 281 #define DOVE_MISC_SAMPLE_AT_RESET0 0x14 282 283 /* 284 * Audio Codec'97 (AC'97) Registers 285 */ 286 #define DOVE_AC97_BASE (DOVE_UNITID2PHYS(AC97)) /* 0xe0000 */ 287 #define DOVE_SSP_BASE (DOVE_UNITID2PHYS(AC97) + 0xc000) 288 289 #endif /* _DOVEREG_H_ */ 290
Indexes created Sun Sep 21 16:09:51 GMT 2025