1 /* $NetBSD: sumod.h,v 1.4 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 #ifndef _SUMOD_H_ 27 #define _SUMOD_H_ 28 29 /* pm registers */ 30 31 /* rcu */ 32 #define RCU_FW_VERSION 0x30c 33 34 #define RCU_PWR_GATING_SEQ0 0x408 35 #define RCU_PWR_GATING_SEQ1 0x40c 36 #define RCU_PWR_GATING_CNTL 0x410 37 # define PWR_GATING_EN (1 << 0) 38 # define RSVD_MASK (0x3 << 1) 39 # define PCV(x) ((x) << 3) 40 # define PCV_MASK (0x1f << 3) 41 # define PCV_SHIFT 3 42 # define PCP(x) ((x) << 8) 43 # define PCP_MASK (0xf << 8) 44 # define PCP_SHIFT 8 45 # define RPW(x) ((x) << 16) 46 # define RPW_MASK (0xf << 16) 47 # define RPW_SHIFT 16 48 # define ID(x) ((x) << 24) 49 # define ID_MASK (0xf << 24) 50 # define ID_SHIFT 24 51 # define PGS(x) ((x) << 28) 52 # define PGS_MASK (0xf << 28) 53 # define PGS_SHIFT 28 54 55 #define RCU_ALTVDDNB_NOTIFY 0x430 56 #define RCU_LCLK_SCALING_CNTL 0x434 57 # define LCLK_SCALING_EN (1 << 0) 58 # define LCLK_SCALING_TYPE (1 << 1) 59 # define LCLK_SCALING_TIMER_PRESCALER(x) ((x) << 4) 60 # define LCLK_SCALING_TIMER_PRESCALER_MASK (0xf << 4) 61 # define LCLK_SCALING_TIMER_PRESCALER_SHIFT 4 62 # define LCLK_SCALING_TIMER_PERIOD(x) ((x) << 16) 63 # define LCLK_SCALING_TIMER_PERIOD_MASK (0xf << 16) 64 # define LCLK_SCALING_TIMER_PERIOD_SHIFT 16 65 66 #define RCU_PWR_GATING_CNTL_2 0x4a0 67 # define MPPU(x) ((x) << 0) 68 # define MPPU_MASK (0xffff << 0) 69 # define MPPU_SHIFT 0 70 # define MPPD(x) ((x) << 16) 71 # define MPPD_MASK (0xffff << 16) 72 # define MPPD_SHIFT 16 73 #define RCU_PWR_GATING_CNTL_3 0x4a4 74 # define DPPU(x) ((x) << 0) 75 # define DPPU_MASK (0xffff << 0) 76 # define DPPU_SHIFT 0 77 # define DPPD(x) ((x) << 16) 78 # define DPPD_MASK (0xffff << 16) 79 # define DPPD_SHIFT 16 80 #define RCU_PWR_GATING_CNTL_4 0x4a8 81 # define RT(x) ((x) << 0) 82 # define RT_MASK (0xffff << 0) 83 # define RT_SHIFT 0 84 # define IT(x) ((x) << 16) 85 # define IT_MASK (0xffff << 16) 86 # define IT_SHIFT 16 87 88 /* yes these two have the same address */ 89 #define RCU_PWR_GATING_CNTL_5 0x504 90 #define RCU_GPU_BOOST_DISABLE 0x508 91 92 #define MCU_M3ARB_INDEX 0x504 93 #define MCU_M3ARB_PARAMS 0x508 94 95 #define RCU_GNB_PWR_REP_TIMER_CNTL 0x50C 96 97 #define RCU_SclkDpmTdpLimit01 0x514 98 #define RCU_SclkDpmTdpLimit23 0x518 99 #define RCU_SclkDpmTdpLimit47 0x51C 100 #define RCU_SclkDpmTdpLimitPG 0x520 101 102 #define GNB_TDP_LIMIT 0x540 103 #define RCU_BOOST_MARGIN 0x544 104 #define RCU_THROTTLE_MARGIN 0x548 105 106 #define SMU_PCIE_PG_ARGS 0x58C 107 #define SMU_PCIE_PG_ARGS_2 0x598 108 #define SMU_PCIE_PG_ARGS_3 0x59C 109 110 /* mmio */ 111 #define RCU_STATUS 0x11c 112 # define GMC_PWR_GATER_BUSY (1 << 8) 113 # define GFX_PWR_GATER_BUSY (1 << 9) 114 # define UVD_PWR_GATER_BUSY (1 << 10) 115 # define PCIE_PWR_GATER_BUSY (1 << 11) 116 # define GMC_PWR_GATER_STATE (1 << 12) 117 # define GFX_PWR_GATER_STATE (1 << 13) 118 # define UVD_PWR_GATER_STATE (1 << 14) 119 # define PCIE_PWR_GATER_STATE (1 << 15) 120 # define GFX1_PWR_GATER_BUSY (1 << 16) 121 # define GFX2_PWR_GATER_BUSY (1 << 17) 122 # define GFX1_PWR_GATER_STATE (1 << 18) 123 # define GFX2_PWR_GATER_STATE (1 << 19) 124 125 #define GFX_INT_REQ 0x120 126 # define INT_REQ (1 << 0) 127 # define SERV_INDEX(x) ((x) << 1) 128 # define SERV_INDEX_MASK (0xff << 1) 129 # define SERV_INDEX_SHIFT 1 130 #define GFX_INT_STATUS 0x124 131 # define INT_ACK (1 << 0) 132 # define INT_DONE (1 << 1) 133 134 #define CG_SCLK_CNTL 0x600 135 # define SCLK_DIVIDER(x) ((x) << 0) 136 # define SCLK_DIVIDER_MASK (0x7f << 0) 137 # define SCLK_DIVIDER_SHIFT 0 138 #define CG_SCLK_STATUS 0x604 139 # define SCLK_OVERCLK_DETECT (1 << 2) 140 141 #define CG_DCLK_CNTL 0x610 142 # define DCLK_DIVIDER_MASK 0x7f 143 # define DCLK_DIR_CNTL_EN (1 << 8) 144 #define CG_DCLK_STATUS 0x614 145 # define DCLK_STATUS (1 << 0) 146 #define CG_VCLK_CNTL 0x618 147 # define VCLK_DIVIDER_MASK 0x7f 148 # define VCLK_DIR_CNTL_EN (1 << 8) 149 #define CG_VCLK_STATUS 0x61c 150 151 #define GENERAL_PWRMGT 0x63c 152 # define STATIC_PM_EN (1 << 1) 153 154 #define SCLK_PWRMGT_CNTL 0x644 155 # define SCLK_PWRMGT_OFF (1 << 0) 156 # define SCLK_LOW_D1 (1 << 1) 157 # define FIR_RESET (1 << 4) 158 # define FIR_FORCE_TREND_SEL (1 << 5) 159 # define FIR_TREND_MODE (1 << 6) 160 # define DYN_GFX_CLK_OFF_EN (1 << 7) 161 # define GFX_CLK_FORCE_ON (1 << 8) 162 # define GFX_CLK_REQUEST_OFF (1 << 9) 163 # define GFX_CLK_FORCE_OFF (1 << 10) 164 # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 165 # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 166 # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 167 # define GFX_VOLTAGE_CHANGE_EN (1 << 16) 168 # define GFX_VOLTAGE_CHANGE_MODE (1 << 17) 169 170 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 171 # define TARG_SCLK_INDEX(x) ((x) << 6) 172 # define TARG_SCLK_INDEX_MASK (0x7 << 6) 173 # define TARG_SCLK_INDEX_SHIFT 6 174 # define CURR_SCLK_INDEX(x) ((x) << 9) 175 # define CURR_SCLK_INDEX_MASK (0x7 << 9) 176 # define CURR_SCLK_INDEX_SHIFT 9 177 # define TARG_INDEX(x) ((x) << 12) 178 # define TARG_INDEX_MASK (0x7 << 12) 179 # define TARG_INDEX_SHIFT 12 180 # define CURR_INDEX(x) ((x) << 15) 181 # define CURR_INDEX_MASK (0x7 << 15) 182 # define CURR_INDEX_SHIFT 15 183 184 #define CG_SCLK_DPM_CTRL 0x684 185 # define SCLK_FSTATE_0_DIV(x) ((x) << 0) 186 # define SCLK_FSTATE_0_DIV_MASK (0x7f << 0) 187 # define SCLK_FSTATE_0_DIV_SHIFT 0 188 # define SCLK_FSTATE_0_VLD (1 << 7) 189 # define SCLK_FSTATE_1_DIV(x) ((x) << 8) 190 # define SCLK_FSTATE_1_DIV_MASK (0x7f << 8) 191 # define SCLK_FSTATE_1_DIV_SHIFT 8 192 # define SCLK_FSTATE_1_VLD (1 << 15) 193 # define SCLK_FSTATE_2_DIV(x) ((x) << 16) 194 # define SCLK_FSTATE_2_DIV_MASK (0x7f << 16) 195 # define SCLK_FSTATE_2_DIV_SHIFT 16 196 # define SCLK_FSTATE_2_VLD (1 << 23) 197 # define SCLK_FSTATE_3_DIV(x) ((x) << 24) 198 # define SCLK_FSTATE_3_DIV_MASK (0x7f << 24) 199 # define SCLK_FSTATE_3_DIV_SHIFT 24 200 # define SCLK_FSTATE_3_VLD (1U << 31) 201 #define CG_SCLK_DPM_CTRL_2 0x688 202 #define CG_GCOOR 0x68c 203 # define PHC(x) ((x) << 0) 204 # define PHC_MASK (0x1f << 0) 205 # define PHC_SHIFT 0 206 # define SDC(x) ((x) << 9) 207 # define SDC_MASK (0x3ff << 9) 208 # define SDC_SHIFT 9 209 # define SU(x) ((x) << 23) 210 # define SU_MASK (0xf << 23) 211 # define SU_SHIFT 23 212 # define DIV_ID(x) ((x) << 28) 213 # define DIV_ID_MASK (0x7 << 28) 214 # define DIV_ID_SHIFT 28 215 216 #define CG_FTV 0x690 217 #define CG_FFCT_0 0x694 218 # define UTC_0(x) ((x) << 0) 219 # define UTC_0_MASK (0x3ff << 0) 220 # define UTC_0_SHIFT 0 221 # define DTC_0(x) ((x) << 10) 222 # define DTC_0_MASK (0x3ff << 10) 223 # define DTC_0_SHIFT 10 224 225 #define CG_GIT 0x6d8 226 # define CG_GICST(x) ((x) << 0) 227 # define CG_GICST_MASK (0xffff << 0) 228 # define CG_GICST_SHIFT 0 229 # define CG_GIPOT(x) ((x) << 16) 230 # define CG_GIPOT_MASK (0xffff << 16) 231 # define CG_GIPOT_SHIFT 16 232 233 #define CG_SCLK_DPM_CTRL_3 0x6e0 234 # define FORCE_SCLK_STATE(x) ((x) << 0) 235 # define FORCE_SCLK_STATE_MASK (0x7 << 0) 236 # define FORCE_SCLK_STATE_SHIFT 0 237 # define FORCE_SCLK_STATE_EN (1 << 3) 238 # define GNB_TT(x) ((x) << 8) 239 # define GNB_TT_MASK (0xff << 8) 240 # define GNB_TT_SHIFT 8 241 # define GNB_THERMTHRO_MASK (1 << 16) 242 # define CNB_THERMTHRO_MASK_SCLK (1 << 17) 243 # define DPM_SCLK_ENABLE (1 << 18) 244 # define GNB_SLOW_FSTATE_0_MASK (1 << 23) 245 # define GNB_SLOW_FSTATE_0_SHIFT 23 246 # define FORCE_NB_PSTATE_1 (1U << 31) 247 248 #define CG_SSP 0x6e8 249 # define SST(x) ((x) << 0) 250 # define SST_MASK (0xffff << 0) 251 # define SST_SHIFT 0 252 # define SSTU(x) ((x) << 16) 253 # define SSTU_MASK (0xffff << 16) 254 # define SSTU_SHIFT 16 255 256 #define CG_ACPI_CNTL 0x70c 257 # define SCLK_ACPI_DIV(x) ((x) << 0) 258 # define SCLK_ACPI_DIV_MASK (0x7f << 0) 259 # define SCLK_ACPI_DIV_SHIFT 0 260 261 #define CG_SCLK_DPM_CTRL_4 0x71c 262 # define DC_HDC(x) ((x) << 14) 263 # define DC_HDC_MASK (0x3fff << 14) 264 # define DC_HDC_SHIFT 14 265 # define DC_HU(x) ((x) << 28) 266 # define DC_HU_MASK (0xfU << 28) 267 # define DC_HU_SHIFT 28 268 #define CG_SCLK_DPM_CTRL_5 0x720 269 # define SCLK_FSTATE_BOOTUP(x) ((x) << 0) 270 # define SCLK_FSTATE_BOOTUP_MASK (0x7 << 0) 271 # define SCLK_FSTATE_BOOTUP_SHIFT 0 272 # define TT_TP(x) ((x) << 3) 273 # define TT_TP_MASK (0xffff << 3) 274 # define TT_TP_SHIFT 3 275 # define TT_TU(x) ((x) << 19) 276 # define TT_TU_MASK (0xff << 19) 277 # define TT_TU_SHIFT 19 278 #define CG_SCLK_DPM_CTRL_6 0x724 279 #define CG_AT_0 0x728 280 # define CG_R(x) ((x) << 0) 281 # define CG_R_MASK (0xffff << 0) 282 # define CG_R_SHIFT 0 283 # define CG_L(x) ((x) << 16) 284 # define CG_L_MASK (0xffffU << 16) 285 # define CG_L_SHIFT 16 286 #define CG_AT_1 0x72c 287 #define CG_AT_2 0x730 288 #define CG_THERMAL_INT 0x734 289 #define DIG_THERM_INTH(x) ((x) << 8) 290 #define DIG_THERM_INTH_MASK 0x0000FF00 291 #define DIG_THERM_INTH_SHIFT 8 292 #define DIG_THERM_INTL(x) ((x) << 16) 293 #define DIG_THERM_INTL_MASK 0x00FF0000 294 #define DIG_THERM_INTL_SHIFT 16 295 #define THERM_INT_MASK_HIGH (1 << 24) 296 #define THERM_INT_MASK_LOW (1 << 25) 297 #define CG_AT_3 0x738 298 #define CG_AT_4 0x73c 299 #define CG_AT_5 0x740 300 #define CG_AT_6 0x744 301 #define CG_AT_7 0x748 302 303 #define CG_BSP_0 0x750 304 # define BSP(x) ((x) << 0) 305 # define BSP_MASK (0xffff << 0) 306 # define BSP_SHIFT 0 307 # define BSU(x) ((x) << 16) 308 # define BSU_MASK (0xf << 16) 309 # define BSU_SHIFT 16 310 311 #define CG_CG_VOLTAGE_CNTL 0x770 312 # define REQ (1 << 0) 313 # define LEVEL(x) ((x) << 1) 314 # define LEVEL_MASK (0x3 << 1) 315 # define LEVEL_SHIFT 1 316 # define CG_VOLTAGE_EN (1 << 3) 317 # define FORCE (1 << 4) 318 # define PERIOD(x) ((x) << 8) 319 # define PERIOD_MASK (0xffff << 8) 320 # define PERIOD_SHIFT 8 321 # define UNIT(x) ((x) << 24) 322 # define UNIT_MASK (0xf << 24) 323 # define UNIT_SHIFT 24 324 325 #define CG_ACPI_VOLTAGE_CNTL 0x780 326 # define ACPI_VOLTAGE_EN (1 << 8) 327 328 #define CG_DPM_VOLTAGE_CNTL 0x788 329 # define DPM_STATE0_LEVEL_MASK (0x3 << 0) 330 # define DPM_STATE0_LEVEL_SHIFT 0 331 # define DPM_VOLTAGE_EN (1 << 16) 332 333 #define CG_PWR_GATING_CNTL 0x7ac 334 # define DYN_PWR_DOWN_EN (1 << 0) 335 # define ACPI_PWR_DOWN_EN (1 << 1) 336 # define GFX_CLK_OFF_PWR_DOWN_EN (1 << 2) 337 # define IOC_DISGPU_PWR_DOWN_EN (1 << 3) 338 # define FORCE_POWR_ON (1 << 4) 339 # define PGP(x) ((x) << 8) 340 # define PGP_MASK (0xffff << 8) 341 # define PGP_SHIFT 8 342 # define PGU(x) ((x) << 24) 343 # define PGU_MASK (0xf << 24) 344 # define PGU_SHIFT 24 345 346 #define CG_CGTT_LOCAL_0 0x7d0 347 #define CG_CGTT_LOCAL_1 0x7d4 348 349 #define DEEP_SLEEP_CNTL 0x818 350 # define R_DIS (1 << 3) 351 # define HS(x) ((x) << 4) 352 # define HS_MASK (0xfff << 4) 353 # define HS_SHIFT 4 354 # define ENABLE_DS (1U << 31) 355 #define DEEP_SLEEP_CNTL2 0x81c 356 # define LB_UFP_EN (1 << 0) 357 # define INOUT_C(x) ((x) << 4) 358 # define INOUT_C_MASK (0xff << 4) 359 # define INOUT_C_SHIFT 4 360 361 #define CG_SCRATCH2 0x824 362 363 #define CG_SCLK_DPM_CTRL_11 0x830 364 365 #define HW_REV 0x5564 366 # define ATI_REV_ID_MASK (0xfU << 28) 367 # define ATI_REV_ID_SHIFT 28 368 /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ 369 370 #define DOUT_SCRATCH3 0x611c 371 372 #define GB_ADDR_CONFIG 0x98f8 373 374 #endif 375
Indexes created Sun Sep 21 16:09:51 GMT 2025