1 /* $NetBSD: drm_dsc.h,v 1.2 2021/12/18 23:45:45 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: MIT 4 * Copyright (C) 2018 Intel Corp. 5 * 6 * Authors: 7 * Manasi Navare <manasi.d.navare (at) intel.com> 8 */ 9 10 #ifndef DRM_DSC_H_ 11 #define DRM_DSC_H_ 12 13 #include <drm/drm_dp_helper.h> 14 15 /* VESA Display Stream Compression DSC 1.2 constants */ 16 #define DSC_NUM_BUF_RANGES 15 17 #define DSC_MUX_WORD_SIZE_8_10_BPC 48 18 #define DSC_MUX_WORD_SIZE_12_BPC 64 19 #define DSC_RC_PIXELS_PER_GROUP 3 20 #define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 21 #define DSC_RANGE_BPG_OFFSET_MASK 0x3f 22 23 /* DSC Rate Control Constants */ 24 #define DSC_RC_MODEL_SIZE_CONST 8192 25 #define DSC_RC_EDGE_FACTOR_CONST 6 26 #define DSC_RC_TGT_OFFSET_HI_CONST 3 27 #define DSC_RC_TGT_OFFSET_LO_CONST 3 28 29 /* DSC PPS constants and macros */ 30 #define DSC_PPS_VERSION_MAJOR_SHIFT 4 31 #define DSC_PPS_BPC_SHIFT 4 32 #define DSC_PPS_MSB_SHIFT 8 33 #define DSC_PPS_LSB_MASK (0xFF << 0) 34 #define DSC_PPS_BPP_HIGH_MASK (0x3 << 8) 35 #define DSC_PPS_VBR_EN_SHIFT 2 36 #define DSC_PPS_SIMPLE422_SHIFT 3 37 #define DSC_PPS_CONVERT_RGB_SHIFT 4 38 #define DSC_PPS_BLOCK_PRED_EN_SHIFT 5 39 #define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8) 40 #define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8) 41 #define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4 42 #define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 43 #define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 44 #define DSC_PPS_NATIVE_420_SHIFT 1 45 #define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16 46 #define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0 47 #define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13 48 49 /** 50 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters 51 * 52 * This defines different rate control parameters used by the DSC engine 53 * to compress the frame. 54 */ 55 struct drm_dsc_rc_range_parameters { 56 /** 57 * @range_min_qp: Min Quantization Parameters allowed for this range 58 */ 59 u8 range_min_qp; 60 /** 61 * @range_max_qp: Max Quantization Parameters allowed for this range 62 */ 63 u8 range_max_qp; 64 /** 65 * @range_bpg_offset: 66 * Bits/group offset to apply to target for this group 67 */ 68 u8 range_bpg_offset; 69 }; 70 71 /** 72 * struct drm_dsc_config - Parameters required to configure DSC 73 * 74 * Driver populates this structure with all the parameters required 75 * to configure the display stream compression on the source. 76 */ 77 struct drm_dsc_config { 78 /** 79 * @line_buf_depth: 80 * Bits per component for previous reconstructed line buffer 81 */ 82 u8 line_buf_depth; 83 /** 84 * @bits_per_component: Bits per component to code (8/10/12) 85 */ 86 u8 bits_per_component; 87 /** 88 * @convert_rgb: 89 * Flag to indicate if RGB - YCoCg conversion is needed 90 * True if RGB input, False if YCoCg input 91 */ 92 bool convert_rgb; 93 /** 94 * @slice_count: Number fo slices per line used by the DSC encoder 95 */ 96 u8 slice_count; 97 /** 98 * @slice_width: Width of each slice in pixels 99 */ 100 u16 slice_width; 101 /** 102 * @slice_height: Slice height in pixels 103 */ 104 u16 slice_height; 105 /** 106 * @simple_422: True if simple 4_2_2 mode is enabled else False 107 */ 108 bool simple_422; 109 /** 110 * @pic_width: Width of the input display frame in pixels 111 */ 112 u16 pic_width; 113 /** 114 * @pic_height: Vertical height of the input display frame 115 */ 116 u16 pic_height; 117 /** 118 * @rc_tgt_offset_high: 119 * Offset to bits/group used by RC to determine QP adjustment 120 */ 121 u8 rc_tgt_offset_high; 122 /** 123 * @rc_tgt_offset_low: 124 * Offset to bits/group used by RC to determine QP adjustment 125 */ 126 u8 rc_tgt_offset_low; 127 /** 128 * @bits_per_pixel: 129 * Target bits per pixel with 4 fractional bits, bits_per_pixel << 4 130 */ 131 u16 bits_per_pixel; 132 /** 133 * @rc_edge_factor: 134 * Factor to determine if an edge is present based on the bits produced 135 */ 136 u8 rc_edge_factor; 137 /** 138 * @rc_quant_incr_limit1: 139 * Slow down incrementing once the range reaches this value 140 */ 141 u8 rc_quant_incr_limit1; 142 /** 143 * @rc_quant_incr_limit0: 144 * Slow down incrementing once the range reaches this value 145 */ 146 u8 rc_quant_incr_limit0; 147 /** 148 * @initial_xmit_delay: 149 * Number of pixels to delay the initial transmission 150 */ 151 u16 initial_xmit_delay; 152 /** 153 * @initial_dec_delay: 154 * Initial decoder delay, number of pixel times that the decoder 155 * accumulates data in its rate buffer before starting to decode 156 * and output pixels. 157 */ 158 u16 initial_dec_delay; 159 /** 160 * @block_pred_enable: 161 * True if block prediction is used to code any groups within the 162 * picture. False if BP not used 163 */ 164 bool block_pred_enable; 165 /** 166 * @first_line_bpg_offset: 167 * Number of additional bits allocated for each group on the first 168 * line of slice. 169 */ 170 u8 first_line_bpg_offset; 171 /** 172 * @initial_offset: Value to use for RC model offset at slice start 173 */ 174 u16 initial_offset; 175 /** 176 * @rc_buf_thresh: Thresholds defining each of the buffer ranges 177 */ 178 u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; 179 /** 180 * @rc_range_params: 181 * Parameters for each of the RC ranges defined in 182 * &struct drm_dsc_rc_range_parameters 183 */ 184 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 185 /** 186 * @rc_model_size: Total size of RC model 187 */ 188 u16 rc_model_size; 189 /** 190 * @flatness_min_qp: Minimum QP where flatness information is sent 191 */ 192 u8 flatness_min_qp; 193 /** 194 * @flatness_max_qp: Maximum QP where flatness information is sent 195 */ 196 u8 flatness_max_qp; 197 /** 198 * @initial_scale_value: Initial value for the scale factor 199 */ 200 u8 initial_scale_value; 201 /** 202 * @scale_decrement_interval: 203 * Specifies number of group times between decrementing the scale factor 204 * at beginning of a slice. 205 */ 206 u16 scale_decrement_interval; 207 /** 208 * @scale_increment_interval: 209 * Number of group times between incrementing the scale factor value 210 * used at the beginning of a slice. 211 */ 212 u16 scale_increment_interval; 213 /** 214 * @nfl_bpg_offset: Non first line BPG offset to be used 215 */ 216 u16 nfl_bpg_offset; 217 /** 218 * @slice_bpg_offset: BPG offset used to enforce slice bit 219 */ 220 u16 slice_bpg_offset; 221 /** 222 * @final_offset: Final RC linear transformation offset value 223 */ 224 u16 final_offset; 225 /** 226 * @vbr_enable: True if VBR mode is enabled, false if disabled 227 */ 228 bool vbr_enable; 229 /** 230 * @mux_word_size: Mux word size (in bits) for SSM mode 231 */ 232 u8 mux_word_size; 233 /** 234 * @slice_chunk_size: 235 * The (max) size in bytes of the "chunks" that are used in slice 236 * multiplexing. 237 */ 238 u16 slice_chunk_size; 239 /** 240 * @rc_bits: Rate control buffer size in bits 241 */ 242 u16 rc_bits; 243 /** 244 * @dsc_version_minor: DSC minor version 245 */ 246 u8 dsc_version_minor; 247 /** 248 * @dsc_version_major: DSC major version 249 */ 250 u8 dsc_version_major; 251 /** 252 * @native_422: True if Native 4:2:2 supported, else false 253 */ 254 bool native_422; 255 /** 256 * @native_420: True if Native 4:2:0 supported else false. 257 */ 258 bool native_420; 259 /** 260 * @second_line_bpg_offset: 261 * Additional bits/grp for seconnd line of slice for native 4:2:0 262 */ 263 u8 second_line_bpg_offset; 264 /** 265 * @nsl_bpg_offset: 266 * Num of bits deallocated for each grp that is not in second line of 267 * slice 268 */ 269 u16 nsl_bpg_offset; 270 /** 271 * @second_line_offset_adj: 272 * Offset adjustment for second line in Native 4:2:0 mode 273 */ 274 u16 second_line_offset_adj; 275 }; 276 277 /** 278 * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set 279 * 280 * The VESA DSC standard defines picture parameter set (PPS) which display 281 * stream compression encoders must communicate to decoders. 282 * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in 283 * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2. 284 * The PPS fields that span over more than a byte should be stored in Big Endian 285 * format. 286 */ 287 struct drm_dsc_picture_parameter_set { 288 /** 289 * @dsc_version: 290 * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC 291 * PPS0[7:4] - dsc_version_major: Contains major version of DSC 292 */ 293 u8 dsc_version; 294 /** 295 * @pps_identifier: 296 * PPS1[7:0] - Application specific identifier that can be 297 * used to differentiate between different PPS tables. 298 */ 299 u8 pps_identifier; 300 /** 301 * @pps_reserved: 302 * PPS2[7:0]- RESERVED Byte 303 */ 304 u8 pps_reserved; 305 /** 306 * @pps_3: 307 * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to 308 * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits, 309 * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits, 310 * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2. 311 * PPS3[7:4] - bits_per_component: Bits per component for the original 312 * pixels of the encoded picture. 313 * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2) 314 * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also 315 * allowed only when dsc_minor_version = 0x2) 316 */ 317 u8 pps_3; 318 /** 319 * @pps_4: 320 * PPS4[1:0] -These are the most significant 2 bits of 321 * compressed BPP bits_per_pixel[9:0] syntax element. 322 * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled 323 * PPS4[3] - simple_422: Indicates if decoder drops samples to 324 * reconstruct the 4:2:2 picture. 325 * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is 326 * active. 327 * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any 328 * groups in picture 329 * PPS4[7:6] - Reseved bits 330 */ 331 u8 pps_4; 332 /** 333 * @bits_per_pixel_low: 334 * PPS5[7:0] - This indicates the lower significant 8 bits of 335 * the compressed BPP bits_per_pixel[9:0] element. 336 */ 337 u8 bits_per_pixel_low; 338 /** 339 * @pic_height: 340 * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows 341 * within the raster. 342 */ 343 __be16 pic_height; 344 /** 345 * @pic_width: 346 * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within 347 * the raster. 348 */ 349 __be16 pic_width; 350 /** 351 * @slice_height: 352 * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels. 353 */ 354 __be16 slice_height; 355 /** 356 * @slice_width: 357 * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels. 358 */ 359 __be16 slice_width; 360 /** 361 * @chunk_size: 362 * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks 363 * that are used for slice multiplexing. 364 */ 365 __be16 chunk_size; 366 /** 367 * @initial_xmit_delay_high: 368 * PPS16[1:0] - Most Significant two bits of initial transmission delay. 369 * It specifies the number of pixel times that the encoder waits before 370 * transmitting data from its rate buffer. 371 * PPS16[7:2] - Reserved 372 */ 373 u8 initial_xmit_delay_high; 374 /** 375 * @initial_xmit_delay_low: 376 * PPS17[7:0] - Least significant 8 bits of initial transmission delay. 377 */ 378 u8 initial_xmit_delay_low; 379 /** 380 * @initial_dec_delay: 381 * 382 * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number 383 * of pixel times that the decoder accumulates data in its rate buffer 384 * before starting to decode and output pixels. 385 */ 386 __be16 initial_dec_delay; 387 /** 388 * @pps20_reserved: 389 * 390 * PPS20[7:0] - Reserved 391 */ 392 u8 pps20_reserved; 393 /** 394 * @initial_scale_value: 395 * PPS21[5:0] - Initial rcXformScale factor used at beginning 396 * of a slice. 397 * PPS21[7:6] - Reserved 398 */ 399 u8 initial_scale_value; 400 /** 401 * @scale_increment_interval: 402 * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing 403 * the rcXformScale factor at end of a slice. 404 */ 405 __be16 scale_increment_interval; 406 /** 407 * @scale_decrement_interval_high: 408 * PPS24[3:0] - Higher 4 bits indicating number of group times between 409 * decrementing the rcXformScale factor at beginning of a slice. 410 * PPS24[7:4] - Reserved 411 */ 412 u8 scale_decrement_interval_high; 413 /** 414 * @scale_decrement_interval_low: 415 * PPS25[7:0] - Lower 8 bits of scale decrement interval 416 */ 417 u8 scale_decrement_interval_low; 418 /** 419 * @pps26_reserved: 420 * PPS26[7:0] 421 */ 422 u8 pps26_reserved; 423 /** 424 * @first_line_bpg_offset: 425 * PPS27[4:0] - Number of additional bits that are allocated 426 * for each group on first line of a slice. 427 * PPS27[7:5] - Reserved 428 */ 429 u8 first_line_bpg_offset; 430 /** 431 * @nfl_bpg_offset: 432 * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits 433 * deallocated for each group for groups after the first line of slice. 434 */ 435 __be16 nfl_bpg_offset; 436 /** 437 * @slice_bpg_offset: 438 * PPS30, PPS31[7:0] - Number of bits that are deallocated for each 439 * group to enforce the slice constraint. 440 */ 441 __be16 slice_bpg_offset; 442 /** 443 * @initial_offset: 444 * PPS32,33[7:0] - Initial value for rcXformOffset 445 */ 446 __be16 initial_offset; 447 /** 448 * @final_offset: 449 * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset 450 */ 451 __be16 final_offset; 452 /** 453 * @flatness_min_qp: 454 * PPS36[4:0] - Minimum QP at which flatness is signaled and 455 * flatness QP adjustment is made. 456 * PPS36[7:5] - Reserved 457 */ 458 u8 flatness_min_qp; 459 /** 460 * @flatness_max_qp: 461 * PPS37[4:0] - Max QP at which flatness is signalled and 462 * the flatness adjustment is made. 463 * PPS37[7:5] - Reserved 464 */ 465 u8 flatness_max_qp; 466 /** 467 * @rc_model_size: 468 * PPS38,39[7:0] - Number of bits within RC Model. 469 */ 470 __be16 rc_model_size; 471 /** 472 * @rc_edge_factor: 473 * PPS40[3:0] - Ratio of current activity vs, previous 474 * activity to determine presence of edge. 475 * PPS40[7:4] - Reserved 476 */ 477 u8 rc_edge_factor; 478 /** 479 * @rc_quant_incr_limit0: 480 * PPS41[4:0] - QP threshold used in short term RC 481 * PPS41[7:5] - Reserved 482 */ 483 u8 rc_quant_incr_limit0; 484 /** 485 * @rc_quant_incr_limit1: 486 * PPS42[4:0] - QP threshold used in short term RC 487 * PPS42[7:5] - Reserved 488 */ 489 u8 rc_quant_incr_limit1; 490 /** 491 * @rc_tgt_offset: 492 * PPS43[3:0] - Lower end of the variability range around the target 493 * bits per group that is allowed by short term RC. 494 * PPS43[7:4]- Upper end of the variability range around the target 495 * bits per group that i allowed by short term rc. 496 */ 497 u8 rc_tgt_offset; 498 /** 499 * @rc_buf_thresh: 500 * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for 501 * the 15 ranges defined by 14 thresholds. 502 */ 503 u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; 504 /** 505 * @rc_range_parameters: 506 * PPS58[7:0] - PPS87[7:0] 507 * Parameters that correspond to each of the 15 ranges. 508 */ 509 __be16 rc_range_parameters[DSC_NUM_BUF_RANGES]; 510 /** 511 * @native_422_420: 512 * PPS88[0] - 0 = Native 4:2:2 not used 513 * 1 = Native 4:2:2 used 514 * PPS88[1] - 0 = Native 4:2:0 not use 515 * 1 = Native 4:2:0 used 516 * PPS88[7:2] - Reserved 6 bits 517 */ 518 u8 native_422_420; 519 /** 520 * @second_line_bpg_offset: 521 * PPS89[4:0] - Additional bits/group budget for the 522 * second line of a slice in Native 4:2:0 mode. 523 * Set to 0 if DSC minor version is 1 or native420 is 0. 524 * PPS89[7:5] - Reserved 525 */ 526 u8 second_line_bpg_offset; 527 /** 528 * @nsl_bpg_offset: 529 * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated 530 * for each group that is not in the second line of a slice. 531 */ 532 __be16 nsl_bpg_offset; 533 /** 534 * @second_line_offset_adj: 535 * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second 536 * line in Native 4:2:0 mode. 537 */ 538 __be16 second_line_offset_adj; 539 /** 540 * @pps_long_94_reserved: 541 * PPS 94, 95, 96, 97 - Reserved 542 */ 543 u32 pps_long_94_reserved; 544 /** 545 * @pps_long_98_reserved: 546 * PPS 98, 99, 100, 101 - Reserved 547 */ 548 u32 pps_long_98_reserved; 549 /** 550 * @pps_long_102_reserved: 551 * PPS 102, 103, 104, 105 - Reserved 552 */ 553 u32 pps_long_102_reserved; 554 /** 555 * @pps_long_106_reserved: 556 * PPS 106, 107, 108, 109 - reserved 557 */ 558 u32 pps_long_106_reserved; 559 /** 560 * @pps_long_110_reserved: 561 * PPS 110, 111, 112, 113 - reserved 562 */ 563 u32 pps_long_110_reserved; 564 /** 565 * @pps_long_114_reserved: 566 * PPS 114 - 117 - reserved 567 */ 568 u32 pps_long_114_reserved; 569 /** 570 * @pps_long_118_reserved: 571 * PPS 118 - 121 - reserved 572 */ 573 u32 pps_long_118_reserved; 574 /** 575 * @pps_long_122_reserved: 576 * PPS 122- 125 - reserved 577 */ 578 u32 pps_long_122_reserved; 579 /** 580 * @pps_short_126_reserved: 581 * PPS 126, 127 - reserved 582 */ 583 __be16 pps_short_126_reserved; 584 } __packed; 585 586 /** 587 * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter 588 * Set Metadata 589 * 590 * This structure represents the DSC PPS infoframe required to send the Picture 591 * Parameter Set metadata required before enabling VESA Display Stream 592 * Compression. This is based on the DP Secondary Data Packet structure and 593 * comprises of SDP Header as defined &struct struct dp_sdp_header in drm_dp_helper.h 594 * and PPS payload defined in &struct drm_dsc_picture_parameter_set. 595 * 596 * @pps_header: Header for PPS as per DP SDP header format of type 597 * &struct dp_sdp_header 598 * @pps_payload: PPS payload fields as per DSC specification Table 4-1 599 * as represented in &struct drm_dsc_picture_parameter_set 600 */ 601 struct drm_dsc_pps_infoframe { 602 struct dp_sdp_header pps_header; 603 struct drm_dsc_picture_parameter_set pps_payload; 604 } __packed; 605 606 void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); 607 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, 608 const struct drm_dsc_config *dsc_cfg); 609 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); 610 611 #endif /* _DRM_DSC_H_ */ 612
Indexes created Sun Sep 21 14:09:52 GMT 2025