1 /* $NetBSD: dwcsatareg.h,v 1.1 2026/06/14 00:02:35 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Synopsys DesignWare Cores SATA-II AHB host as integrated in the 33 * AMCC/AppliedMicro PPC460EX 34 */ 35 36 #ifndef _IBM4XX_DWCSATAREG_H_ 37 #define _IBM4XX_DWCSATAREG_H_ 38 39 #define DWCSATA_SIZE 0x800 /* whole block, incl. DMADR window */ 40 41 /* 42 * ATA taskfile shadow registers (SATA0_CDR0-CDR7), 4-byte stride, in 43 * the standard wd_* order: data, error/features, seccnt, sector, 44 * cyl_lo, cyl_hi, sdh, command/status. 45 */ 46 #define DWCSATA_CDR_BASE 0x00 47 #define DWCSATA_CDR_STRIDE 4 48 49 #define DWCSATA_CLR0 0x20 /* altstatus / device control */ 50 51 /* SATA status and control registers (SATA0_SCR0-SCR4) */ 52 #define DWCSATA_SSTATUS 0x24 53 #define DWCSATA_SERROR 0x28 /* write 1s to clear */ 54 #define DWCSATA_SCONTROL 0x2c 55 #define DWCSATA_SACTIVE 0x30 56 #define DWCSATA_SNOTIFICATION 0x34 57 58 /* 59 * DWC-specific control block. (NCQ) DMA registers and 60 * DMACR/DBTSR only matter on the DMA data path. 61 */ 62 #define DWCSATA_FPTAGR 0x64 /* first-party DMA tag */ 63 #define DWCSATA_FPBOR 0x68 /* first-party DMA buffer offset */ 64 #define DWCSATA_FPTCR 0x6c /* first-party DMA transfer count */ 65 66 #define DWCSATA_DMACR 0x70 /* DMA channel control */ 67 #define DWCSATA_DMACR_TXCHEN 0x00000001 /* TX channel enable */ 68 #define DWCSATA_DMACR_RXCHEN 0x00000002 /* RX channel enable */ 69 #define DWCSATA_DMACR_TXMODE 0x00000004 /* close TX FIS on TXCHEN clear */ 70 /* clears both channel enables; TXMODE is what U-Boot/Linux run with */ 71 #define DWCSATA_DMACR_TXRXCH_CLEAR DWCSATA_DMACR_TXMODE 72 /* TXMODE must accompany every DMACR write, including the RMW clears */ 73 #define DWCSATA_DMACR_TX_START (DWCSATA_DMACR_TXCHEN | DWCSATA_DMACR_TXMODE) 74 #define DWCSATA_DMACR_RX_START (DWCSATA_DMACR_RXCHEN | DWCSATA_DMACR_TXMODE) 75 #define DWCSATA_DMACR_TX_CLEAR(v) \ 76 (((v) & ~DWCSATA_DMACR_TXCHEN) | DWCSATA_DMACR_TXMODE) 77 #define DWCSATA_DMACR_RX_CLEAR(v) \ 78 (((v) & ~DWCSATA_DMACR_RXCHEN) | DWCSATA_DMACR_TXMODE) 79 80 #define DWCSATA_DBTSR 0x74 /* DMA burst transaction size */ 81 #define DWCSATA_DBTSR_MWR(bytes) (((bytes) / 4) & 0x01ff) 82 #define DWCSATA_DBTSR_MRD(bytes) ((((bytes) / 4) & 0x01ff) << 16) 83 84 #define DWCSATA_INTPR 0x78 /* interrupt pending, write 1 clears */ 85 #define DWCSATA_INTPR_DMAT 0x00000001 /* DMA transfer done */ 86 #define DWCSATA_INTPR_NEWFP 0x00000002 /* new first-party DMA FIS */ 87 #define DWCSATA_INTPR_PMABRT 0x00000004 /* power mgmt request aborted */ 88 #define DWCSATA_INTPR_ERR 0x00000008 /* SError & ERRMR nonzero */ 89 #define DWCSATA_INTPR_NEWBIST 0x00000010 /* BIST activate FIS received */ 90 #define DWCSATA_INTPR_PRIMERR 0x00000020 /* link layer primitive error */ 91 #define DWCSATA_INTPR_CMDABORT 0x00000040 /* Reg/SDB FIS w/ Status.ERR=1 */ 92 #define DWCSATA_INTPR_CMDGOOD 0x00000080 /* Reg/SDB FIS w/ Status.ERR=0 */ 93 #define DWCSATA_INTPR_ERRADDR 0x07ff0000 /* AHB slave bad-access addr bits: 94 haddr[21:31] of the offending 95 access (0x3ff = dma_finish_tx 96 with nothing in DMADR) */ 97 #define DWCSATA_INTPR_ERRADDR_GET(v) (((v) & DWCSATA_INTPR_ERRADDR) >> 16) 98 #define DWCSATA_INTPR_IPF 0x10000000 /* ATA interrupt flag (D2H intrq) */ 99 100 #define DWCSATA_INTMR 0x7c /* interrupt mask, 1 = enabled */ 101 #define DWCSATA_INTMR_DMATM 0x00000001 102 #define DWCSATA_INTMR_NEWFPM 0x00000002 103 #define DWCSATA_INTMR_PMABRTM 0x00000004 104 #define DWCSATA_INTMR_ERRM 0x00000008 105 #define DWCSATA_INTMR_NEWBISTM 0x00000010 106 107 #define DWCSATA_ERRMR 0x80 /* SError bits allowed into INTPR_ERR */ 108 #define DWCSATA_ERRMR_ERR_BITS 0x0fff0f03 /* all error (non-DIAG) bits */ 109 110 #define DWCSATA_LLCR 0x84 /* link layer control */ 111 #define DWCSATA_LLCR_SCRAMEN 0x00000001 /* scrambler enable */ 112 #define DWCSATA_LLCR_DESCRAMEN 0x00000002 /* descrambler enable */ 113 #define DWCSATA_LLCR_RPDEN 0x00000004 /* random pattern (BIST) enable */ 114 115 /* BIST registers (0x88-0xb4 area per the Synopsys layout) not listed */ 116 117 #define DWCSATA_TESTR 0xf4 /* test mode */ 118 #define DWCSATA_VERSIONR 0xf8 /* core version, 4 ASCII chars */ 119 #define DWCSATA_IDR 0xfc /* core ID; reset value 0 on 460EX! */ 120 121 /* 122 * DMA data FIFO window 123 */ 124 #define DWCSATA_DMADR 0x400 125 #define DWCSATA_DMADR_PHYS(base) ((uint32_t)(base) + DWCSATA_DMADR) 126 127 #endif /* _IBM4XX_DWCSATAREG_H_ */ 128
Indexes created Tue Jul 07 00:25:39 UTC 2026