1 /* $NetBSD: dmacreg.h,v 1.6 2025/06/19 12:38:16 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <mips/cpuregs.h> 33 34 typedef u_int64_t dmatag_t; 35 36 #define DMAC_BLOCK_SIZE 16 37 #define DMAC_SLICE_SIZE 128 38 #define DMAC_TRANSFER_QWCMAX 0xffff 39 40 /* all register length are 32bit */ 41 #define DMAC_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000) 42 #define DMAC_REGSIZE 0x00010000 43 44 /* 45 * DMAC common registers. 46 */ 47 #define D_CTRL_REG MIPS_PHYS_TO_KSEG1(0x1000e000) /* DMA control */ 48 #define D_STAT_REG MIPS_PHYS_TO_KSEG1(0x1000e010) /* interrupt status */ 49 #define D_PCR_REG MIPS_PHYS_TO_KSEG1(0x1000e020) /* priority control */ 50 #define D_SQWC_REG MIPS_PHYS_TO_KSEG1(0x1000e030) /* interleave size */ 51 #define D_RBOR_REG MIPS_PHYS_TO_KSEG1(0x1000e040) /* ring buffer addr */ 52 #define D_RBSR_REG MIPS_PHYS_TO_KSEG1(0x1000e050) /* ring buffer size */ 53 #define D_STADR_REG MIPS_PHYS_TO_KSEG1(0x1000e060) /* stall address */ 54 #define D_ENABLER_REG MIPS_PHYS_TO_KSEG1(0x1000f520) /* DMA enable (r) */ 55 #define D_ENABLEW_REG MIPS_PHYS_TO_KSEG1(0x1000f590) /* DMA enable (w) */ 56 57 /* 58 * Channel registers. (10ch) 59 */ 60 #define DMA_CH_VIF0 0 /* to (priority 0) */ 61 #define DMA_CH_VIF1 1 /* both */ 62 #define DMA_CH_GIF 2 /* to */ 63 #define DMA_CH_FROMIPU 3 64 #define DMA_CH_TOIPU 4 65 #define DMA_CH_SIF0 5 /* from */ 66 #define DMA_CH_SIF1 6 /* to */ 67 #define DMA_CH_SIF2 7 /* both (priority 1) */ 68 #define DMA_CH_FROMSPR 8 /* burst channel */ 69 #define DMA_CH_TOSPR 9 /* burst channel */ 70 #define DMA_CH_VALID(x) (((x) >= 0) && ((x) <= 9)) 71 72 #define D_CHCR_OFS 0x00 73 #define D_MADR_OFS 0x10 74 #define D_QWC_OFS 0x20 75 #define D_TADR_OFS 0x30 76 #define D_ASR0_OFS 0x40 77 #define D_ASR1_OFS 0x50 78 #define D_SADR_OFS 0x80 79 80 #define D0_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000) 81 #define D1_REGBASE MIPS_PHYS_TO_KSEG1(0x10009000) 82 #define D2_REGBASE MIPS_PHYS_TO_KSEG1(0x1000a000) 83 #define D3_REGBASE MIPS_PHYS_TO_KSEG1(0x1000b000) 84 #define D4_REGBASE MIPS_PHYS_TO_KSEG1(0x1000b400) 85 #define D5_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c000) 86 #define D6_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c400) 87 #define D7_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c800) 88 #define D8_REGBASE MIPS_PHYS_TO_KSEG1(0x1000d000) 89 #define D9_REGBASE MIPS_PHYS_TO_KSEG1(0x1000d400) 90 91 #define D_CHCR_REG(base) (base) 92 #define D_MADR_REG(base) (base + D_MADR_OFS) 93 #define D_QWC_REG(base) (base + D_QWC_OFS) 94 #define D_TADR_REG(base) (base + D_TADR_OFS) 95 #define D_ASR0_REG(base) (base + D_ASR0_OFS) 96 #define D_ASR1_REG(base) (base + D_ASR1_OFS) 97 #define D_SADR_REG(base) (base + D_SADR_OFS) 98 99 #define D0_CHCR_REG MIPS_PHYS_TO_KSEG1(0x10008000) 100 #define D0_MADR_REG MIPS_PHYS_TO_KSEG1(0x10008010) 101 #define D0_QWC_REG MIPS_PHYS_TO_KSEG1(0x10008020) 102 #define D0_TADR_REG MIPS_PHYS_TO_KSEG1(0x10008030) 103 #define D0_ASR0_REG MIPS_PHYS_TO_KSEG1(0x10008040) 104 #define D0_ASR1_REG MIPS_PHYS_TO_KSEG1(0x10008050) 105 106 #define D1_CHCR_REG MIPS_PHYS_TO_KSEG1(0x10009000) 107 #define D1_MADR_REG MIPS_PHYS_TO_KSEG1(0x10009010) 108 #define D1_QWC_REG MIPS_PHYS_TO_KSEG1(0x10009020) 109 #define D1_TADR_REG MIPS_PHYS_TO_KSEG1(0x10009030) 110 #define D1_ASR0_REG MIPS_PHYS_TO_KSEG1(0x10009040) 111 #define D1_ASR1_REG MIPS_PHYS_TO_KSEG1(0x10009050) 112 113 #define D2_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000a000) 114 #define D2_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000a010) 115 #define D2_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000a020) 116 #define D2_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000a030) 117 #define D2_ASR0_REG MIPS_PHYS_TO_KSEG1(0x1000a040) 118 #define D2_ASR1_REG MIPS_PHYS_TO_KSEG1(0x1000a050) 119 120 #define D3_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000b000) 121 #define D3_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000b010) 122 #define D3_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000b020) 123 124 #define D4_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000b400) 125 #define D4_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000b410) 126 #define D4_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000b420) 127 #define D4_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000b430) 128 129 #define D5_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c000) 130 #define D5_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c010) 131 #define D5_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c020) 132 133 #define D6_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c400) 134 #define D6_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c410) 135 #define D6_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c420) 136 #define D6_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000c430) 137 138 #define D7_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c800) 139 #define D7_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c810) 140 #define D7_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c820) 141 142 #define D8_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000d000) 143 #define D8_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000d010) 144 #define D8_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000d020) 145 #define D8_SADR_REG MIPS_PHYS_TO_KSEG1(0x1000d080) 146 147 #define D9_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000d400) 148 #define D9_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000d410) 149 #define D9_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000d420) 150 #define D9_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000d430) 151 #define D9_SADR_REG MIPS_PHYS_TO_KSEG1(0x1000d480) 152 153 /* 154 * DMA control 155 */ 156 #define D_CTRL_DMAE 0x00000001 /* all DMA enable/disable */ 157 #define D_CTRL_RELE 0x00000002 /* Cycle stealing on/off */ 158 /* Memory FIFO drain control */ 159 #define D_CTRL_MFD_MASK 0x3 160 #define D_CTRL_MFD_SHIFT 2 161 #define D_CTRL_MFD(x) \ 162 (((x) >> D_CTRL_MFD_SHIFT) & D_CTRL_MFD_MASK) 163 #define D_CTRL_MFD_CLR(x) \ 164 ((x) & ~(D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT)) 165 #define D_CTRL_MFD_SET(x, val) \ 166 ((x) | (((val) << D_CTRL_MFD_SHIFT) & \ 167 (D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT))) 168 #define D_CTRL_MFD_DISABLE 0 169 #define D_CTRL_MFD_VIF1 2 170 #define D_CTRL_MFD_GIF 3 171 172 /* Stall control source channel */ 173 #define D_CTRL_STS_MASK 0x3 174 #define D_CTRL_STS_SHIFT 4 175 #define D_CTRL_STS(x) \ 176 (((x) >> D_CTRL_STS_SHIFT) & D_CTRL_STS_MASK) 177 #define D_CTRL_STS_CLR(x) \ 178 ((x) & ~(D_CTRL_STS_MASK << D_CTRL_STS_SHIFT)) 179 #define D_CTRL_STS_SET(x, val) \ 180 ((x) | (((val) << D_CTRL_STS_SHIFT) & \ 181 (D_CTRL_STS_MASK << D_CTRL_STS_SHIFT))) 182 #define D_CTRL_STS_NONE 0 183 #define D_CTRL_STS_SIF0 1 184 #define D_CTRL_STS_FROMSPR 2 185 #define D_CTRL_STS_FROMIPU 3 186 187 /* Stall control drain channel */ 188 #define D_CTRL_STD_MASK 0x3 189 #define D_CTRL_STD_SHIFT 6 190 #define D_CTRL_STD(x) \ 191 (((x) >> D_CTRL_STD_SHIFT) & D_CTRL_STD_MASK) 192 #define D_CTRL_STD_CLR(x) \ 193 ((x) & ~(D_CTRL_STD_MASK << D_CTRL_STD_SHIFT)) 194 #define D_CTRL_STD_SET(x, val) \ 195 ((x) | (((val) << D_CTRL_STD_SHIFT) & \ 196 (D_CTRL_STD_MASK << D_CTRL_STD_SHIFT))) 197 #define D_CTRL_STD_NONE 0 198 #define D_CTRL_STD_VIF1 1 199 #define D_CTRL_STD_GIF 2 200 #define D_CTRL_STD_SIF1 3 201 202 /* 203 * Release cycle 204 * for burst channel Cycle steanling on mode only. 205 */ 206 #define D_CTRL_RCYC_MASK 0x7 207 #define D_CTRL_RCYC_SHIFT 8 208 #define D_CTRL_RCYC(x) \ 209 (((x) >> D_CTRL_RCYC_SHIFT) & D_CTRL_RCYC_MASK) 210 #define D_CTRL_RCYC_CLR(x) \ 211 ((x) & ~(D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT)) 212 #define D_CTRL_RCYC_SET(x, val) \ 213 ((x) | (((val) << D_CTRL_RCYC_SHIFT) & \ 214 (D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT))) 215 #define D_CTRL_RCYC_CYCLE(x) (8 << (x)) 216 217 /* 218 * Interrupt status register (write clear/invert) 219 * DMAC interrupt line connected to MIPS HwINT1 220 */ 221 /* MFIFO empty interrupt enable */ 222 #define D_STAT_MEIM 0x40000000 223 /* DMA stall interrupt enable */ 224 #define D_STAT_SIM 0x20000000 225 /* Channel interrupt enable */ 226 #define D_STAT_CIM_MASK 0x3ff 227 #define D_STAT_CIM_SHIFT 16 228 #define D_STAT_CIM(x) (((x) >> D_STAT_CIM_SHIFT) & D_STAT_CIM_MASK) 229 #define D_STAT_CIM_BIT(x) ((1 << (x)) << D_STAT_CIM_SHIFT) 230 #define D_STAT_CIM9 0x02000000 231 #define D_STAT_CIM8 0x01000000 232 #define D_STAT_CIM7 0x00800000 233 #define D_STAT_CIM6 0x00400000 234 #define D_STAT_CIM5 0x00200000 235 #define D_STAT_CIM4 0x00100000 236 #define D_STAT_CIM3 0x00080000 237 #define D_STAT_CIM2 0x00040000 238 #define D_STAT_CIM1 0x00020000 239 #define D_STAT_CIM0 0x00010000 240 /* BUSERR interrupt status */ 241 #define D_STAT_BEIS 0x00008000 242 /* MFIFO empty interrupt status */ 243 #define D_STAT_MEIS 0x00004000 244 /* DMA stall interrupt status */ 245 #define D_STAT_SIS 0x00002000 246 /* Channel interrupt status */ 247 #define D_STAT_CIS_MASK 0x3ff 248 #define D_STAT_CIS_SHIFT 0 249 #define D_STAT_CIS_BIT(x) (1 << (x)) 250 #define D_STAT_CIS9 0x00000200 251 #define D_STAT_CIS8 0x00000100 252 #define D_STAT_CIS7 0x00000080 253 #define D_STAT_CIS6 0x00000040 254 #define D_STAT_CIS5 0x00000020 255 #define D_STAT_CIS4 0x00000010 256 #define D_STAT_CIS3 0x00000008 257 #define D_STAT_CIS2 0x00000004 258 #define D_STAT_CIS1 0x00000002 259 #define D_STAT_CIS0 0x00000001 260 261 /* 262 * Priority control register. 263 */ 264 /* Priority control enable */ 265 #define D_PCR_PCE 0x80000000 266 /* Channel DMA enable (packet priority control enable) */ 267 #define D_PCR_CDE_MASK 0x3ff 268 #define D_PCR_CDE_SHIFT 16 269 #define D_PCR_CDE(x) \ 270 (((x) >> D_PCR_CDE_SHIFT) & D_PCR_CDE_MASK) 271 #define D_PCR_CDE_CLR(x) \ 272 ((x) & ~(D_PCR_CDE_MASK << D_PCR_CDE_SHIFT)) 273 #define D_PCR_CDE_SET(x, val) \ 274 ((x) | (((val) << D_PCR_CDE_SHIFT) & \ 275 (D_PCR_CDE_MASK << D_PCR_CDE_SHIFT))) 276 #define D_PCR_CDE9 0x02000000 277 #define D_PCR_CDE8 0x01000000 278 #define D_PCR_CDE7 0x00800000 279 #define D_PCR_CDE6 0x00400000 280 #define D_PCR_CDE5 0x00200000 281 #define D_PCR_CDE4 0x00100000 282 #define D_PCR_CDE3 0x00080000 283 #define D_PCR_CDE2 0x00040000 284 #define D_PCR_CDE1 0x00020000 285 #define D_PCR_CDE0 0x00010000 286 /* COP control (interrupt status connect to CPCOND[0] or not) */ 287 #define D_PCR_CPC_MASK 0x3ff 288 #define D_PCR_CPC_SHIFT 0 289 #define D_PCR_CPC(x) ((x) & D_PCR_CPC_MASK) 290 #define D_PCR_CPC_CLR(x) ((x) & ~D_PCR_CPC_MASK) 291 #define D_PCR_CPC_SET(x, val) ((x) | ((val) & D_PCR_CPC_MASK)) 292 #define D_PCR_CPC_BIT(x) (1 << (x)) 293 #define D_PCR_CPC9 0x00000200 294 #define D_PCR_CPC8 0x00000100 295 #define D_PCR_CPC7 0x00000080 296 #define D_PCR_CPC6 0x00000040 297 #define D_PCR_CPC5 0x00000020 298 #define D_PCR_CPC4 0x00000010 299 #define D_PCR_CPC3 0x00000008 300 #define D_PCR_CPC2 0x00000004 301 #define D_PCR_CPC1 0x00000002 302 #define D_PCR_CPC0 0x00000001 303 304 /* 305 * Interleave size register 306 */ 307 /* Transfer quadword counter */ 308 #define D_SQWC_TQWC_MASK 0xff 309 #define D_SQWC_TQWC_SHIFT 16 310 #define D_SQWC_TQWC(x) \ 311 (((x) >> D_SQWC_TQWC_SHIFT) & D_SQWC_TQWC_MASK) 312 #define D_SQWC_TQWC_CLR(x) \ 313 ((x) & ~(D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT)) 314 #define D_SQWC_TQWC_SET(x, val) \ 315 ((x) | (((val) << D_SQWC_TQWC_SHIFT) & \ 316 (D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT))) 317 /* Skip quadword counter */ 318 #define D_SQWC_SQWC_MASK 0xff 319 #define D_SQWC_SQWC_SHIFT 0 320 #define D_SQWC_SQWC(x) \ 321 (((x) >> D_SQWC_SQWC_SHIFT) & D_SQWC_SQWC_MASK) 322 #define D_SQWC_SQWC_CLR(x) \ 323 ((x) & ~(D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT)) 324 #define D_SQWC_SQWC_SET(x, val) \ 325 ((x) | (((val) << D_SQWC_SQWC_SHIFT) & \ 326 (D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT))) 327 328 /* 329 * Ring buffer address register 330 * 16byte alignment address [30:4] 331 */ 332 333 /* 334 * Ring buffer size register 335 * must be 2 ** n qword. [30:4] 336 */ 337 338 /* 339 * Stall address register 340 * [30:0] (qword alignment) 341 */ 342 343 /* 344 * DMA suspend register 345 */ 346 #define D_ENABLE_SUSPEND 0x00010000 347 348 349 /* 350 * Channel specific register. 351 */ 352 353 /* CHANNEL CONTROL REGISTER */ 354 /* upper 16bit of DMA tag last read. */ 355 #define D_CHCR_TAG_MASK 0xff 356 #define D_CHCR_TAG_SHIFT 16 357 #define D_CHCR_TAG(x) \ 358 (((x) >> D_CHCR_TAG_SHIFT) & D_CHCR_TAG_MASK) 359 #define D_CHCR_TAG_CLR(x) \ 360 ((x) & ~(D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT)) 361 #define D_CHCR_TAG_SET(x, val) \ 362 ((x) | (((val) << D_CHCR_TAG_SHIFT) & \ 363 (D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT))) 364 /* DMA start */ 365 #define D_CHCR_STR 0x00000100 366 /* Tag interrupt enable (IRQ bit of DMAtag) */ 367 #define D_CHCR_TIE 0x00000080 368 /* Tag transfer enable (Source chain mode only) */ 369 #define D_CHCR_TTE 0x00000040 370 /* Address stack pointer */ 371 #define D_CHCR_ASP_MASK 0x3 372 #define D_CHCR_ASP_SHIFT 4 373 #define D_CHCR_ASP(x) \ 374 (((x) >> D_CHCR_ASP_SHIFT) & D_CHCR_ASP_MASK) 375 #define D_CHCR_ASP_CLR(x) \ 376 ((x) & ~(D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT)) 377 #define D_CHCR_ASP_SET(x, val) \ 378 ((x) | (((val) << D_CHCR_ASP_SHIFT) & \ 379 (D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT))) 380 #define D_CHCR_ASP_PUSHED_NONE 0 381 #define D_CHCR_ASP_PUSHED_1 1 382 #define D_CHCR_ASP_PUSHED_2 2 383 /* Logical transfer mode */ 384 #define D_CHCR_MOD_MASK 0x3 385 #define D_CHCR_MOD_SHIFT 2 386 #define D_CHCR_MOD(x) \ 387 (((x) >> D_CHCR_MOD_SHIFT) & D_CHCR_MOD_MASK) 388 #define D_CHCR_MOD_CLR(x) \ 389 ((x) & ~(D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT)) 390 #define D_CHCR_MOD_SET(x, val) \ 391 ((x) | (((val) << D_CHCR_MOD_SHIFT) & \ 392 (D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT))) 393 #define D_CHCR_MOD_NORMAL 0 394 #define D_CHCR_MOD_CHAIN 1 395 #define D_CHCR_MOD_INTERLEAVE 2 396 /* 397 * DMA transfer direction (1 ... from Memory, 0 ... to Memory) 398 * (VIF1, SIF2 only. i.e. `both'-direction channel requires this) 399 */ 400 #define D_CHCR_DIR 0x00000001 401 402 /* 403 * TRANSFER ADDRESS REGISTER (D-RAM address) 404 * 16 byte alignment. In FROMSPR, TOSPR channel, D_MADR_SPR always 0 405 */ 406 #define D_MADR_SPR 0x80000000 407 408 /* 409 * TAG ADDRESS REGISTER (next tag address) 410 * 16 byte alignment. 411 */ 412 #define D_TADR_SPR 0x80000000 413 414 /* 415 * TAG ADDRESS STACK REGISTER (2 stage) 416 * 16 byte alignment. 417 */ 418 #define D_ASR_SPR 0x80000000 419 420 /* 421 * SPR TRANSFER ADDRESS REGISTER (SPR address) 422 * 16 byte alignment. FROMSPR, TOSPR only. 423 */ 424 #define D_SADR_MASK 0x3fff 425 #define D_SADR_SHIFT 0 426 #define D_SADR(x) \ 427 ((u_int32_t)(x) & D_SADR_MASK) 428 /* 429 * TRANSFER SIZE REGISTER 430 * min 16 byte to max 1 Mbyte. 431 */ 432 #define D_QWC_MASK 0xffff 433 #define D_QWC_SHIFT 0 434 #define D_QWC(x) (((x) >> D_QWC_SHIFT) & D_QWC_MASK) 435 #define D_QWC_CLR(x) ((x) & ~(D_QWC_MASK << D_QWC_SHIFT)) 436 #define D_QWC_SET(x, val) \ 437 ((x) | (((val) << D_QWC_SHIFT) & D_QWC_MASK << D_QWC_SHIFT)) 438 439 /* 440 * Source/Destination Chain Tag definition. 441 * SC ... VIF0, VIF1, GIF, toIPU, SIF1, toSPR 442 * DC ... SIF0, fromSPR 443 */ 444 /* 445 * DMA address 446 * At least, 16byte align. 447 * but 64byte align is recommended. because EE D-cache line size is 64byte. 448 * To gain maximum DMA speed, use 128 byte align. 449 */ 450 #define DMATAG_ADDR_MASK 0xffffffff 451 #define DMATAG_ADDR_SHIFT 32 452 #define DMATAG_ADDR(x) \ 453 ((u_int32_t)(((x) >> DMATAG_ADDR_SHIFT) & DMATAG_ADDR_MASK)) 454 #define DMATAG_ADDR_SET(x, val) \ 455 ((dmatag_t)(x) | (((dmatag_t)(val)) << DMATAG_ADDR_SHIFT)) 456 457 #define DMATAG_ADDR32_INVALID(x) ((x) & 0xf) /* 16byte alignment */ 458 459 /* 460 * DMA controller command 461 */ 462 #define DMATAG_CMD_MASK 0xffffffff 463 #define DMATAG_CMD_SHIFT 0 464 #define DMATAG_CMD(x) \ 465 ((u_int32_t)((x) & DMATAG_CMD_MASK)) 466 467 #define DMATAG_CMD_IRQ 0x80000000 468 469 #define DMATAG_CMD_ID_MASK 0x7 470 #define DMATAG_CMD_ID_SHIFT 28 471 #define DMATAG_CMD_ID(x) \ 472 (((x) >> DMATAG_CMD_ID_SHIFT) & DMATAG_CMD_ID_MASK) 473 #define DMATAG_CMD_ID_CLR(x) \ 474 ((x) & ~(DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT)) 475 #define DMATAG_CMD_ID_SET(x, val) \ 476 ((x) | (((val) << DMATAG_CMD_ID_SHIFT) & \ 477 (DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT))) 478 #define DMATAG_CMD_SCID_REFE 0 479 #define DMATAG_CMD_SCID_CNT 1 480 #define DMATAG_CMD_SCID_NEXT 2 481 #define DMATAG_CMD_SCID_REF 3 482 #define DMATAG_CMD_SCID_REFS 4 /* VIF1, GIF, SIF1 only */ 483 #define DMATAG_CMD_SCID_CALL 5 /* VIF0, VIF1, GIF only */ 484 #define DMATAG_CMD_SCID_RET 6 /* VIF0, VIF1, GIF only */ 485 #define DMATAG_CMD_SCID_END 7 486 487 #define DMATAG_CMD_DCID_CNTS 0 /* SIF0, fromSPR only */ 488 #define DMATAG_CMD_DCID_CNT 1 489 #define DMATAG_CMD_DCID_END 7 490 491 #define DMATAG_CMD_PCE_MASK 0x3 492 #define DMATAG_CMD_PCE_SHIFT 26 493 #define DMATAG_CMD_PCE(x) \ 494 (((x) >> DMATAG_CMD_PCE_SHIFT) & DMATAG_CMD_PCE_MASK) 495 #define DMATAG_CMD_PCE_CLR(x) \ 496 ((x) & ~(DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT)) 497 #define DMATAG_CMD_PCE_SET(x, val) \ 498 ((x) | (((val) << DMATAG_CMD_PCE_SHIFT) & \ 499 (DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT))) 500 #define DMATAG_CMD_PCE_NONE 0 501 #define DMATAG_CMD_PCE_DISABLE 2 502 #define DMATAG_CMD_PCE_ENABLE 3 503 504 #define DMATAG_CMD_QWC_MASK 0xffff 505 #define DMATAG_CMD_QWC_SHIFT 0 506 #define DMATAG_CMD_QWC(x) \ 507 (((x) >> DMATAG_CMD_QWC_SHIFT) & DMATAG_CMD_QWC_MASK) 508 #define DMATAG_CMD_QWC_CLR(x) \ 509 ((x) & ~(DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT)) 510 #define DMATAG_CMD_QWC_SET(x, val) \ 511 ((x) | (((val) << DMATAG_CMD_QWC_SHIFT) & \ 512 (DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT))) 513
Indexes created Sun Sep 21 20:09:37 GMT 2025