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    Searched defs:DefIdx (Results 1 - 21 of 21) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.h 141 unsigned DefIdx;
160 return DefIdx-1;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
LiveIntervalCalc.cpp 45 SlotIndex DefIdx =
49 LR.createDeadDef(DefIdx, Alloc);
190 unsigned DefIdx;
193 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
196 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
TargetSchedule.cpp 158 unsigned DefIdx = 0;
162 ++DefIdx;
164 return DefIdx;
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
219 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
222 STI->getWriteLatencyEntry(SCDesc, DefIdx);
238 // If DefIdx does not exist in the model (e.g. implicit defs), then return
244 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
MachineCombiner.cpp 200 int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg());
202 LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx,
RenameIndependentSubregs.cpp 335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef);
336 SlotIndex RegDefIdx = DefIdx.getRegSlot();
InlineSpiller.cpp 641 SlotIndex DefIdx =
646 auto *NewMI = LIS.getInstructionFromIndex(DefIdx);
649 (void)DefIdx;
650 LLVM_DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
651 << *LIS.getInstructionFromIndex(DefIdx));
MachineInstr.cpp 289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
290 if (DefIdx != -1)
291 tieOperands(DefIdx, OpNo);
895 unsigned DefIdx;
896 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
897 OpIdx = DefIdx;
1087 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1099 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1100 MachineOperand &DefMO = getOperand(DefIdx);
1102 assert(DefMO.isDef() && "DefIdx must be a def operand")
    [all...]
MachineVerifier.cpp 248 SlotIndex DefIdx, const LiveRange &LR,
1882 unsigned DefIdx;
1885 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
1886 Reg != MI->getOperand(DefIdx).getReg())
2114 unsigned MONum, SlotIndex DefIdx,
2119 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
2121 if (VNI->def != DefIdx) {
2128 report_context(DefIdx);
2136 report_context(DefIdx);
2140 LiveQueryResult LRQ = LR.Query(DefIdx);
    [all...]
RegisterCoalescer.cpp 834 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg());
835 assert(DefIdx != -1);
837 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
944 SlotIndex DefIdx = UseIdx.getRegSlot();
945 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
948 LLVM_DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
949 assert(DVNI->def == DefIdx);
952 VNInfo *SubDVNI = S.getVNInfoAt(DefIdx);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64CollectLOH.cpp 403 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg());
406 if (DefIdx != OpIdx && (DefInfo.OneUser || DefInfo.MultiUsers))
573 int DefIdx = mapRegToGPRIndex(Def.getReg());
575 if (DefIdx >= 0 && OpIdx >= 0 &&
576 handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx]))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 204 unsigned DefIdx = 0;
208 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
209 IsTiedToChangedOp = OpChanged[DefIdx];
295 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
InlineAsmLowering.cpp 435 unsigned DefIdx = OpInfo.getMatchedOperand();
436 // Find operand with register def that corresponds to DefIdx.
438 for (unsigned i = 0; i < DefIdx; ++i)
472 unsigned Flag = InlineAsm::getFlagWordForMatchingOp(UseFlag, DefIdx);
Utils.cpp 172 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
173 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
174 I.tieOperands(DefIdx, OpI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSubtarget.cpp 495 int DefIdx = -1;
507 DefIdx = OpNum;
510 assert(DefIdx >= 0 && "Def Reg not found in Src MI");
517 DefIdx, *DstI, OpNum));
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXSwapRemoval.cpp 621 int DefIdx = SwapMap[DefMI];
622 (void)EC->unionSets(SwapVector[DefIdx].VSEId,
626 SwapVector[DefIdx].VSEId,
725 int DefIdx = SwapMap[DefMI];
727 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
728 SwapVector[DefIdx].IsStore) {
734 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": ");
801 int DefIdx = SwapMap[DefMI];
802 SwapVector[DefIdx].WillRemove = 1
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizationArtifactCombiner.h 525 unsigned DefIdx = 0;
529 ++DefIdx;
532 return DefIdx;
629 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs;
630 ++j, ++DefIdx)
631 DstRegs.push_back(MI.getOperand(DefIdx).getReg());
682 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) {
684 for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRegStackify.cpp 650 SlotIndex DefIdx = LIS.getInstructionIndex(*Def).getRegSlot();
656 LiveInterval::iterator I = LI.FindSegmentContaining(DefIdx);
657 VNInfo *ValNo = LI.getVNInfoAt(DefIdx);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/
MIParser.cpp 1462 unsigned DefIdx = Operands[I].TiedDefIdx.getValue();
1463 if (DefIdx >= E)
1466 Twine(DefIdx) + "'; instruction has only ") +
1468 const auto &DefOperand = Operands[DefIdx].Operand;
1473 Twine(DefIdx) + "'; the operand #" + Twine(DefIdx) +
1477 if (TiedPair.first == DefIdx)
1479 Twine("the tied-def operand #") + Twine(DefIdx) +
1482 TiedRegisterPairs.push_back(std::make_pair(DefIdx, I));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 2388 SlotIndex DefIdx;
2409 DefIdx = V->def;
2416 if (!DefIdx.isValid() ||
2417 MDT.dominates(LIS->getInstructionFromIndex(DefIdx),
2419 DefIdx = V->def;
2426 MachineInstr *Def = LIS->getInstructionFromIndex(DefIdx);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 5498 unsigned DefIdx = 0;
5502 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
5503 IsTiedToChangedOp = OpChanged[DefIdx];
5589 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
ARMISelLowering.cpp 11701 int DefIdx = MCID->getOperandConstraint(i, MCOI::TIED_TO);
11702 if (DefIdx != -1)
11703 MI.tieOperands(DefIdx, i);

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